JPH06104731A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To detect the defect of an ECL circuit with high efficiency in a test mode with high stability and with no change of temperature. CONSTITUTION:A constant current circuit 8 supplies the constant currents I01 and I02 to apply the bias currents I3...In to the ECL circuits E3...En. A test terminal 10 inputs a control signal from the outside, and a selection switch 9 selects both currents I01 and I02 of the circuit 8 based on the control signal. The switch 9 selects a test constant current I02 smaller than the level of a normal mode for detection of the defects of the circuits E3...En. In such a constitution, the constant current of the circuit 8 is selected by the external control and a bias current smaller than the level of a normal mode is applied to the ECL circuits to reduce the logical amplitude of the ECL circuit. Thus it is possible to detect the defect of the ECL circuit with high efficiency in a stable state and with no change of the temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which can easily test a defect of an ECL circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional semiconductor integrated circuit IC100 having ECL circuits E3 ... En.
Is a power supply terminal of the IC 100, 2 is a constant current circuit, 3 is a constant voltage circuit.
The electric power is supplied to the ECL circuits E3 ... En and the constant current circuit 2 to supply a constant voltage Vr. Also I
C100 is an NPN transistor Q3 which supplies bias currents I3 ..., In to the ECL circuits E3.
,, Qn, and the value of bias current I3 ,, In is NP
It is controlled by N transistors Q1 and Q2, and a constant current I is applied to the collector of the transistor Q1 by a constant current circuit 2.
0 is shed. That is, the transistors Q1 ..., Qn form a current mirror circuit together with the resistors R2 ..., Rn, and the constant current I0 and the bias currents I3 ..., In are equal to each other, and I0 = I3 = ... = In ... (1) Have a relationship.

FIG. 5 shows an ECL circuit E3 shown in FIG. 4, an ECL circuit E4 at the next stage directly connected to the ECL circuit E3,
It is a circuit diagram showing the vicinity thereof, and the ECL circuit E3 is an NPN.
Transistors Q31, Q32 and these transistors Q31, Q
The ECL circuit E4 is composed of NPN transistors Q41 and Q42 and a resistor R0, like the ECL circuit E3. The first input terminal 4 and the second input terminal 5 are signal lines in the IC100 circuit for applying a potential to the ECL circuit E3, and the first output terminal 6
And the second output terminal 7 inputs the output signal of the ECL circuit E4 to the adjacent ECL circuit E5 (not shown) and
This is a terminal for taking out the potential generated in the circuit E4, and each ECL
It is provided between circuits.

FIG. 6 shows the ECL circuit E3 shown in FIG.
FIG. 7 is a waveform diagram showing the normal operation of E4. FIGS. 7 and 8 show ECL circuits E3 and E4 when the transistor Q32 is defective.
6 is a waveform diagram showing the operation of FIG.

Next, the operation will be described. In the conventional semiconductor integrated circuit IC100 configured as described above, as shown in FIG.
As shown in (A), when the potential Vr-.DELTA.V is applied to the first input terminal 4 of the ECL circuit E3 and the potential Vr is applied to the second input terminal 5, it is the collector of the transistor Q31. The potential of a becomes Vr, and the potential of the point b, which is the collector of the transistor Q32, becomes Vr-.DELTA.V.

Further, at this time, I0 =
From the relationship of I3 = ... = In, the voltage difference .DELTA.V in the logic state is .DELTA.V = R0.times.I0 (2), and as shown in FIG. 5, the potential Vr at the point a is at the base of the transistor Q42 and at the point b. Is applied to the base of the transistor Q41, the potential of the first output terminal 6 becomes Vr, and the potential of the second output terminal 7 becomes Vr.
r −ΔV.

Similarly, when the potentials Vr and Vr-ΔV are applied to the input terminals 4 and 5, respectively, as shown in FIG.
As shown in (B), the potential at the point a becomes Vr-ΔV,
The potential at point b is Vr. And at the output terminals 6 and 7,
The potentials Vr-ΔV and Vr are output, respectively.

In the IC 100 operating in this way,
For example, if the transistor Q32 of the ECL circuit E3 is defective, it is assumed that the collector of the transistor Q32 has a resistance value of R1 with respect to GND regardless of the potential of the input terminal 5 and a constant current I1 flows through it. The potential of the collector of is fixed to Vr-ΔVf, and the voltage difference ΔVf in the defective state is ΔVf = R0 × I1 (3).

Here, the relationship between ΔVf and ΔV is ΔVf>
When ΔV, as shown in FIG.
When the potentials Vr-.DELTA.V and Vr are applied to the respective points 5, the potentials at the points a and b become Vr and Vr-.DELTA.Vf, and Vr> Vr.
From −ΔVf, the potential at the point a is higher than the potential at the point b, and the potentials Vr and Vr −ΔV are output to the output terminals 6 and 7, respectively. On the other hand, the potentials Vr and Vr are applied to the input terminals 4 and 5, respectively.
When −ΔV is applied, as shown in FIG.
The potential of b becomes Vr-ΔV, Vr-ΔVf, and ΔVf>
From the relationship of ΔV, Vr −ΔV> Vr −ΔVf, and the potential at the point a is higher than the potential at the point b. In any case, the potentials Vr and Vr −ΔV are output to the output terminals 6 and 7, respectively. .

As described above, when ΔVf> ΔV, the base potential of the transistor Q41, that is, the potential at the point b is always lower than the potential of the base of the transistor Q42, that is, the potential at the point a, and the potentials of the input terminals 4 and 5. The potential of the point b cannot be controlled due to the change of the above, and the defect of the transistor Q32 is detected.

However, when ΔVf <ΔV, the condition shown in FIG.
As shown in (A), the potential V is applied to the input terminals 4 and 5, respectively.
When r −ΔV and Vr are applied, the potentials at points a and b are Vr.
, Vr−ΔVf, and from Vr> Vr−ΔVf to point a
Is higher than the potential at the point b, and the potentials Vr and Vr-.DELTA.V are output to the output terminals 6 and 7, respectively. On the other hand, FIG.
As shown in (B), the potential V is applied to the input terminals 4 and 5, respectively.
When r and Vr-ΔV are applied, the potentials at points a and b become Vr.
−ΔV, Vr −ΔVf, and from the relationship of ΔVf <ΔV, Vr −ΔV <Vr −ΔVf, the potential at point a is lower than the potential at point b, and the potential V is applied to the output terminals 6 and 7, respectively.
r-ΔV and Vr are output.

As described above, when ΔVf <ΔV, the level relationship between the potential at the point a and the potential at the point b is replaced by the change in the potentials at the input terminals 4 and 5, and the potentials at the output terminals 6 and 7 are shown in FIG. The waveform will be the same as when
Although 32 is defective, the ECL circuit will show a normal operating condition. Therefore, transistor Q32
Cannot be identified as defective.

Further, the resistance R0 has a positive temperature characteristic, but the current I0 flowing through the constant current circuit 2 is controlled so as to cancel the characteristic, so that .DELTA.V has a small temperature dependency. However, since there is no such control for the constant current I1, ΔVf
Has a large temperature dependency, and the magnitude relationship between ΔVf and ΔV may change if the temperature at which the ECL circuit is tested differs from the temperature at which it is used. Therefore, even in this case, the defective operation of the transistor Q32 may not be detected by the test.

[0014]

Since the conventional semiconductor integrated circuit is constructed as described above, it is not easy to detect the defect of the ECL circuit by the conventional test, and the temperature is changed during the measurement. There was a need. However, when testing is performed by changing the temperature, there is a problem in that stability and efficiency are poor in terms of temperature control when detecting defects. The present invention has been made to solve the above-described problems, and when detecting a defective operation of an ECL circuit, a semiconductor integrated circuit which is stable without changing the temperature and can be efficiently tested is obtained. The purpose is to

[0015]

A semiconductor integrated circuit according to the present invention is provided with a constant current circuit having a plurality of current values for applying a bias current to an ECL circuit, and at the time of test, a bias current smaller than that in normal time is externally supplied. The selection is made by the control signal from the test terminal to reduce the logic amplitude of the ECL circuit to increase the detection range of the defect in the ECL circuit.

The semiconductor integrated circuit according to the present invention is
A constant voltage circuit having a plurality of voltage values is provided to supply a constant voltage to the ECL circuit, and at the time of testing, a constant voltage higher than the normal time is selected by a control signal from an external test terminal to determine the logical amplitude of the ECL circuit. The size is reduced to increase the defect detection range in the ECL circuit.

Further, in the semiconductor integrated circuit according to the present invention, at the time of testing, the logic amplitude of the ECL circuit is selected by selecting the power supply voltage as the constant voltage in order to give the ECL circuit a constant voltage higher than that in the normal state from the outside. The size is reduced to increase the defect detection range in the ECL circuit.

[0018]

According to the present invention, the constant current of the constant current circuit is logically switched by the control signal input from the external test terminal, and a smaller test bias current is applied to the ECL circuit at the time of the test, so that the logic amplitude of the ECL circuit is increased. Is smaller, the range in which the defect can be detected is increased, and the defective operation of the ECL circuit can be efficiently detected from the outside without changing the temperature.

In the present invention, the constant voltage of the constant voltage circuit is logically switched or the constant voltage is proportional to the power supply voltage by the control signal input from the external test terminal.
At the time of the test, a larger test constant voltage is supplied to the ECL circuit to reduce the logic amplitude of the ECL circuit, so that the range in which the defect can be detected becomes large, and the defective operation of the ECL circuit can be efficiently performed without changing the temperature. Can be detected well.

Further, in the present invention, during the test, the power supply voltage is selected as a constant voltage, and a larger constant voltage is externally applied to reduce the logic amplitude of the ECL circuit. The range becomes large and it becomes possible to detect efficiently.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 is a circuit diagram of a semiconductor integrated circuit IC101 according to a first embodiment of the present invention. The same reference numerals as those in FIGS. 4 and 5 denote the same or corresponding portions, and 8 indicates a constant current I01 for normal use. Sometimes it is a constant current circuit provided with two current outputs for giving a constant current I02 to the current mirror circuit, whereby each ECL circuit E3 ... En.
Bias currents I3 ..., In are supplied to. Reference numeral 9 denotes a selection switch, which is controlled by a control signal input from an externally provided test terminal 10 so that the constant current I01,
Select either I02. Further, FIG. 9 shows a transistor Q
FIG. 9 is a waveform diagram showing the operation of ECL circuits E3 and E4 when 32 is defective.

Here, the control signal "H" is input from the test terminal 10 to the selection switch 9 in the normal state, and the constant current I01 of the constant current circuit 8 is selected by the selection switch 9. It is assumed that the control signal "L" is input from the terminal 10 to the selection switch 9 and the constant current I02 of the constant current circuit 8 is selected. here,
The constant currents I01, I02 have a relationship of I01> I02 (4), and reduce the bias currents I3, ... In during the test as compared with the normal time.

2 in each ECL circuit E3 ... En
The voltage difference between the two logic states is ΔVT = R0 × I02 (5) at the time of test, and ΔVN = R0 × I01 (6) at the normal time. Since there is a relation of equation (4), I01> I02, ΔVN> ΔVT (7), the voltage difference .DELTA.V between the logic states of the ECL circuits E3 ... En becomes small during the test, and the relationship of .DELTA.Vf> .DELTA.VT is established.

Next, the operation will be described. Here, it is assumed that the transistor Q32 of the ECL circuit E3 is defective as in the conventional example, and the relationship of ΔVf = R0 × I1 in the equation (3) is satisfied.

When a control signal "L" is input from the external test terminal 10 to test the operation of the ECL circuit E3, the constant current I02 is selected by the selection switch 9.
Bias currents I3, ..., In are supplied to the ECL circuits E3 ,. Then, as shown in FIG. 9A, when the potentials Vr-.DELTA.VT and Vr are applied to the input terminals 4 and 5, respectively, the potentials at the points a and b become Vr and Vr-.DELTA.Vf, and Vr.
> Vr−ΔVf to output terminals 6 and 7 respectively, and potential V
r, Vr-ΔVT are output. On the other hand, input terminals 4, 5
When the potentials Vr and Vr-ΔVT are applied to the respective points, as shown in FIG. 9B, the potentials at points a and b are Vr-ΔVT.
, Vr −ΔVf, and at this time, ΔVf during normal operation
ΔVN, which had a relationship of <ΔVN, has a relationship of ΔVN> ΔVT in the equation (7) at the time of the test, and ΔVf> ΔVT
From the above, Vr-ΔVT> Vr-ΔVf
Therefore, the potentials Vr and V are similarly applied to the output terminals 6 and 7.
r-ΔVT is output. In this way, the relationship of ΔVf> ΔV as shown in FIG. 7 is established, and the potentials of the output terminals 6 and 7 cannot be controlled by the change of the potentials of the input terminals 4 and 5,
A defect of the transistor Q32 of the ECL circuit E3 is detected.

As described above, in the first embodiment, in order to test the ECL circuit, a bias current smaller than that in the normal state is applied to the ECL circuit to reduce the logical amplitude of the ECL circuit and the relationship of ΔVf> ΔV is established. I decided to do so, so EC
The detectable range of the defect of the L circuit becomes large, the defective operation of the ECL circuit can be efficiently detected by an external operation, and the temperature control is not required, so that the stable detection can be performed.

Example 2. FIG. 2 is a circuit diagram of a semiconductor integrated circuit IC102 according to a second embodiment of the present invention, in which the same reference numerals as those in FIGS. 4 and 5 indicate the same or corresponding portions, and 11
Is a constant voltage circuit which gives a constant voltage Vr1 in a normal state and a constant voltage Vr2 in a test, and the constant voltage Vr1 and Vr2 of the constant voltage circuit 11 are controlled by a control signal inputted from the test terminal 10.
Select one of Also, FIG. 10 shows a transistor Q32.
FIG. 7 is a waveform diagram showing the operation of the ECL circuits E3 and E4 when the signal is defective.

Here, the control signal "H" is input from the test terminal 10 to the selection switch 9 during normal operation, the constant voltage Vr1 of the constant voltage circuit 11 is selected, and during the test, the constant voltage Vr1 is selected from the test terminal 10 to the selection switch 9. On the other hand, it is assumed that the control signal “L” is input and the constant voltage Vr2 of the constant voltage circuit 11 is selected.

Here, the constant voltages Vr1 and Vr2 have a relationship of Vr1 <Vr2 (8), the transistor Q32 of the ECL circuit E3 is defective and the collector of the transistor Q32 is GND as in the prior art example. When a resistance value of R1 is provided between them, ΔVfT = Vr2 × R1 / (R0 + R1) (9) at the time of testing, and ΔVfT is proportional to Vr2. However, since ΔV is determined by the product of the constant current I0 and the resistance R0, the constant voltage Vr2
It is a constant value regardless of Therefore, the constant voltage V
Let r2 be the constant voltage V in the normal state as Vr1 <Vr2 in the equation (8).
By setting the value higher than r1, the relationship of ΔVfT> ΔV is established.

Next, the operation will be described. In the ECL circuits E3 and E4 of the IC 102 according to the second embodiment, as shown in FIG.
, The potential Vr2−Δ is applied to the input terminals 4 and 5, respectively.
When V and Vr2 are applied, the potentials at points a and b are respectively V
r2, Vr2-ΔVfT, and as shown in FIG.
When the potentials Vr2 and Vr2-ΔV are applied to the input terminals 4 and 5, respectively, the potentials at the points a and b are Vr2-ΔV and Vr2-ΔVfT.
Becomes From the relationship of ΔVfT> ΔV, these potentials are Vr2> Vr2-ΔVfT and Vr2-ΔV> Vr2-ΔVfT, and the potential at point a becomes higher than the potential at point b regardless of the potentials at the input terminals 4 and 5. . In this way, the potential of the output terminals 6 and 7 does not change due to the change of the potential applied from the input terminals 4 and 5, and the malfunction of the ECL circuit can be detected.

As described above, in the second embodiment, ΔVfT
Since a constant voltage higher than the normal time is selected and tested so that the relation of> ΔV is established, the range in which the defect of the ECL circuit can be detected becomes large as in the first embodiment.
The same effect can be obtained.

Example 3. FIG. 3 is a circuit diagram of a semiconductor integrated circuit IC103 according to the third embodiment of the present invention. The same reference numerals as those in FIGS. 4 and 5 indicate the same or corresponding parts. In the third embodiment, an input is made from a test terminal 10. A selection switch 9 for short-circuiting the power supply terminal 1 and the constant voltage Vr by the generated control signal is provided. When the control signal "H" is input from the test terminal 10, the selection switch 9 is turned off and opened, When the control signal "L" is input during the test, the selection switch 9 is turned on and closed, and Vcc = Vr.

In the ECL circuit of the IC 103 of the third embodiment, the constant voltage circuit 3 supplies a constant voltage Vr to the ECL circuits E3 ... En and the constant current circuit 2. During the test, the selection switch 9 is on and Vcc = Vr, so
The constant voltage Vr can be freely set from the outside. Therefore, if Vcc is set higher than the constant voltage Vr in the normal condition during the test, Δ
The relationship of Vf> ΔV is established, and the defective operation of the ECL circuit can be detected by an external operation as in the second embodiment.

Example 4. In the semiconductor integrated circuit according to the fourth embodiment of the present invention, in addition to the constant voltage Vr of the constant voltage circuit 3,
It has a circuit that outputs a voltage proportional to the power supply voltage.
At the time of test, receiving the control signal from the test terminal 10,
The selection switch built in the constant voltage circuit 3 is switched from the constant voltage Vr at the normal time to a voltage proportional to the power supply voltage, and by supplying Vcc higher than the constant voltage at the normal time, a voltage proportional to this Vcc. Each ECL circuit E3 ... En
I am trying to give it to.

In such a semiconductor integrated circuit, the third embodiment
It is not always necessary to short circuit Vcc and constant voltage Vr as shown in, and by giving Vr proportional to Vcc,
Similar tests can be performed with similar effects.

[0036]

As described above, according to the semiconductor integrated circuit of the present invention, it is possible to reduce the logical amplitude of the ECL circuit by switching the constant current value of the constant current circuit by an external control signal. Since the bias current is selected for the test, and the bias current is given to the ECL circuit for the test, the range in which the defect of the ECL circuit can be detected can be increased and the accuracy can be improved, and the ECL circuit can be operated by an external operation. The defective operation can be detected efficiently and easily, and since temperature control is not required, there is an effect that stable detection can be performed.

Further, according to the semiconductor integrated circuit of the present invention, the EC voltage can be switched by switching the constant voltage value of the constant voltage circuit or by making the constant voltage proportional to the power supply voltage in accordance with an external control signal.
Since a larger constant voltage that reduces the logical amplitude of the L circuit is selected for testing and is supplied to the ECL circuit for testing, the same effect as described above can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional semiconductor integrated circuit.

5 is a circuit diagram showing the ECL circuit of FIG. 4. FIG.

6 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 7 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 8 is a waveform diagram for explaining the operation of the circuit of FIG.

9 is a waveform chart for explaining the operation of the circuit of FIG.

10 is a waveform chart for explaining the operation of the circuit of FIG.

[Explanation of symbols] 1 power supply terminal 2 constant current circuit 3 constant voltage circuit 4 first input terminal 5 second input terminal 6 first output terminal 7 second output terminal 8 constant current circuit 9 selection switch 10 test terminal 11 constant voltage circuit 100 IC 101 IC 102 IC 103 IC I01 constant current I02 constant current Vr1 constant voltage Vr2 constant voltage E3 to En ECL circuit I3 to In bias current Q1 to Qn NPN transistor R2 to Rn resistance

Claims (8)

[Claims] 1. A semiconductor integrated circuit comprising an emitter-coupled logic (hereinafter referred to as ECL) circuit, a constant current circuit for giving any one of bias currents having a current value of 2 or more to the ECL circuit, and the constant current circuit. A switch for switching between two or more current values of the current circuit, and a test terminal for inputting a control signal from the outside to the switch are provided, and the plurality of switches are provided by the control signal input from the test terminal. The semiconductor integrated circuit is characterized in that the defect detectable range of the ECL circuit can be increased by selecting any one of the bias currents for testing. 2. The semiconductor integrated circuit according to claim 1, wherein a bias current smaller than that in a normal state is selected at the time of a test to reduce a logic amplitude of the ECL circuit and increase a detectable range. Semiconductor integrated circuit. 3. A semiconductor integrated circuit comprising an ECL circuit, wherein a constant voltage circuit for giving any of the constant voltages having a voltage value of 2 or more to the ECL circuit, and a constant voltage circuit of 2 or more voltage values of the constant voltage circuit. A changeover switch for switching either one and a test terminal for inputting a control signal to the switch from the outside are provided, and one of the plurality of constant voltages is selected according to the control signal input from the test terminal. Is selected for testing, the range in which the defect of the ECL circuit can be detected can be increased. 4. The semiconductor integrated circuit according to claim 3, wherein a constant voltage larger than a normal time is selected at the time of a test to reduce the logic amplitude of the ECL circuit and increase the detectable range. Semiconductor integrated circuit. 5. A semiconductor integrated circuit comprising an ECL circuit, and a changeover switch for changing a constant voltage of a constant voltage circuit given to the ECL circuit at a normal time to a power supply voltage, and a control signal to the switch from the outside. And a test terminal for inputting, and by selecting a power supply voltage as a test voltage by a control signal input from the test terminal, it is possible to increase a detectable range of the defect of the ECL circuit. Semiconductor integrated circuit. 6. The semiconductor integrated circuit according to claim 5, wherein at the time of a test, a power supply voltage higher than a constant voltage at a normal time is applied to the ECL circuit, thereby reducing the logical amplitude of the ECL circuit and enabling the detection. A semiconductor integrated circuit having a large range. 7. A semiconductor integrated circuit comprising an ECL circuit, and a constant voltage circuit for applying to the ECL circuit any one of a constant voltage at a normal time and a voltage proportional to a power supply voltage, and a constant voltage at a normal time. A test terminal for externally inputting a control signal for switching between a voltage proportional to the power supply voltage and a voltage is provided, and a voltage proportional to the power supply voltage is selected for a test by the control signal input from the test terminal. By
A semiconductor integrated circuit characterized in that a detectable range of defects of the ECL circuit can be increased. 8. The semiconductor integrated circuit according to claim 7, wherein during a test, a power supply voltage higher than a normal constant voltage is supplied to the constant voltage circuit, and a voltage proportional to the power supply voltage is applied to the ECL circuit. As a result, the semiconductor integrated circuit is characterized in that the logic amplitude of the ECL circuit is reduced and the detectable range is increased.