JPH06104697A - Programmable digital filter - Google Patents

Abstract

PURPOSE:To obtain the digital filter by which an inexpensive ghost canceller is formed by reducing number of components of the circuit for the digital filter. CONSTITUTION:640-Sets of delay registers 20 are connected to form a shift register 18. Each output terminal of each delay register 20 is provided with a tap. 16-Taps are connected respectively to 64-sets of selectors 24, one tap is selected among 16 taps by each selector 24 and a signal from the tap is fed to a correspondent multiplier 22. The multiplier 22 multiplies the applied signal with a prescribed coefficient. The coefficient is set on a coefficient register 23 externally provided corresponding to the multiplier 22. The value is set on a selection register 26 externally and which tap is to be selected by the selector 24 based on the value is determined. Thus, number of the multipliers 22 is reduced for the 640-sets of delay registers 20.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to digital filters. In particular, the present invention relates to a programmable digital filter in which each coefficient is programmable and used in a ghost canceller for television broadcasting and the like.

[0002]

2. Description of the Related Art The ghost phenomenon caused by reflected radio waves from high-rise buildings has become a major obstacle to reception since the early days of television broadcasting. Various measures have been attempted in order to solve this problem, but none of them have produced satisfactory results, and elimination of ghosts has been a long-standing problem for television engineers.

At the Telecommunications Technology Council in March 1989, the ghost cancellation reference signal (GCR) established by the Broadcasting Technology Development Association (BTA) was approved as a standard system in Japan. And from the fall of the same year, this GCR
Clear vision broadcasting was started with one of the features of ghost elimination using.

In this clear vision broadcast, the above-mentioned reference signal (GCR) is inserted during the vertical blanking period, and the television receiver receives this GCR and the reference signal created in the receiver is used. By comparing, it is possible to determine what kind of reflected wave is generated.
If a video signal is processed using a programmable digital filter in which each coefficient is set based on this judgment, a ghost-free video signal can be obtained. The video signal must be A before input to this programmable digital filter.
It is digitized by the / D converter, output from the filter, and then converted into an analog signal by the D / A converter.

FIG. 8 shows a block diagram of a conventional typical ghost canceller. As shown in the figure, this ghost canceller has a structure in which five 128-tap transversal filters 10 are combined. The transversal filter 10a constitutes a 128-tap FIR filter, and mainly removes the proximity ghost. In addition, the transversal filters 10b to 10b
e is connected so as to form a loop as a whole, and forms an IIR type filter. This IIR filter mainly removes distant ghosts.

FIG. 9 shows a circuit configuration diagram of the transversal filter 10. As shown in FIG. 9, the transversal filter 10 by itself is FI.
It is an R-type digital filter. The number of stages is 128 as described above. That is, the delay register,
128 multipliers, coefficient registers, and adders are provided. Therefore, the ghost canceller shown in FIG. 8 has a total of about 640 taps.

The reflected wave forming the ghost can be detected up to the maximum horizontal scanning time as its delay time. Therefore, the ghost canceller must be a digital filter capable of realizing the maximum time, that is, a signal delay of about 40 μsec. I won't.

From the above, the delay time per stage of the ghost canceller shown in FIG. 8 is about 70n.
Set to seconds. Therefore, this ghost canceller can realize a maximum delay time of 44.8 μsec (70 nsec × 640).

Next, examples of actual products will be given. FIG. 10 shows a circuit configuration diagram of a ghost canceller used in an actual TV tuner (Sunada et al .:
"Ghost Removal Tuner" Ghost Clear "GCT-1
000 ", broadcasting technology, pp1175-1182, 198.
December 9th). The ghost canceller shown here is a ghost canceller having substantially the same configuration as the ghost canceller shown in FIG. 8, and each transversal filter is arranged so as to be arranged according to the situation of the ghost. The amount of delay between them is adjusted. That is,
A variable delay line is provided between the stages to adjust the delay time between the stages. The coefficient calculation of each stage is performed by using a 16-bit CPU.

[0010]

Since the conventional ghost canceller is constructed as described above, a digital filter having an extremely large number of taps is required. For example, the ghost canceller shown in FIG. 8 requires five transversal filters each having 128 taps, resulting in an extremely expensive device. Also this 1
When the 28-tap transversal filter operates, C
Even in MOS, the power consumption is 1 W or more, so a special IC
A package is required, and the heat radiation design of the television receiver is also special.

The present invention has been made in view of the above problems, and an object thereof is to obtain a digital filter which can reduce the number of parts constituting a circuit and can form an inexpensive ghost canceller.

[0012]

In order to solve the above-mentioned problems, a first invention is a shift register for delaying an input signal, which is constituted by connecting a plurality of registers in series. Each of the registers is provided with a tap at its output end, and each tap outputs a signal having a different delay time, and a shift register connected to an arbitrary number of taps of the plurality of taps. A plurality of selectors that select any one of the taps and output signals from the selected taps; and a plurality of selectors that are provided for each of the selectors and that hold coefficients that are multiplied by the signals output from the selectors. Coefficient register and each selector, which is provided for each selector and multiplies the signal output by each selector by the coefficient held in each coefficient register. A multiplier of a number, each coefficient register holds a coefficient supplied from the outside, and each selector selects one of the connected taps by an external command. It is a programmable digital filter characterized by the above.

Therefore, the selector can arbitrarily select a signal having a desired delay time to be multiplied.

In order to solve the above-mentioned problems, the second aspect of the present invention is, in the programmable digital filter of the first aspect of the present invention, that the delay time is long from the low-order side tap from which a signal with a short delay time is output. The programmable digital filter is characterized in that the number of the selectors to which the taps are connected is sequentially reduced toward the high-order side taps from which signals are output.

Therefore, the signal with the smaller delay time can be more densely selected as the object of multiplication.

In order to solve the above-mentioned problems, a third aspect of the present invention is a shift register for delaying an input signal, wherein a predetermined number of variable length shift registers whose delay time can be changed are connected in series. A shift register which is provided with an output terminal of each variable length register, and outputs a signal with a different delay time from each tap, and a signal which is provided for each tap and is output from the tap. A coefficient register holding a count to be multiplied,
A multiplier that is provided for each tap and that multiplies the output signal from the tap by the coefficient held in the corresponding coefficient register, and the coefficient register holds the coefficient supplied from the outside. However, the delay time of the variable-length shift register is changed by a command from the outside, which is a programmable digital filter.

Therefore, by varying the delay amount of the variable length shift register, it is possible to arbitrarily select the signal to be multiplied, as in the first aspect of the present invention.

In order to solve the above-mentioned problems, a fourth aspect of the present invention is a programmable digital filter according to the third aspect of the present invention, in which a two-phase clock delay register constituting a variable length shift register is clocked by an external command. Is a programmable digital filter characterized by allowing the input signal to pass without delay.

Therefore, similarly to the third aspect of the present invention, it is possible to arbitrarily select the signal to be multiplied.

[0020]

The selector according to the first aspect of the present invention selects a signal from a desired tap by a signal from the outside. Therefore, it is possible to target only the signal having the desired delay time.

In the second aspect of the present invention, the number of selectors to which the taps are connected is larger in the low-order side taps than in the high-order side taps, so the low-order side taps should be selected more densely. Is possible. That is, the signal with the shorter delay time can be subjected to multiplication with more signals than the signal with the longer delay time.

In the variable length shift register according to the third aspect of the present invention, when the delay time is changed by a command from the outside, the delay of the signal output by the tap provided at the output end of each variable length shift register. The time is changed. That is, it is possible to arbitrarily select the delay time of the signal to be multiplied.

The fourth aspect of the present invention is the same as the third aspect of the present invention.
It is possible to arbitrarily select the delay time of the signal to be multiplied. Further, in the method of selecting the delay amount of the variable length shift register by the selector, at least 5120 selectors and buffers of 5120 gates for 640 taps are required for an 8-bit input signal.
It can be realized only by the gate.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a partial circuit diagram of a programmable digital filter according to Embodiment 1 of the present invention. In this embodiment, the input signal input to the shift register 18 is an 8-bit parallel signal, and the video signals of the respective delay registers 20 constituting the shift register 18 are all input / output by 8-bit parallel input / output. . In the figure, the shift register 18
Is the lower part of the delay register 20 and the uppermost part (640
Only the (th) delay register 20 is shown in the figure, and the other parts are omitted and not shown. 64 multipliers 22 and 64 coefficients a are provided. Coefficient a
Is supplied by the output signal of the 8-bit coefficient register 23 and is multiplied by the video signal in the multiplier 22. The sum of the multiplication output from each multiplier 22 is obtained by the adder, and the sum is output to the outside as the final output of the digital filter.

The value of this coefficient a is (not shown).
It is set in the coefficient register 23 from the outside. Further, the video signal multiplied by the coefficient a in each multiplier 22 is the selector 2 provided corresponding to each multiplier 22.
Selected by 4. One selector 24 is provided for each multiplier 22, and a total of 64 selectors 24 are provided. Each selector 24 has 16 8-bit input terminals, and the output terminals of the above-mentioned delay register, that is, predetermined 16 taps of the output taps are connected to the input terminals. Then, the selector 24 selects one tap of the video signal to be multiplied by the coefficient a from the 16 connected taps, and supplies the video signal to the corresponding multiplier 22. Which selector each tap is connected to is set for each tap and each selector 24. That is, the user cannot freely determine which video signal the selector 14 selects as a selection candidate. The user selects a desired video signal from the candidate video signals.

It is the 4-bit selection register 26 that determines which video signal the selector 24 selects, and the user rewrites the value of this register to the selector 24 so that the video of the desired delay time is displayed. The signal can be selected. When the present programmable digital filter is used, for example, in a ghost canceller of a television receiver, the value of the selection register 26 is set by the control unit in the television receiver in the same manner as the coefficient register 23 that holds the coefficient a. It will be set and controlled to cancel the reflected wave.

In this embodiment, only 64 multipliers 22 are provided for the 640 delay registers 20. Therefore, video signals with 640 kinds of delay times cannot be simultaneously multiplied. However, since the video signals that are multiplied by the 64 multipliers 22 are respectively selected from the 16 candidates by the selector 24, the video signals of all delay times are input to the multipliers as described later. there is a possibility.

When the programmable digital filter is used in a ghost canceller, the number of reflected waves is about several tens at most. Therefore, the above 640 coefficients a in the conventional programmable digital filter are
Most of them were "0". In the present embodiment, in consideration of such a fact, the number of multipliers (equal to the coefficient a) is reduced to 64. That is, 64 signals can be selected from video signals of 640 kinds of delay times.

By the way, if the number of delay registers is reduced to 64, the time accuracy for canceling the reflected wave deteriorates.
The number of delay registers itself remains 640, which is the same as the conventional one. In the first place, reducing the number of delay registers to 64 is the same as simply reducing the number of stages of conventional digital filters.

The 64 signals to be supplied to the multiplier from the output signals of the 640 delay registers are the selector 2
Selected by 4. Therefore, it is possible to reduce the number of components without deteriorating the accuracy of canceling the reflected wave (without reducing the number of delay registers).

Each selector 24 selects one signal from 16 specific video signals.
Signals selected by each selector 24 (that is, the selector 2
The following is an example of the setting of signals connected to No. 4). In the example shown below, Sn (n = 1, ..., 640) represents the tap of the n-th delay register 20.

Input of selector 24-1 S1 to S16 Input of selector 24-2 S2 to S17 Input of selector 24-3 S3 to S18 Input of selector 24-4 S4 to S19 Input of selector 24-5 S6 to S21 Selector 24 -6 input S8 to S23 selector 24-7 input S10 to S25 selector 24-8 input S12 to S27 selector 24-9 input S15 to S30 selector 24-10 input S18 to S33 selector 24-11 input S21 ~ S36 Input of selector 24-12 S24 ~ S39 Input of selector 24-13 S28 ~ S43 Input of selector 24-14 S32 ~ S47 Input of selector 24-15 S36 ~ S51 Input of selector 24-16 S40 ~ S55 Selector 24- 17 inputs S45 to S70 selector 24-18 input S50 to S75 selector 24-19 input S55 to S80 selector 24-20 input 60 to S85 Input of selector 24-21 S66 to S81 Input of selector 24-22 S72 to S87 Input of selector 24-23 S78 to S93 Input of selector 24-24 S85 to S100 Input of selector 24-25 S92 to S107 Selector 24 -26 input S99-S114 selector 24-27 input S107-S122 selector 24-28 input S115-S130 selector 24-29 input S123-S138 selector 24-30 input S132-S147 selector 24-31 input S141 -S156 Input of selector 24-32 S150-S165 Input of selector 24-33 S160-S175 Input of selector 24-34 S170-S185 Input of selector 24-35 S180-S195 Input of selector 24-36 S191-S206 Selector 24-- 37 input S202 to S217 selector 24-38 input S213 to S228 selector 24-39 input Force S225-S240 Input of selector 24-40 S241-S256 Input of selector 24-41 S257-S272 Input of selector 24-42 S273-S288 Input of selector 24-43 S289-S304 Input of selector 24-44 S305-S320 Selector Input of 24-45 S321-S336 Input of selector 24-46 S337-S352 Input of selector 24-47 S353-S368 Input of selector 24-48 S369-S384 Input of selector 24-49 S385-S400 Input of selector 24-50 S401 to S416 Input of selector 24-51 S417 to S432 Input of selector 24-52 S433 to S448 Input of selector 24-53 S449 to S464 Input of selector 24-54 S465 to S480 Input of selector 24-55 S481 to S496 Selector 24 -56 input S497-S512 selector 24-57 input S513-S528 section Input of the selector 24-58 S529 to S544 Input of the selector 24-59 S545 to S560 Input of the selector 24-60 S561 to S576 Input of the selector 24-61 S577 to S592 Input of the selector 24-62 S593 to S608 Selector of the selector 24-63 Inputs S609 to S624 Inputs of selectors 24-64 S625 to S640 As described above, each selector 24 selects the output video signals of the continuous 16 shift registers, but each selector becomes a candidate as the number of stages increases. The distance between each group of 16 video signals increases. As a result, the number of selectors 24 to which each tap is connected decreases as the number of stages increases.

For example, as shown above, tap S15 is 9 from selector 24-1 to selector 24-9.
The taps S100 are connected to the three selectors 24, which are candidates for the selectors 24-24 to 26-26. The taps S229 and above are connected to only one selector 24.

This is because the coefficient a of multiplication generally becomes smaller as the number of stages increases, so that the influence on the accuracy is smaller than that in the portion having a smaller number of stages. That is,
It is set so that the selector candidates can be densely selected in a portion having a low stage number, and the selector candidates are roughly selected in a portion having a high stage number.

By thus limiting the candidates of selectors, for example, the tap S of the delay register 20 is S.
The four output signals of 1, S2, S3 and S4 can be input to the multiplier at the same time (in the first, second, third and fourth stage multipliers 22, respectively). Input), taps S609, S610, S61 of the delay register 20
The four output signals 1 and S612 cannot be input to the multiplier 22 at the same time (only one of these signals is input to the 63rd stage multiplier via the selector 24).

A feature of this embodiment is that the video signal to be multiplied by the multiplier 22 is selected by the selector 24 from 640 time-delayed video signals. Therefore, it is possible to efficiently cancel the ghost of the video signal without providing the multiplier 22 for every 640 video signals. Further, in the low-stage portion of the shift register, the video signal input to the multiplier 22 can be more densely selected because it has a short time delay and cancels a large number of reflected waves of large amplitude. ing. Therefore, it is possible to effectively cancel the ghost.

Embodiment 2 FIG. 2 is a partial circuit diagram of a programmable digital filter according to Embodiment 2 of the present invention. Also in this embodiment,
The input signal is an 8-bit parallel signal.

In this embodiment, the shift register 18 is
It is configured by connecting the variable length shift registers 30 in series. In FIG. 2, only the lower variable length shift register 30 and the uppermost (64th) variable length shift register 30-64 are shown in the figure, and the other parts are omitted and not shown. A feature of this embodiment is that 64 variable length shift registers 30 are used instead of 640 fixed length shift registers. The output signal of each variable length shift register 30 is supplied to the multiplier 32. The variable length shift register 30 can change its delay time. The value of the delay time is set by an 8-bit delay time register 36 provided for each variable length shift register 30. From one stage of the variable length shift register 30 to one stage of the fixed length delay register, 1
A delay time equivalent to 6 stages can be realized.

The variable length shift register 30 for outputting the video signal multiplied by the coefficient a in each multiplier 32 is determined for each multiplier 32. By changing the delay time (shift time) of the variable length shift register 30, it is possible to obtain the same effect as selecting the video signals having different delay times as in the first embodiment. As can be easily understood from FIG. 2, n
The delay amount (the number of delay stages) of the video signal input to the multiplier 32 of the stage is the sum of the delay times of the variable length shift registers 30 from the first stage to the n-th stage. As the value of each delay time register 36, a predetermined value is externally written as in the first embodiment. Further, as in the first embodiment,
A predetermined value is also written in the coefficient register 33 from the outside.

As in the first embodiment, 64 multipliers 32 and 64 coefficient registers 33 holding the coefficients a are provided.

In the present embodiment, the delay amount of the video signal supplied to each multiplier 32 can be freely set by adjusting the delay amount of the variable length shift register 30.

Generally, when a programmable digital filter is used in a ghost canceller, the number of reflected waves is at most about several tens as described above, so that the performance is degraded in this embodiment as in the first embodiment. It is possible to reduce the number of multipliers 32 (equal to the number of coefficients a) to 64 without doing so.

In the first embodiment, the distance (difference in the number of stages) between the groups of 16 signals that are candidates selected by each selector increases as the number of stages increases. On the other hand, in the present embodiment, there is no such difference in accuracy depending on the number of stages, but the maximum value (16) of the distance (difference in the number of stages) between the signals supplied to each multiplier 32 is set. That is, this embodiment is a digital filter capable of efficiently canceling ghosts when the signals supplied to the multiplier 32 are substantially evenly distributed in time. However, as a matter of course, the signal can be ignored by appropriately setting the count a supplied to the multiplier 32 to "0", and as a result, the distance between the signals before and after the ignored signal becomes 16 steps or more. It goes without saying that you can do it.

Embodiment 3 FIG. 3 shows a variable length shift register 30 of a partial circuit of a programmable digital filter according to Embodiment 3 of the present invention.
4 is an example of the circuit diagram of the delay register 41 constituting the variable-length shift register, FIG. 5 is an example of the circuit diagram of the preceding-stage bit latch and the succeeding-stage bit latch, and FIG. 6 is the second clock generation circuit. For example, FIG. 7 is a timing diagram showing the relationship between the first clock and the second clock.

Also in this embodiment, the input signal is an 8-bit parallel signal. In FIG. 3, the variable length shift register 30 is configured by connecting ten delay registers 41 in series. In FIG. 3, only the delay registers 1, 2, 3 and 10 are shown, and other parts are omitted and not shown. 4, the delay register 41 includes a front stage latch 42 and a rear stage latch 45, the front stage latch 42 includes a front stage input gate 43 and a front stage bit latch 44, and the rear stage latch 45 includes a rear stage input gate 46 and a rear stage bit latch. It is composed of 47. In FIG. 4, only the systems of inputs 0, 1, and 7 are shown, and other parts are omitted and not shown. The previous stage input gate 43 becomes conductive when the first clock is at a high level, and the input state at that time is stored in the previous stage bit latch 44. When the first clock goes low, the previous stage input gate 43 becomes non-conductive, and the memory of the previous stage bit latch 44 is held even if the input state changes. Similarly, the rear-stage input gate 46 conducts when the second clock is at a high level, and the state of the front-stage bit latch 44 at that time is in the rear-stage bit latch 4.
Stored in 7. When the second clock goes low, the rear-stage input gate 46 becomes non-conductive, and the front-stage bit latch 4
Even if the state of 4 changes, the memory of the latter stage bit latch 47 is held.

In FIG. 5, the preceding-stage bit latch 44 and the succeeding-stage bit latch 47 are composed of a normal inverter 48 and a minimum inverter 49 forming a loop with its input / output, and hold the state. Even if the front-stage input gate 43 and the rear-stage input gate 46 become non-conducting, the front-stage bit latch 44 and the rear-stage bit latch 47 retain their states, respectively.

Therefore, when the first clock and the second clock have opposite phases, the input state can be fetched into the front stage latch 42 at the first clock and shifted to the rear stage latch 45 at the second clock for output. When 10 delay registers 41 are connected in series, a 10-byte shift register is formed. However, if the first clock and the second clock have the same phase,
At the same time that the input state is taken in by the first stage latch 42 at the first clock, the same input state is also taken in by the latter stage latch 45 and output. 10 delay registers connected in series 4
The delay time can be varied by setting the number of the second clocks that should pass through the first clock in the same phase as the first clock.

In this embodiment, the delay amount of the video signal supplied to each multiplier 32 can be freely set by adjusting the second clock of the delay register 41.

4 and 5, an example in which the front-stage latch 42 and the rear-stage latch 45 are composed of input gates and bit latches by inverters is shown.
It goes without saying that it can also be configured by a flip-flop or the like.

In FIG. 6, the second clock is composed of a delay register 51, a basic clock and three gates. In the figure, the second clock is composed of a delay time register 51, a basic clock and three gates. In the figure, only the second clocks 1, 2 and 10 are shown, and other parts are omitted and not shown. To make the second clock in phase with the basic clock, the delay time register 5
The corresponding bit of 1 is set to 1, that is, Q is set to high level and Q is set to low level. To set the opposite phase, delay time register 5
The corresponding bit of 1 is set to 0, that is, Q is set to low level and Q is set to high level. The timing chart at that time is shown in FIG.
Although an example of the circuit is not shown, the second clock and the first clock which are out of phase with each other are prevented from being at a high level at the same time in order to prevent passage of a memory. The second clock having the same phase has substantially the same timing as the first clock.

As described above, according to the first, second, and third embodiments, the signal supplied to the multiplier is the digital filter having 640 or more taps. Since 64 is selected as the maximum value, it is possible to provide a ghost canceller in which the number of multipliers and adders is significantly reduced.

In particular, according to the first embodiment, the video signal supplied to each of the multipliers 22 can be densely selected from the shift registers having a short time delay and a low number of stages, so that a more accurate ghost canceller can be provided. It has the effect that it can be provided.

According to the second embodiment, since the variable length shift register 30 is used, there is an effect that the number of multipliers 32 can be reduced without using a selector.

In the third embodiment, the variable length shift register 30 of the second embodiment is composed of a delay register using a two-phase clock, and the delay register is made to pass by the selection of the clock.
The delay time can be changed. This has the effect of significantly reducing the number of circuits compared to the selector method.

[0056]

As described above, according to the programmable digital filter of the first aspect of the present invention, it is possible to select a signal having a necessary delay time by an external command from a controller or the like. Therefore, when the number of required signals is smaller than the number of delay registers, that is, taps, the number of selectors can be reduced to about the number of signals. At the same time, since the number of multipliers and coefficient registers is the same as that of this selector, the number of multipliers and coefficient registers can be significantly reduced.

Conventionally, a multiplier and a coefficient register are provided for each tap, and the same number as the number of taps is required.
The configuration can be greatly simplified. Therefore, according to the present invention, a large-scale programmable digital filter, which has conventionally been too large to be stored in one chip due to its circuit scale, can also be stored in one chip.

Therefore, by using the digital filter of the present invention, there is an effect that a smaller and cheaper ghost canceller can be obtained.

According to the programmable digital filter of the second aspect of the present invention, in addition to the first aspect of the present invention, a selector connected to the taps on the low level side having a short delay time and the taps on the high level side having a long delay time is connected to the taps. Since the number of the signals is gradually decreasing, it is possible to densely select signals with short delay times as targets for multiplication.

In television broadcasting, the magnitude of a reflected wave having a short delay time is generally larger. Therefore, if a ghost canceller is configured using the programmable digital filter of the present invention, there is an effect that a ghost canceller capable of efficiently removing a large reflected wave having a short delay time can be obtained.

According to the programmable digital filter of the third aspect of the present invention, the shift register is constructed by using the variable length shift register. Therefore, the delay amount of the variable length shift register is changed by the command signal from the outside, so that the delay amount of the signal output from the tap provided at the output end of each variable length shift register is changed. .

Therefore, it is possible to select the delay time of the signal to be multiplied without the selection by the selector. Therefore, if the programmable digital filter of the present invention is used, like the first present invention,
A smaller and cheaper ghost canceller can be obtained.

Further, according to the programmable digital filter of the fourth aspect of the present invention, the variable length shift register is constituted by a delay register using a two-phase clock, and the delay register can be passed by selecting the clock.
Therefore, the method of selecting the delay amount by the selector requires at least 5120 selectors for 640 taps and 5120 buffers for an 8-bit input signal, but can be realized with only 1920 gates.

Therefore, by using the programmable digital filter of the present invention, it is possible to obtain a ghost canceller which is smaller in size, consumes less power and is inexpensive.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram of a programmable digital filter which is a first preferred embodiment of the present invention.

FIG. 2 is a partial circuit diagram of a programmable digital filter which is a second preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a variable length shift register of a programmable digital filter according to a third preferred embodiment of the present invention.

FIG. 4 is a circuit diagram of a delay register that constitutes the variable length register of FIG.

5 is a circuit diagram of a front stage bit latch and a rear stage bit latch shown in FIG. 4. FIG.

FIG. 6 is a circuit diagram of a second clock generation circuit shown in FIGS. 3 and 4.

FIG. 7 is a timing diagram showing a relationship between a first clock and a second clock.

FIG. 8 is a configuration block diagram of a conventional typical ghost canceller.

FIG. 9 is a circuit configuration diagram of the transversal filter 10.

FIG. 10 is a circuit configuration diagram of an actual product of a conventional ghost canceller used in a television tuner.

[Explanation of symbols]

 18 shift register 20 delay register 22 multiplier 23 coefficient register 24 selector 30 variable length shift register 32 multiplier 33 coefficient register 36 delay time register 41 delay register 42 pre-stage latch 43 pre-stage input gate 44 pre-stage bit latch 45 post-stage latch 46 post-stage input gate 47 Second-stage bit latch 48 Normal inverter 49 Minimum inverter 51 Delay time register

Claims (4)

[Claims] 1. A shift register for delaying an input signal, comprising a plurality of delay registers connected in series, wherein each delay register has a tap at its output end, and each tap has a delay time. Shift register that outputs different signals, and is connected to any number of taps of the plurality of taps, select any one of the connected taps, the signal from the selected taps , A plurality of selectors for outputting each of the selectors, a plurality of coefficient registers provided for each of the selectors for holding a coefficient by which a signal output from the selector is multiplied, and provided for each of the selectors, and output by each of the selectors. And a plurality of multipliers for multiplying the coefficient held in each coefficient register, each coefficient register Holding the supplied coefficient from said each selector, either one of the taps of the attached tapped, programmable digital filter, characterized by selecting the command from outside. 2. The programmable digital filter according to claim 1, wherein the tap extends from the low-side tap that outputs a signal with a small delay time to the high-side tap that outputs a signal with a long delay time. A programmable digital filter characterized in that the number of connected selectors is successively decreasing. 3. A shift register for delaying an input signal, the shift register comprising a predetermined number of variable length shift registers whose delay times can be changed, connected in series, and tapped at an output end of each variable length register. A shift register that outputs signals with different delay times from each tap; a coefficient register that is provided for each tap and holds a count that is multiplied with the signal output from the tap; And a multiplier for multiplying the output signal from the tap by the coefficient held in the corresponding coefficient register, the coefficient register holding the coefficient supplied from the outside, The programmable digital filter characterized in that the delay time of the variable length shift register is changed by an external command. 4. The programmable digital filter according to claim 3, wherein the variable-length shift register is configured by connecting a plurality of delay registers in series, and the delay register includes a pre-stage latch that latches at a first clock and a second clock. A programmable digital filter characterized in that it is provided with a post-stage latch for latching with, and the second clock can be selected from the outside in phase or in phase with the first clock.