JPH082015B2 - Digital filter and digital signal processing system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter and a digital signal processing system for filtering image signals and audio signals.

[0002]

2. Description of the Related Art There are two methods shown below in FIGS. 9 and 10 for the configuration of a FIR type digital filter.

FIG. 9 shows a direct type n-tap digital filter, in which 1 (1) to 1 (n-1) are delay units, 2 (1) to 2 (n) are multipliers, and 3 (1) to 3 (1). 3 (n) is an adder.

FIG. 10 shows a transposed n-tap digital filter, in which 1 (1) to 1 (n-1) are delay units, 2 (1) to 2 (n) are multipliers, and 3 (1) to 3 (n) is an adder.

In the direct type circuit configuration shown in FIG. 9, a delay device 1 is included in the input data. On the other hand, in the transposed circuit configuration in FIG. 10, the delay unit 1 is included in the multiplication and addition result. The direct type delay device is for input data, but the transpose type is a delay device for the result of multiplication and addition, so the bit width of the delay device is transposed by the multiplication coefficient of the multiplier. growing. Therefore, in terms of the number of elements, the direct type is less and advantageous.

However, in the direct type, it is difficult to add n multiplication results within one clock, and pipeline processing of the above operation causes layout difficulty. That is, it is impossible to add all the multiplication results within one clock with a digital filter having a direct type and a large number of taps. Also in terms of layout, collecting and adding each multiplication result in one place requires a large wiring area,
The full custom design is rather cumbersome and not suitable.

On the other hand, in the transposed type, it is possible to regularly arrange on the array by using a multiplication / addition (sum of products) for one tap as a basic unit. Further, since the delay device also serves as a pipeline register for addition operation, it has a structure suitable for pipeline processing. Therefore, in spite of the large number of elements, most custom chips have conventionally adopted the transposition type.

Further, when a digital signal processing system such as a waveform equalization system is constructed by using a FIR type digital filter, a transposed digital filter is used, as shown in FIG.

FIG. 11 shows a configuration example of a waveform equalization system using a transposed n-tap digital filter.
(1) to 1 (n) and 17 (3) to 17 (n) are delay devices, 2 (1) to 2 (n) are multipliers, 3 (1) to 3 (n) are adders, and 15 is A selector, 16 is a control circuit for controlling the selector 15 and the multiplication coefficient of each tap.

A digital signal processing system such as a waveform equalization system requires a function of outputting the input signal itself, not the output of the digital filter, until each multiplication coefficient is determined. In that case, the phases of the output of the input signal and the output of the digital filter must be matched. Therefore, in the transposed configuration, the delay device 17 for phase matching with respect to the input signal is required.

However, a waveform equalization system using a direct type n-tap digital filter has a configuration example as shown in FIG. In FIG. 8, 1 (1) to 1 (n) are delay devices, 2 (1)
~ 2 (n) is a multiplier, 3 (1) ~ 3 (n) is an adder, 15 is a selector, 16
Is a control circuit for controlling the selector 15 and the multiplication coefficient of each tap.

As can be seen by comparing the configuration examples of FIGS. 8 and 11, in FIG. 8, a delay device for matching the phase of the output of the input signal and the output of the digital filter is obtained from the middle of the delay device group 1. ing. Therefore, the delay group 17 for phase matching between the filter output and the input signal, which is necessary in the transposed configuration, is not required. When configuring such a digital signal processing system, the direct type configuration can simplify the entire system and is advantageous in terms of circuit scale.

[0013]

DISCLOSURE OF THE INVENTION As described above,
Although the direct type is advantageous in terms of the number of elements, the transposed type configuration has been adopted from the viewpoint of compatibility of pipeline processing and layout.

Since the transposition type structure has been adopted as described above, there is a limit in reducing the number of elements.

An object of the present invention is to adopt a direct type structure in the structure of a digital filter, solve the disadvantages of pipeline processing compatibility and layout which are disadvantageous as compared with the conventional transposition type structure, and It is to provide a small number of direct type digital filters.

Another object of the present invention is to provide a digital signal processing system having a smaller circuit scale than the conventional one.

[0017]

According to a first aspect of the present invention, an n-stage delay device for first input data, a first register for storing an output of the n-stage delay device, and N multipliers for multiplying the output data of the delay device by an arbitrary coefficient, and (n + 2) input adder for adding the output results of the n multipliers and the second and third input data from the outside. And two second and third stored as an intermediate result of addition by the adder.
And an n-tap digital filter as a first constituent unit, and the output of the first register of the constituent unit is the first input data of the constituent unit of the next stage, and the second and third constituent units of the constituent unit. The output of the register is used as the second third input data of the constituent unit of the next stage, so that the m units of the constituent units are cascade- connected, and the second third unit of the constituent unit of the final stage is cascade- connected. And a fourth register for accommodating the addition result, and the third input data to the adder of the first-stage constituent unit connected in cascade is set to 0. The n × m tap digital filter 1 is configured.

According to a second aspect of the present invention, in the above-mentioned n × m tap digital filter, the first unit of the m-th stage constituent unit is used.
A fifth register for storing the output of the register
The n × m tap digital filter is used as a second constituent unit, the output of the fifth register of the second constituent unit is used as the first input data of the second constituent unit of the next stage, and the second constituent unit is used. By setting the output of the fourth register of the above as the second input data of the second constituent unit of the next stage, an n × m × j tap digital filter 2 in which j second constituent units are cascade- connected is provided. Configure.

According to a third aspect of the present invention, in the n-tap digital filter which is the first structural unit, the output signal from the preceding tap delay device is input to each tap, and the tap delay device is input to the next tap delay device. , The multiplier for multiplying the output data of the delay unit by an arbitrary coefficient, the multiplication result output, the sum output signal from the previous tap, and the carry output signal. It has the full adder group as an input and outputs as a sum input signal of the next-stage tap and a carry input signal, each tap being a minimum constitutional unit, and constituted by n-stage cascade connection of the minimum constitutional unit. n × m
The tap digital filter 3 is constructed.

[0020]

According to a fourth aspect of the present invention, the outputs of the n × m tap digital filters 1 to 3 and the i-th (0 ≦ i ≦ n × m) delay device of the n × m tap digital filter are provided. A digital signal processing system 4 having a selector that selects either of the outputs and a control circuit that controls the output of the selector is constructed.

[0022]

The above-mentioned direct type digital filters 1 and 2 are direct type FIR type digital filters, and the direct type digital filter for every several taps is used as a structural unit, and each structural unit has a pipeline structure and multistage cascade connection. By adopting the following configuration, it is possible to solve the problem of pipeline processing compatibility, which was a disadvantage in the direct type configuration, and it is possible to provide a digital filter with a small number of elements. .

By adopting the structure of the direct type digital filter 3 described above, it becomes possible to solve the layout problem that occurs in the digital filter 1.

Further, when constructing a waveform equalization system,
By configuring the digital signal processing system 4 using the above digital filters 1 to 3 , it is possible to provide a digital signal processing system having a smaller circuit scale than the conventional one.

[0025]

FIG. 1 is a block diagram of a digital filter having a direct type 8-tap digital filter as a structural unit.
Fig. 2 shows 6 obtained by cascading these structural units.
The whole block diagram of a 4-tap digital filter is shown.

A digital filter according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. In FIG. 1, 1 (1) to 1 (8) are eight-stage delay devices for the first data,
2 (1) to 2 (8) are eight multipliers for multiplying the output data of each delay device 1 by an arbitrary coefficient, 4 (1) to 4 (8) are delay devices, and 5 (1) to 5 (5)
(8) is a 1-tap digital filter, 8 is 8 multipliers 2
A 10-input adder for adding the output result and the second and third input data from the outside, and 10 and 11 are delays made up of two second and third registers for storing the result of addition by the adder 8 Reference numeral 12 is a delay unit composed of a first register for storing the output of the delay unit 1 of the eighth stage.

The characteristic of the configuration of FIG. 1 compared with the conventional direct type digital filter is that (1) an 8-tap direct type digital filter is used as a structural unit, and pipeline registers 10 and 11 are provided. ) The output of the 10-input adder is not the addition result (1 output) of 8 pieces of data, but the intermediate calculation result (2 outputs), (3) the data delay unit 12 for phase matching is provided, It is possible to make a multi-stage cascade connection between 8-tap direct type digital filters.

By adopting the pipeline structure as in (1), the number of gate delay stages required for addition of multiplication results of all taps is significantly reduced, and by (2), gate delay of operation required for 10-input adder. It is possible to further reduce the number of stages. By setting the output of the 10-input adder 8 to 2 outputs of the intermediate calculation result, carry carry delay with respect to the bit width of the adder is eliminated. Further, (3) enables cascade connection of 8-tap digital filters. In this way, the intermediate calculation result is stored in the delay device 10 and the delay device 11, and by adopting the constitutional unit of the 8-tap digital filter, it is possible to add the 8-input signal as the multiplication result and the other 2 input signals. There is.

FIG. 2 shows a configuration example of a 64-tap digital filter obtained by cascade-connecting eight 8-tap digital filters shown in FIG. 6 (1) to 6 (8) in FIG.
Is an 8-tap digital filter which is the first structural unit shown in FIG. 1, and 9 is a multi-stage cascade connection of eight structural units,
An adder for adding the two outputs of the second and third registers of the final-stage constituent unit connected in a multistage cascade , 13 is a delay device serving as a fourth register for storing the addition result of the adder 9, and 14 is 8 It is a delay device serving as a fifth register that stores the output of the first register of the structural unit of the stage.

In FIG. 2, the output of the delay unit 12 of the structural unit shown in FIG. 1 is used as the input signal of the delay unit 1 (1) of the structural unit of the next stage, and the outputs of the delay units 10 and 11 are the structural units of the next stage. By using the input signal to the unit 10-input adder 8, multi-stage cascade connection of the constituent units shown in FIG. 1 becomes possible.

In FIG. 2, the two outputs which have been propagated as they are in the middle of the calculation are finally added by the adder 9, and the normal calculation result is completed here. The calculation result is stored in the delay unit 13.

As described above, in the first embodiment of the present invention, as shown in FIG.
An 8-tap direct type digital filter as shown in Fig. 2 is used as a constituent unit, which is cascade- connected, and the intermediate calculation result propagated as it is with 2 outputs is finally added by the adder 9 shown in Fig. A 64-tap direct type digital filter is completed by solving the problem of compatibility of pipeline processing which is a problem of type.

Next, a digital filter according to the second embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG.
Is an example in which a 256-tap digital filter is configured with the 64-tap digital filter of FIG. 2 as one structural unit (one LSI). 7 (1) to 7 (4) in FIG.
Is a 64-tap digital filter shown in FIG. In FIG. 3, the output of the delay unit 14 of the 64-tap digital filter shown in FIG. 2 is used as the input signal of the delay unit 1 (1) of the structural unit 6 (1) of the next-stage 64-tap digital filter, and the delay unit 13 By using the output as the input signal to the adder 8 of the constituent unit 6 (1) of the next-stage 64-tap digital filter,
Multi-stage cascade connection of the 64-tap digital filter shown in FIG. 2 is possible.

The delay device 14 of FIG. 2 is a delay device for phase matching, and this delay device 14 enables cascade connection between 64-tap digital filters.

Next, the configuration of the 10-input adder of the digital filter according to the third embodiment of the present invention will be described with reference to FIGS. 4 and 5.

In FIG. 4, the reference numerals in the drawing are the same as those in FIG. In FIG. 4, reference numerals 42 (1) to 42 (8) denote 10 × 10 multipliers, each of which includes a multiplier 2 and a delay unit 4. 8 (1) -8 (8)
Represents the arrangement of the 10-input adder 8 in FIG. 8 (1) to 8 (8) are 20-bit full adders, which are included in each 1-tap digital filter of each tap. The sum output (sum) and carry output (carry) generated from each 20-bit full adder are input to the 20-bit full adder of the tap at the next stage. By including the 20-bit full adder in each tap in this way, it becomes possible to arrange the taps in an array.

The configuration of the 10-input adder 8 described above will be described in more detail with reference to FIG. FIG. 5 shows the wiring structure of the 10-input adder 8 of FIG.
, 8 (1.1) to 8 (1.20) are components of the 20-bit full adder 8 (1) in FIG. Similarly, 8 (2.1) to 8 (2.20) are components of the 20-bit full adder 8 (2) in FIG. 4, and similarly 8 (8.1) to 8 (8.20) are 20-bit full adders in FIG. Adder 8
It is a component of (8).

The sum signal and carry signal output from the preceding 8-tap direct type digital filter and the multiplier 2 (1) of FIG.
The multiplication result of is input to the 20-bit full adder 8 (1) at the first tap, and the sum signal and the carry signal are output. This output is the input signal to the 20-bit full adder 8 (2) at the second tap. Similarly, 20-bit full adder 8 at the final 8th tap
The sum signal and carry signal output from (8) are added to the delay units 10 and 11.
Stored by.

By adopting the wiring structure of a 10-input adder as shown in FIG. 5 and including a 20-bit full adder 8 for each tap as shown in FIG. 4, the taps are arranged in an array between the taps. This makes it possible to form an array-like and simple layout structure.

Further, the sum signal output from the 20-bit full adder 8 (8) and the carry signal are not added and stored in the delay units 10 and 11, so that carry propagation for the bit width of the 20-bit full adder is carried out. It also has the effect of eliminating the delay.

Table 1 shows the conventional direct type construction method, transposition type construction method, and each feature of the present invention.

[0042]

[Table 1]

By adopting the direct type configuration as described above, it is possible to solve the problems of compatibility of pipeline processing and layout which are disadvantageous in the direct type configuration.

Next, a digital filter according to the fourth embodiment of the present invention will be described with reference to FIGS. 6 and 7.

If the clock rate is slow and the propagation delay time of the 10-input adder 8 shown in FIG.
The 8-tap direct type digital filter shown in can be used as one structural unit. FIG. 7 shows an overall block diagram of a 64-tap digital filter obtained by cascading these structural units.

In FIG. 6, reference numerals 1 (1) to 1 (8) denote delay devices, and 2 (1) to 1 (8).
2 (8) is a multiplier, 4 (1) to 4 (8) is a delay device, 5 (1) to 5 (8) is a 1-tap digital filter, and 3 (1) to 3 (8) are 2-input adders. ,
10 and 12 are delay devices.

In the configuration shown in FIG. 6, the pipeline register 10 has a direct-type digital filter with 8 taps as a unit.
And a data delay unit 12 for phase matching enable multistage cascade connection between 8-tap direct type digital filters.

As a result, the 2-input adder 3 group has the same function as that of the 9-input adder, and as described above, when the propagation delay time of the 9-input adder has a margin, such a configuration is adopted. Is also possible. Compared with FIG. 1, the delay device 11 can be omitted, and in addition, the two-input adder 9 and the delay device 13, shown in FIG.
There is an effect that 14 can be reduced and the entire circuit scale becomes smaller than that of the digital filter according to claim 1.

Next, 64 of the transposition type structure which has been used conventionally is used.
Compare the number of gates with the tap digital filter.
Here, the bit width of the input signal is rounded to 10 bits, the bit width of the multiplication coefficient is rounded to 10 bits, and the output of the multiplication result is rounded to 14 bits, and the adder performs comparison with 20 bits so that overflow does not occur.

In the case of the configuration example shown in FIGS. 1 and 2 of this embodiment, 210 delay devices are reduced as compared with the conventional transposition type. Further, in the case of the configuration example shown in FIGS. 6 and 7 of this embodiment,
Compared with the conventional transposed type, 370 delay devices are reduced.

Although the case where the multiplication coefficient is 10 bits is shown,
In the above configuration, this effect becomes more remarkable as the bit width of the multiplication coefficient increases.

Furthermore, when a digital processing system such as a waveform equalization system is constructed using such a digital filter, a function of outputting the input signal itself, not the output of the digital filter, until each multiplication coefficient is determined. Need. In that case, the phases of the output of the input signal and the output of the digital filter must be matched. As already mentioned in the section of the conventional example, in the transposed configuration,
A delay device 17 for adjusting the phase of the input signal (see FIG. 11).
(See) is required.

Next, the configuration of a digital signal processing system using the direct type digital filter of the present invention based on the fifth embodiment will be described with reference to FIG.

The waveform equalization system using the n-tap digital filter of the direct type of the present invention has a configuration example as shown in FIG. In FIG. 8, 1 (1) to 1 (n) are delay devices, 2
(1) to 2 (n) are multipliers, 3 (1) to 3 (n) are adders, 15 is a selector, 16 is a control circuit for controlling the selector 15 and the multiplication coefficient of each tap, etc. is there.

As can be seen by comparing the configuration examples of FIG. 8 and FIG. 11, in FIG. 8, a delay device for matching the phase of the output of the input signal and the output of the digital filter is obtained from the middle of the delay device group 1. ing. Therefore, the delay group 17 for phase matching between the filter output and the input signal, which is necessary in the transposed configuration, is not needed, and there is an effect that the circuit scale of the entire system is reduced.

In constructing such a digital signal processing system, the direct type digital filter of the present invention ( actual
Use of Examples 1 to 4) can simplify the entire system,
Further, it is advantageous in terms of circuit scale.

When the direct type digital filter of the present invention is applied to the waveform equalization system shown in FIG. 8, the number of gates of about 500 delay devices is further reduced.

In the above embodiment, the configuration example of the 64-tap digital filter using the 8-tap digital filter as the structural unit has been described. However, the number of taps of the structural unit can be expanded according to the clock rate, and this structural unit can be expanded. It goes without saying that any number of cascades can be connected.

[0059]

By constructing the digital filter as described above, it becomes possible to easily construct the digital filter of the direct type which is not suitable for the pipeline structure and has a good layout dependency, and the conventional digital filter can be easily constructed. Compared with a transposed digital filter, it is advantageous in terms of the number of gates, power consumption, and chip area. When the above-mentioned digital filter of the present invention is applied to a digital signal processing system such as a waveform equalization system, the system can be simplified and its effect becomes remarkable, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an 8-tap digital filter according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a 64-tap digital filter according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a 256-tap digital filter according to an embodiment of the present invention.

FIG. 4 is a layout configuration diagram of an 8-tap digital filter according to an embodiment of the present invention.

FIG. 5 is a wiring diagram of a 10-input adder of an 8-tap digital filter according to an embodiment of the present invention.

FIG. 6 is a configuration diagram of an 8-tap digital filter according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a 64-tap digital filter according to an embodiment of the present invention.

FIG. 8 is a block diagram of a digital signal processing system using the digital filter of the present invention.

FIG. 9 is a direct type block diagram of a FIR type digital filter.

FIG. 10 is a transposed configuration diagram of the FIR digital filter.

FIG. 11 is a block diagram of a digital signal processing system using a transposed digital filter.

[Explanation of symbols]

 1 (1) to 1 (n-1) delay device 2 (1) to 2 (n) multiplier 3 (1) to 3 (n) adder 4 (1) to 4 (8) delay device 5 (1) ~ 5 (8) 1-tap digital filter 6 (1) ~ 6 (8) 8-tap digital filter 7 (1) ~ 7 (4) 64-tap digital filter 8 10-input adder 8 (1) ~ 8 (8) 20 Bit full adder 8 (1.1) to 8 (8.20) 1 bit full adder 9 Adder 10 to 14 Delay device 15 Selector 16 Control circuit 17 (3) to 17 (n) Delay device

Continuation of the front page (56) References JP-A-1-146418 (JP, A) JP-A 64-84910 (JP, A) JP-A 2-301314 (JP, A) JP-A 62-168412 (JP , A) JP-A-2-222319 (JP, A) JP-B-3-22725 (JP, B2) US Patent 5081604 (US, A) European Patent Application Publication 344326 (EP, A) International Publication 89-5544 (WO , A)

Claims (4)

[Claims] 1. An n-stage delay device for first input data, a first register for storing the output of the n-th delay device, and output data of each delay device multiplied by an arbitrary coefficient. N multipliers, and the output results of the n multipliers and the second and third input data from the outside are added (n + 2)
An n-tap digital filter having an input adder and two second and third registers for storing the intermediate result of addition by the adder is used as a first constituent unit, and the first register of the constituent unit is used. Is used as the first input data of the structural unit of the next stage, and the output of the second third register of the structural unit is used as the second input data of the structural unit of the next stage M multi-stage cascade connection, the multi-stage
The multistage cascade- connected first stage configuration is provided with an adder for adding two outputs of the second and third registers in the cascade- connected final stage configuration unit and a fourth register for storing the addition result. An n × m tap digital filter in which the third input data to the unit adder is 0. 2. The n × m tap digital filter according to claim 1, further comprising a fifth n × m tap digital filter having a fifth register for storing an output of the first register of the m-th stage constituent unit. And the output of the fifth register of the second constituent unit as the first input data of the second constituent unit of the next stage, and the fourth constituent of the second constituent unit.
An n.times.m.times.j tap digital filter in which j outputs of the second constituent unit are cascaded in multiple stages by making the output of the register of the second constituent data the second input data of the second constituent unit of the next stage. 3. The n-tap digital filter which is the first constitutional unit according to claim 1, wherein an output signal from the preceding tap delay device is input for each tap and an input signal is input to the next tap delay device. A delay device for outputting, a multiplier for multiplying the output data of the delay device by an arbitrary coefficient, a multiplication result output, a sum output signal from the previous stage tap and a carry output signal as inputs, and a sum of the next stage taps. An n × m tap digital filter having a full adder group for outputting as an input signal and a carry input signal, each tap being a minimum constituent unit, and being configured by cascade connection of n stages of the minimum constituent unit. 4. n × according to claim 1, 2, or 3.
The output of the m-tap digital filter and the n × m tap
The i-th (0 ≦ i ≦ n × m) delay of the pre-digital filter
A selector for selecting one of the output of the delay device and the selection
Signal having a control circuit for controlling the output of the detector
Processing system.