JPH06104657A - Bias circuit - Google Patents

Abstract

PURPOSE:To provide the bias circuit implementing highly accurate temperature compensation regardless of the highest junction temperature of transistors(TRs). CONSTITUTION:A base of a 2nd TR Q3', a collector of a 5th TR Q5, a base of a 4th TR Q4', and a collector of a 3rd TR Q4 are connected to bases of 1st and 2nd output TRS Q1, Q2 respectively. The 1st TR Q3, the 3rd TR Q3 and the 5th TR Q5 are connected in series. A connecting point of emitter resistors ra, rb of the 1st and 2nd output TRs Q1, Q2 and a connecting point of emitter resistors ra, rb of the 3rd and 4th output TRs Q3', Q4' are connected together. The 1st and 2nd TRs Q3, Q3' and the 3rd, 4th TRs Q3', Q4' are respectively coupled densely thermally and the 5th TR Q5 is mounted on a same heat sink on which the 1st and 2nd output TRs Q1, Q2 are mounted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit which is stable against temperature.

[0002]

2. Description of the Related Art A conventional bias circuit includes a first output transistor Q1 of NPN type, as shown in FIG.
A second output transistor Q2 of PNP type and a pair of first and second transistors Q3 which are smaller than the first output transistor Q1 and have the same characteristics of NPN type.
, Q3 ′ are thermally and tightly coupled to each other and mounted in one package, the first twin transistor 1 and the second output transistor Q2 are smaller in size and are a PNP type pair having the same characteristics. 3, 4th transistor Q4, Q4 '
And a second twin transistor 2 mounted in one package by thermally closely coupling them. The first and second output transistors Q1 and Q2 and the first and second output transistors Q1 and Q2.
The twin transistors 1 and 2 were attached to the same heat sink. The collector of the first output transistor Q1 is connected to the positive power source + VCC, the collector of the second output transistor Q2 is connected to the negative power source -VCC, and the emitters have the same resistance value. It is connected via ra and rb. The base of the first output transistor Q1 is connected to the base of the second transistor Q3 'and the collector of the first transistor Q3, and the base of the second output transistor Q2 is connected to the base of the fourth transistor Q4'. The base is connected to the collector of the third transistor Q4. The collectors of the second and fourth transistors Q3 'and Q4' are connected to the collectors of the first and second output transistors Q1 and Q2, respectively, and the emitters thereof have the same resistance value. Connected through the emitter resistors Ra and Rb of
The connection point of the third and fourth emitter resistors Ra and Rb is connected to the connection point of the first and second emitter resistors ra and rb. The emitters of the first and third transistors Q3 and Q4 are directly connected, the bases thereof are connected to each other through the first resistor R1, and the base and collector of the first transistor Q3 are connected to the second resistor resistor R2. The base and collector of the transistor Q4 are connected via the third resistor R3 having the same resistance value as the second resistor R2.

Next, temperature compensation in such a conventional bias circuit will be described with reference to FIG.

FIG. 5 is a diagram showing a thermal equivalent circuit of a conventional bias circuit. In the figure, Tj1 (Tj2) is the first (second) output transistor Q1.
(Q2) junction temperature TH: heat sink temperature Ta: ambient temperature Tj3 '(Tj4'): second (fourth) transistor Q3 '
(Q4 ') junction temperature Tj3 (Tj4): first (third) transistor Q3 (Q4
) Junction temperature P: collector loss of first and second output transistors Q1 and Q2 P ': collector loss of second and fourth transistors Q3' and Q4 'θj1-H (θj2-H): first (Second) output transistor Q
1 (Q2) junction-heat sink thermal resistance θH: Heat sink thermal resistance θj3'-3 (θj4'-4): Second (fourth) transistor Q
3 '(Q4') junction-first (third) transistor Q3
Thermal resistance between junctions of (Q4) θj3'-H (θj4'-H): Second (fourth) transistor Q
3 '(Q4') junction-heat sink thermal resistance θ3 (θ4): Second (fourth) transistor Q3 '(Q4
') Thermal resistance between junction and ambient temperature C1 (C2): first (second) output transistor Q1
(Q2) heat capacity CH: heat sink heat capacity C3 (C4): second (fourth) transistor Q3 '(Q4
') Heat capacity.

Here, the second and fourth transistors Q3 ',
The collector-emitter voltage VCE of Q4 'is the same as that of the first and second output transistors Q1 and Q2, and the first and second output transistors Q1 and Q2 and the second and fourth transistor Q3', Since the collector losses P and P'of Q4 'are almost proportional to the respective collector currents, the collector losses P'of the second and fourth transistors Q3' and Q4 'are P' = r / R · P, where r : First and second emitter resistances (ra, rb)
Resistance value R: the resistance value of the third and fourth emitter resistors (Ra, Rb) becomes, and the junction temperature Tj3 '(Tj4') of the second (fourth) transistor Q3 '(Q4') becomes It becomes proportional to the junction temperature Tj1 (Tj2) of the first (second) output transistor Q1 (Q2).

This second (fourth) transistor Q3 '(Q
The junction temperature Tj3 '(Tj4') of 4 ') has the same characteristics as the second (fourth) transistor Q3' (Q4 ') and the first (third) transistor Q3 (Q4), And the first (second)
In the twin transistor 1 (2) of the above, the first (third) transistor Q3 (Q
4) Promptly transmitted to the joint,

[0007]

[Equation 1] Becomes

The second (fourth) transistor Q3 '
Since (Q4 ') and the first (third) transistor Q3 (Q4) are mounted in the same package and the shape thereof is small, θ3 >>θj3'-3 (θ4 >>θj4' -4), which is generally higher than the heat capacity CH of the heat sink,
The heat capacity C1 (C2) of the first (second) output transistor Q1 (Q2) and the second (fourth) transistor Q3 '(Q
The heat capacity C3 (C4) of 4 ') is small, C1 << CH (C2 << CH) C3 << CH (C4 << CH), and C3 · θj3′-H << θH · CH, so θj3 The first (second) twin transistor 1 so that'-H = R / r.theta.j1-H (.theta.j4'-H = R / r.theta.j2-H).
By selecting the mounting method (2) to the heat sink, the junction temperature Tj3 (Tj4) of the first (second) transistor Q3 (Q4) for bias setting and the first (second) output transistor Junction temperature Tj1 of Q1 (Q2)
The relationship with (Tj2) can be Tj3 = Tj1 (Tj4 = Tj2).

As described above, in the conventional bias circuit, the junction of the first and third transistors Q3 and Q4 for bias setting is changed with respect to the change of the collector loss P of the first and second output transistors Q1 and Q2. Temperature compensation is performed by making the section temperatures Tj3 and Tj4 the same as the junction temperatures Tj1 and Tj2 of the first and second output transistors.

[0010]

In such a conventional bias circuit, the junction temperature Tj3, Tj4 of the first and third transistors Q3, Q4 for setting the bias and the first and second output transistors Q1, Since the junction temperatures Tj1 and Tj2 of Q2 are the same, the maximum junction temperatures (Tjmax) of the respective transistors must also be the same. However, in this bias circuit, since the first and third transistors Q3 and Q4 are small transistors, the maximum junction temperature (Tjmax) of the first and third transistors Q3 and Q4 is the same as that of the first and second output transistors Q1 and Q2. It is set lower than that. For example, in general, the first and second output transistors Q
1, the maximum junction temperature (Tjmax) of the power transistor used for Q2 is specified at 150 ° C,
Bias setting first and third transistors Q3 and Q4
The maximum junction temperature (Tjmax) of the small-signal small transistor used in the above is specified at 125 ° C. for that reason,
When temperature compensation is performed at the maximum junction temperature (Tjmax) of the first and second output transistors Q1 and Q2, there arises a problem in the reliability of the first and third transistors Q3 and Q4 for bias setting, and the accuracy of High temperature compensation may not be possible. Also, the first and third transistors Q3 and Q4
When a transistor having the same maximum junction temperature (Tjmax) as the first and second output transistors Q1 and Q2 is used, the shape of this transistor becomes relatively large and the second (third) transistor Q3 '( Since the thermal resistance θ3 (θ4) between the junction of Q4 ') and the ambient temperature is small, the conditional expression θ3 >>θj3'-3 (θ4 >>θj4'-4) is not satisfied and the accuracy is high. It becomes impossible to perform temperature compensation.

In view of the above, the present invention solves the drawbacks of the conventional example described above, and detects the change in the base-emitter voltage due to the change in the junction temperature of the output transistor, the change in the base-emitter voltage of the transistor for detecting the change in the heat sink temperature. And the change in the base-emitter voltage of the transistor that detects the temperature change proportional to the change in the junction temperature of the output transistor, it is possible to perform highly accurate temperature compensation at the maximum junction temperature of the output transistor. It is an object of the present invention to provide a bias circuit that can be used.

[0012]

In order to achieve the above object, a bias circuit according to the present invention comprises a first output transistor Q1 and a second output transistor Q2 whose emitters are the first and second emitter resistors, respectively. and the first and second output transistors Q1 and Q which are connected to each other through ra and rb.
In a push-pull amplifier in which a drive signal is applied to the base of 2 and an output is taken out from the connection point of the first and second emitter resistors ra and rb, a pair of first and second transistors Q3 having the same characteristics are provided. , Q3 ′ and a pair of third twin transistors 1 having the same characteristics.
The second twin transistor 2 composed of the fourth transistors Q4 and Q4 'is connected to the first and second output transistors Q1.
, Q2 are arranged so as not to be thermally coupled to the heat sink in which the first twin transistor 1 is arranged.
The emitters of the second transistor Q3 'and the fourth transistor Q4' of the second twin transistor 2 are connected to each other through the third and fourth emitter resistors Ra and Rb, respectively, and this connection point is the above-mentioned first point. , A second transistor Q5 connected to the connection point of the second emitter resistances ra and rb, and a fifth transistor Q5 arranged on the heat sink on which the first and second output transistors Q1 and Q2 are arranged, Bias voltage which is connected to the transistor Q1 and which is obtained by detecting the thermal change proportional to the thermal changes of the first and second output transistors Q1 and Q2 by the first and second twin transistors 1 and 2. And the bias voltage obtained by detecting the thermal change of the heat sink by the fifth transistor Q5, the first and second output transistors Q
It is characterized in that bias temperature compensation of 1 and Q2 is performed.

[0013]

The temperature compensation in the bias circuit of the present invention will be described with reference to FIG.

FIG. 2 is a diagram showing a thermal equivalent circuit of the bias circuit of the present invention. In the figure, the same parts as those in FIG. 5 of the conventional example are designated by the same reference numerals.

In the figure, Tj1 (Tj2): first (second) transistor Q1 (Q2)
) Junction temperature TH: temperature of heat sink Tj5: junction temperature of fifth transistor Q5 Ta: ambient temperature Tj3 '(Tj4'): second (fourth) transistor Q3 '
(Q4 ') junction temperature Tj3 (Tj4): first (second) transistor Q3 (Q4)
) Junction temperature P: collector loss of first and second output transistors Q1 and Q2 P ': collector loss of second and fourth transistors Q3' and Q4 'θj1-H (θj2-H): first (Second) output transistor Q
1 (Q2) junction-heat sink thermal resistance θH: Heat sink thermal resistance θj3'-3 (θj4'-4): Second (fourth) transistor Q
3 '(Q4') junction-first (third) transistor Q3
Thermal resistance between junctions of (Q4) θj3'-C (θj4'-C): Second (fourth) transistor Q
3 '(Q4') junction-case thermal resistance θj3-C (θj4-C): First (third) transistor Q3
Thermal resistance between the junction of (Q4) and the case θ3 (θ4): Thermal resistance between the case and the ambient temperature of the first and second (third and fourth) transistors Q3 and Q3 '(Q4, Q4'). C1 (C2): first (second) output transistor Q1
(Q2) heat capacity CH: heat sink heat capacity C3 (C4): heat capacity of the first and second (third and fourth) transistors Q3 and Q3 '(Q4, Q4').

Here, the second and fourth transistors Q3 ',
The collector-emitter voltage VCE of Q4 'is the same as that of the first and second output transistors Q1 and Q2, and the first and second output transistors Q1 and Q2 and the second and fourth transistor Q3', Since the collector losses P and P'of Q4 'are almost proportional to the respective collector currents, the collector losses P'of the second and fourth transistors Q3' and Q4 'are P' = r / R · P, where r : First and second emitter resistances (ra, rb)
Resistance value R: The resistance value of the third and fourth emitter resistances (Ra, Rb).

In the bias circuit of the present invention, the second (fourth)
Transistor Q3 '(Q4') and first (third) transistor Q3 (Q4) are mounted in the same package to form a first (second) twin transistor 1 (2),
Due to its small size, θ3 >>θj3'-3 (θ4 >>θj4'-4) θ3 >>θj3'-C (θ4 >>θj4'-C) θ3 >> θj3-C (θ4 >> θj4-C) and the junction temperatures Tj3 and Tj4 of the first and third transistors Q3 and Q4 are

[0018]

[Equation 2]

[0019]

[Equation 3] Becomes

Here, since θ3 = θ4 C3 = C4 and Tj3 = Tj4, only the first transistor Q3 will be considered hereinafter.

Therefore, the junction temperature change ΔTj3 of the first transistor Q3 is

[0022]

[Equation 4] Becomes

On the other hand, the first and second output transistors Q1
, Q2 junction temperature Tj1, Tj2

[0024]

[Equation 5]

[0025]

[Equation 6] Becomes

Here, since θj1-H = θj2-H C1 = C2 and Tj1 = Tj2, only the first output transistor Q1 will be considered hereinafter.

Therefore, the junction temperature change ΔTj1 of the first output transistor Q1 is

[0028]

[Equation 7] Becomes

Regarding the fifth transistor Q5, the thermal resistance θj5-H between the junction of the fifth transistor Q5 and the heat sink, the thermal resistance θ5 between the junction of the fifth transistor Q5 and the ambient temperature, and the fifth A heat equivalent circuit is constituted by the heat capacity C5 of the transistor Q5. (Not shown)
However, since the fifth transistor Q5 is screwed to the heat sink and θH >> θj5-H θH >> θ5 CH >> C5, the junction temperature Tj5 of the fifth transistor Q5 is
Is

[0030]

[Equation 8] Therefore, the fifth transistor Q5 detects the temperature TH of the heat sink.

Therefore, the junction temperature change ΔTj5 of the fifth transistor Q5 is

[0032]

[Equation 9] Becomes

Then, the first and second output transistors Q
The change ΔVBE of the base-emitter voltage VBE of 1, Q2 with temperature is

[0034]

[Equation 10] However, K1: is a constant of proportionality.

The bias voltage VB1 generated by the fifth transistor Q5 and the first and third transistors Q3, Q4
Change in bias voltage VB2 due to temperature ΔVB1, ΔV
B2 is ΔVB1 = −K2 · ΔTj5 ΔVB2 = −K3 · ΔTj3 where K2 and K3 are proportional constants, and the change ΔVB of the bias voltage VB of the entire bias circuit with temperature is

[0036]

[Equation 11] Becomes

Therefore, the proportional constants K2 and K3 are set as follows: K2 = K1

[0038]

[Equation 12] .DELTA.VB = .DELTA.VBE, the change .DELTA.VB of the bias voltage VB of the entire bias circuit due to the temperature changes .DELTA.VBE of the base-emitter voltage VBE of the first and second output transistors Q1 and Q2. And complete temperature compensation can be performed.

In such a bias circuit, the thermal resistance θQ1 between the junction of the first output transistor Q1 and the heat sink and the ambient temperature, and the thermal resistance between the junction of the first transistor Q3 ′, the case and the ambient temperature. θQ3 ′ is obtained, and the temperature rises ΔTQ1 and ΔTQ3 ′ of the first output transistor Q1 and the first transistor Q3 ′ are ΔTQ1 = θQ1 · P ΔTQ3 ′ = θQ3 ′ · P ′ = r / R · θQ3 ′ · P And the maximum temperature rises ΔTQ1max and ΔTQ3′max of the first output transistor Q1 and the first transistor Q3 ′ are ΔTQ1max = Tj1max−Ta ΔTQ3′max = Tj3′max−Ta, where Tj1max: the first output transistor Maximum junction temperature of Q1 Tj3'max: Since it is the maximum junction temperature of the first transistor Q3 ',

[0040]

[Equation 13] To be used by arbitrarily selecting the ratio r / R of the resistance value r of the first and second emitter resistors ra and rb and the resistance value R of the third and fourth emitter resistors Ra and Rb. It is possible to perform highly accurate temperature compensation regardless of the maximum junction temperature of the transistor to be regulated.

[0041]

Embodiment An embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a diagram showing a configuration of a bias circuit according to an embodiment of the present invention. In the figure, Q1 is a first output transistor of NPN type, Q2 is a second output transistor of PNP type, and 1 is a first. 2 is a second twin transistor. The first twin transistor 1 is a package in which a pair of first and second transistors Q3 and Q3 'having the same characteristics are thermally and tightly coupled and mounted in one package. Transistor 2
Shows a pair of third and fourth transistors Q4 and Q4 'having the same characteristics, which are thermally closely coupled and mounted in one package. Also, the first and second transistors Q3 and Q3 'are NPN type transistors which are smaller than the first output transistor Q1, and the third and fourth transistors Q4 and Q4' are the second output transistor Q2. It is a smaller PNP transistor. Q5 is NP
A fifth N-type transistor, ra and rb are first and second emitter resistors, Ra and Rb are third and fourth emitter resistors, R1, R2, R3, R4 and R5 are first and second. , The third, fourth, and fifth resistances, and the first emitter resistance ra
The second emitter resistance rb, the third emitter resistance Ra and the fourth emitter resistance Rb, the second resistance R2 and the third resistance R3 have the same resistance value. In the figure, the same parts as those in FIG. 4 of the conventional example are designated by the same reference numerals.

In the bias circuit according to the embodiment of the present invention, the first output transistor Q1, the second output transistor Q2, and the fifth transistor Q5 are attached to the same heat sink to be thermally coupled. The twin transistor 1 and the second twin transistor 2 are not thermally coupled.

In the embodiment, the first output transistor Q1
Is connected to the positive power supply + VCC, the collector of the second output transistor Q2 is connected to the negative power supply -VCC, and the emitters thereof are connected via the first and second emitter resistors ra and rb, respectively. The base of the first output transistor Q1 is connected to the base of the second transistor Q3 'and the collector of the fifth transistor Q5, and the base of the second output transistor Q2 is connected to the base of the fourth transistor Q4'. The base is connected to the collector of the third transistor Q4.
The collectors of the second and fourth transistors Q3 'and Q4' are connected to the collectors of the first and second output transistors Q1 and Q2, respectively, and the emitters thereof are connected to the third and fourth emitter resistors Ra and Rb, respectively. And the connection point of the third and fourth emitter resistors Ra and Rb is connected to the first and second
Connected to the connection point of the emitter resistors ra and rb. The emitter of the fifth transistor Q5 and the first transistor Q3
Connected to the collectors of the first and third transistors Q3,
Connect the emitters of Q4. Fifth transistor Q
The base of 5 is connected to the emitter and the collector through the fourth resistor R4 and the fifth resistor R5, respectively. 1st, 3rd
The bases of the transistors Q3 and Q4 of the first resistor R1
The base and collector of the first transistor Q3 and the base and collector of the third transistor Q4 are connected via the second and third resistors R2 and R3, respectively.

As described in detail in the section of the operation, the change ΔVBE in the base-emitter voltage VBE of the first and second output transistors Q1 and Q2 with temperature, and the temperature of the bias voltage VB1 from the fifth transistor Q5. Change ΔV
The change ΔVB2 of the bias voltage VB2 caused by B1, the first and third transistors Q3 and Q4 with temperature is ΔVBE = −K1 · ΔTj1 ΔVB1 = −K2 · ΔTj5 ΔVB2 = −K3 · ΔTj3, and the proportional constants K1 and K2, respectively. , K3, K2 = K1

[0045]

[Equation 14] Therefore, the ratio of the first to fifth resistors R1 to R5 is set.

That is, the change .DELTA.VBE of the base-emitter voltage VBE of the first and second output transistors Q1 and Q2 with temperature is the change .DELTA.VBE1 of the base-emitter voltage VBE1 of the first output transistor Q1 with the second. Is the sum of the base-emitter voltage VBE2 of the output transistor Q2 and the change ΔVBE2 with temperature, and they are the same, so that if the temperature coefficient of the transistor is k, then ΔVBE = ΔVBE1 + ΔVBE2 = −2kΔTj1. The constant of proportionality K1 is K1 = 2k.

From this, the proportional constants K2 and K3 are K2 = 2k

[0048]

[Equation 15] And the bias voltage V due to the fifth transistor Q5
Change in B1 with temperature ΔVB1, Change in bias voltage VB2 due to first and third transistors Q3, Q4 Δ
VB2 is ΔVB1 = -2k · ΔTj5

[0049]

[Equation 16] Becomes

Further, the change ΔVB1 of the bias voltage VB1 due to the temperature due to the fifth transistor Q5 from the change ΔVBE5 of the base-emitter voltage VBE5 of the fifth transistor Q5 due to the temperature,

[0051]

[Equation 17] And the change ΔVB2 of the bias voltage VB2 due to the temperature due to the first and third transistors Q3 and Q4 is equal to the change ΔVBE3 of the base-emitter voltage VBE3 of the first transistor Q3 with respect to the temperature and the base-emitter of the third transistor Q4. Since the change ΔVBE4 of the voltage VBE4 with temperature is the same and the resistance values of the second and third resistors R2 and R3 are the same,

[0052]

[Equation 18] The change ΔVBE5 of the base-emitter voltage VBE5 of the fifth transistor Q5 with temperature and the change ΔVBE3 of the base-emitter voltage VBE3 of the first transistor Q3 with temperature are ΔVBE5 = −k · ΔTj5 ΔVBE3 = −k · ΔTj3. Therefore, R4 = R5

[0053]

[Formula 19] The first to fifth resistors R1 to R5 are set so that

Next, the first and second output transistors Q1
The change in the temperature of each part with respect to the collector loss P of Q2 and Q2 will be described with reference to FIG.

First, as shown in FIG. 3A, when the collector loss P of the first and second output transistors Q1 and Q2 changes, the second and fourth transistors Q are proportionally changed.
The collector loss P'of 3'and Q4 'changes as shown in FIG. Along with this, the junction temperatures Tj1 and Tj2 of the first and second output transistors Q1 and Q2 are, as shown by the broken line in FIG. 3B, the first and third transistors Tj3 and Tj.
j4 rises as shown in FIG. 3 (c), and
The junction temperature Tj5 of the fifth transistor Q5 is shown in FIG.
As shown by the solid line in FIG. As a result, the first and third transistors Q3,
Change in bias voltage VB2 due to Q4 due to temperature ΔVB2,
The change .DELTA.VB1 of the bias voltage VB1 caused by the fifth transistor Q5 with temperature is shown in FIGS. 3 (d) and 3 (e), respectively.
As shown in FIGS. 3 (f) and 3 (g), the change .DELTA.VB in the bias voltage VB of the entire bias circuit due to temperature changes with the first and second output transistors Q1 and Q2.
Of the base-emitter voltage VBE of the same as the temperature variation ΔVBE. Thus, this bias circuit provides full temperature compensation.

Although the bias circuit according to the present invention has been described above in detail based on an example considered to be typical, the embodiment of the bias circuit according to the present invention is not limited to the structure of the above-mentioned embodiment. The present invention can be appropriately modified and implemented as long as it has the constituent features described in the above-mentioned claims, exhibits the action of the present invention, and has the effects described below.

[0057]

According to the bias circuit of the present invention, the junction temperature of the first and second output transistors from the second and fourth transistors having the collector loss proportional to the collector loss of the first and second output transistors. By detecting a temperature change proportional to the change and detecting a temperature change of the heat sink to which the first and second output transistors are attached from the fifth transistor, the base-emitter voltage of the first and third transistors is detected. And the base of the fifth transistor-
The emitter voltage is changed to compensate the bias voltage of the first and second output transistors. Therefore, by setting the ratio of the first and second emitter resistances to the third and fourth emitter resistances arbitrarily, it is possible to always perform highly accurate temperature compensation regardless of the maximum junction temperature of the transistor used. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bias circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a thermal equivalent circuit of a bias circuit of the present invention.

FIG. 3 shows a first bias circuit according to an embodiment of the present invention,
The figure which shows the change with the temperature of each part with respect to the collector loss of a 2nd output transistor.

FIG. 4 is a diagram showing a configuration of a bias circuit in a conventional example.

FIG. 5 is a diagram showing a thermal equivalent circuit of the conventional example.

[Explanation of symbols]

Q1, Q2 first and second output transistors 1, 2 first and second twin transistors Q3, Q3 'first and second transistors Q4, Q4' third and fourth transistors Q5 fifth transistor ra , Rb first and second emitter resistances Ra, Rb third and fourth emitter resistances R1, R2, R3, R4, R5 first, second, third, fourth and fifth resistances

Claims (1)

[Claims] 1. A first output transistor (Q1) and a second output transistor (Q1).
Of the output transistors (Q2) are connected to each other via first and second emitter resistors (ra, rb), respectively, and the first and second output transistors (Q1, Q2) are connected.
), A drive signal is applied to the base of the push-pull amplifier, and an output is taken out from the connection point of the first and second emitter resistors (ra, rb). Transistor (Q
3 、 Q3 ') first twin transistor (1)
And a second twin transistor (2) consisting of a pair of third and fourth transistors (Q4, Q4 ') having the same characteristics, the first and second output transistors (Q1, Q4).
The second twin transistor (1) is arranged so as not to be thermally coupled to the heat sink in which 2) is arranged.
Second transistor (Q3 ') in the second and fourth transistor (Q4') in the second twin transistor (2)
Are connected to each other through third and fourth emitter resistors (Ra, Rb), respectively, and this connection point is connected to the connection point of the first and second emitter resistors (ra, rb), respectively. 5 transistor (Q5) is disposed on the heat sink on which the first and second output transistors (Q1, Q2) are disposed, and the first output transistor (Q1)
), Which is obtained by detecting the thermal change proportional to the thermal change of the first and second output transistors (Q1, Q2) by the first and second twin transistors (1, 2). Bias voltage,
The thermal change of the heat sink is controlled by the fifth transistor (Q5)
A bias circuit for compensating the bias temperature of the first and second output transistors (Q1, Q2) with the bias voltage obtained by the detection.