JPH06104568A - Production of multilayer wiring board - Google Patents
Production of multilayer wiring boardInfo
- Publication number
- JPH06104568A JPH06104568A JP24924792A JP24924792A JPH06104568A JP H06104568 A JPH06104568 A JP H06104568A JP 24924792 A JP24924792 A JP 24924792A JP 24924792 A JP24924792 A JP 24924792A JP H06104568 A JPH06104568 A JP H06104568A
- Authority
- JP
- Japan
- Prior art keywords
- copper plating
- material layer
- layer
- laser beam
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は配線板の製造方法に係
り、特に多層配線板の製造に適する配線板の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board suitable for manufacturing a multilayer wiring board.
【０００２】[0002]
【従来の技術】周知のように配線板（配線回路基板）
は、たとえばガラエポ樹脂基板などの絶縁性基板面上に
接着剤を介して貼着された銅箔について、フォトリソグ
ラフィや、フォトエッチング処理を施し、所要の配線パ
ターン化するという方法で一般的に製造されている。ま
た、この種の配線板において、配線の高密度化ないし配
線板のコンパクト化などを目的にした多層配線型の配線
板も知られている。そして、この多層配線型の配線板
は、一般に次のようにして製造されている。たとえばセ
ラミックス板やポリイミド樹脂フイルムなどの絶縁性基
板を先ず用意し、この絶縁性基板面に、蒸着法などによ
り薄膜導体層を設け、この薄膜導体層面にレジストパタ
ーンを形成する。その後、前記薄膜導体層に選択的なエ
ッチング処理を施して、所要の配線パターンニングを行
ってから、この配線パターンニング面に絶縁層を被着す
る一方、この絶縁層に電気的に接続用の孔を穿設し、こ
の穿設孔内を導電性金属（柱状ピラー）などで埋設す
る。次いで、前記絶縁層上に所要の配線パターンニン
グ、絶縁層形成および配線層間の電気的な接続部の形成
を順次繰り返すことによって、多層配線部（層）を構成
している。2. Description of the Related Art As is well known, wiring boards (wiring circuit boards)
Is generally manufactured by a method of subjecting a copper foil adhered on an insulating substrate surface such as a glass epoxy resin substrate via an adhesive to photolithography or photoetching to form a required wiring pattern. Has been done. Further, in this type of wiring board, a multilayer wiring type wiring board is also known for the purpose of increasing the density of wiring or downsizing the wiring board. The multilayer wiring type wiring board is generally manufactured as follows. For example, an insulating substrate such as a ceramic plate or a polyimide resin film is first prepared, a thin film conductor layer is provided on this insulating substrate surface by a vapor deposition method, and a resist pattern is formed on this thin film conductor layer surface. Thereafter, the thin film conductor layer is subjected to selective etching treatment to perform required wiring patterning, and then an insulating layer is applied to the wiring patterning surface while electrically connecting to the insulating layer. A hole is formed, and the inside of the hole is filled with a conductive metal (columnar pillar) or the like. Next, a multilayer wiring portion (layer) is formed by sequentially repeating required wiring patterning, formation of an insulating layer, and formation of an electrical connection portion between wiring layers on the insulating layer.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記多
層配線板の製造方法の場合には、次のような不都合な点
が認められる。すなわち、前記配線層間の電気的な接続
部を成す柱状ピラーは、その端面が配線パターンに対接
することにより達成される。したがって、前記柱状ピラ
ーの上端面は、この柱状ピラーを貫挿埋設する絶縁層の
上面と同一面を成していることが、電気的な接続の信頼
性の上から重要視される。たとえば、柱状ピラーの上端
面と絶縁層上面との間にμm オーダーの段差があると、
薄膜の特性から段切れを生じ易い傾向がある。こうした
問題は、配線板のコンパクト化ないし配線の高密度化な
どに伴う配線パターンおよび絶縁層の薄膜化、あるいは
配線層間の電気的な接続に寄与する柱状ピラーの細径化
などが進められている現状では、由々しい問題となって
くる。However, in the case of the method for manufacturing a multilayer wiring board, the following disadvantages are recognized. That is, the pillar-shaped pillars that form the electrical connection between the wiring layers are achieved by having their end faces contact the wiring pattern. Therefore, it is important from the standpoint of reliability of electrical connection that the upper end surface of the pillar-shaped pillar is flush with the upper surface of the insulating layer that penetrates and embeds the pillar-shaped pillar. For example, if there is a step on the order of μm between the top surface of the pillar and the top surface of the insulating layer,
Due to the characteristics of the thin film, step breakage tends to occur. To solve these problems, wiring patterns and insulating layers are becoming thinner due to the downsizing of wiring boards and increasing the density of wiring, and the pillar pillars that contribute to electrical connection between wiring layers are becoming thinner. At present, it becomes a serious problem.
【０００４】前記問題に対して、柱状ピラーを絶縁層に
貫挿埋設（貫挿形成）際、柱状ピラー上面と絶縁層面と
が一平面を成すように制御するか、あるいは柱状ピラー
上面と絶縁層面より突出させて貫挿形成ししておき、絶
縁層面とが一平面を成すように研磨する手段の付加が試
みられている。しかし、これらの付加手段は、結果的に
製造工程の繁雑化（複雑化）を招来して、量産性などの
低下をもたらすので、実用的に十分な製造方法とはいえ
ない。To solve the above problem, when the pillar pillars are embedded in the insulating layer (insertion formation), the pillar pillar upper surface and the insulating layer surface are controlled so as to form a single plane, or the pillar pillar upper surface and the insulating layer surface. Attempts have been made to add a means of further protruding and penetrating and then polishing so that the insulating layer surface and the insulating layer surface are flush with each other. However, these addition means result in a complicated manufacturing process (complexity) and a decrease in mass productivity, and thus are not practically sufficient manufacturing methods.
【０００５】本発明は上記事情に対処してなされたもの
で、繁雑なな工程によらず、配線層間の電気的な接続も
確実に達成され、信頼性の高い多層配線板などを歩留ま
りよく製造することが可能な配線板の製造方法の提供を
目的とする。The present invention has been made in consideration of the above circumstances, and can reliably produce an electrical connection between wiring layers without complicated processes, and can manufacture a highly reliable multilayer wiring board with a high yield. An object of the present invention is to provide a method for manufacturing a wiring board that can be manufactured.
【０００６】[0006]
【課題を解決するための手段】本発明に係る配線板の第
一の製造方法は、導電性を有する支持基体面上に絶縁性
フイルムを貼合わせる工程と、前記絶縁性フイルム面上
にレーザ感度の高い材料層を被着形成する工程と、前記
絶縁性フイルムおよびレーザ感度の高い材料層を貫通し
て支持基体面に達する孔をレーザビーム照射で選択的に
穿設する工程と、 前記レーザ感度の高い材料層をレー
ザビーム照射して穿設貫通孔周辺部を一部とて含むパタ
ーンニングする工程と、前記支持基体を陰極として電気
銅メッキ処理を施して穿設されている貫通孔内およびパ
ターンニング面上に銅メッキを成長させる工程とを具備
してなることを特徴とする。A first method of manufacturing a wiring board according to the present invention comprises a step of laminating an insulating film on the surface of a conductive support substrate, and a laser sensitivity on the surface of the insulating film. A material layer having a high sensitivity, a step of selectively forming a hole penetrating the insulating film and the material layer having a high laser sensitivity to reach the surface of the supporting substrate by laser beam irradiation, and the laser sensitivity Patterning of a high-quality material layer by irradiating a laser beam with a peripheral portion of the through-hole provided as a part, and in the through-hole provided by electrolytic copper plating using the supporting substrate as a cathode, and And a step of growing copper plating on the patterning surface.
【０００７】また、本発明に係る配線板の第二の製造方
法は、レーザビーム照射で選択的に穿設した貫通孔を有
する絶縁性フイルムを貼合わせた導電性を有する支持基
体を陰極として電気銅メッキ処理を施して穿設されてい
る貫通孔内を銅メッキの成長で埋設する工程と、前記銅
メッキの成長による埋設面上にレーザ感度の高い材料層
を被着形成する工程と、前記レーザ感度の高い材料層を
レーザビーム照射して銅メッキの成長による埋設面を一
部とて含むパターンニングする工程と、前記支持基体を
陰極として電気銅メッキ処理を施してパターンニング面
上に銅メッキを成長させる工程とを具備してなることを
特徴とする。In the second method for manufacturing a wiring board according to the present invention, an electrically conductive supporting substrate having an insulating film having through holes selectively formed by laser beam irradiation is used as a cathode. A step of burying the inside of the through hole, which is bored by performing a copper plating treatment, by growth of copper plating; a step of depositing a material layer having high laser sensitivity on the embedded surface by the growth of copper plating; A step of patterning a material layer having a high laser sensitivity by irradiating a laser beam with a part of a buried surface formed by the growth of copper plating, and performing copper plating on the patterned surface by performing electrolytic copper plating with the supporting substrate as a cathode. And a step of growing plating.
【０００８】[0008]
【作用】本発明に係る配線板の製造方法によれば、たと
えば導電性支持基体面に一体的に絶縁層を配置し、この
絶縁層の所要箇所に選択的に穿設された貫通孔内を、電
気銅メッキにより埋め込み層間の接続部（柱状ピラー）
を形成すること、そして形成される層間接続部（柱状ピ
ラー）を介して（電気的な接続を成して）、上層の配線
パターンが電気銅メッキにより一体的に成長・形成され
ることなどにより、信頼性の高い層間接続が成される。
つまり、柱状ピラーは、導電性支持基体を陰極とした電
気銅メッキ処理で、絶縁層の所定箇所に穿設された貫通
孔内を成長・充填して形成される。しかも、この際、貫
通孔の周辺部面に予め下地配線パターンが形成されてい
る場合は、周辺部面の下地配線パターン面へのメッキ成
長により、絶縁層に対する段差の解消された構造を成
し、信頼性の高い層間接続が成される。一方、貫通孔の
周辺部面に予め下地配線パターンが形成されていない場
合でも、貫通孔内の銅メッキによる成長・充填（埋め込
み）の制御は容易で、絶縁層に対する段差の解消された
構造の形成が可能であり、その後形成された下地配線パ
ターンを介しての電気銅メッキによる主配線パターンの
形成段階で、接続一体化が助長され、信頼性の高い層間
接続が成される。According to the method of manufacturing a wiring board according to the present invention, for example, an insulating layer is integrally arranged on the surface of a conductive support substrate, and the inside of a through hole selectively formed at a required position of the insulating layer. , Connection part between buried layers by electrolytic copper plating (columnar pillar)
And the wiring pattern of the upper layer is integrally grown and formed by electrolytic copper plating through the formed interlayer connection (columnar pillar) (forming electrical connection). A highly reliable interlayer connection is formed.
That is, the columnar pillar is formed by growing and filling the inside of the through hole formed at a predetermined position of the insulating layer by electrolytic copper plating using the conductive support base as the cathode. In addition, at this time, when the underlying wiring pattern is formed in advance on the peripheral surface of the through hole, the step of the insulating layer is eliminated by plating growth on the peripheral wiring surface of the peripheral surface. A highly reliable interlayer connection is formed. On the other hand, even if the underlying wiring pattern is not formed in advance on the peripheral surface of the through hole, it is easy to control the growth / filling (embedding) by copper plating in the through hole, and the step with respect to the insulating layer is eliminated. The formation of the main wiring pattern is possible by forming the main wiring pattern by electrolytic copper plating through the underlying wiring pattern that has been formed thereafter, and integration of the connection is promoted, and highly reliable interlayer connection is achieved.
【０００９】[0009]
【実施例】以下図１(a) 〜(e) および図２(a) 〜(e) を
参照して本発明の実施例を説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 (a) to 1 (e) and 2 (a) to 2 (e).
【００１０】実施例１ 図１(a) 〜(e) は、本発明に係る第一の配線板の製造方
法の実施態様例を模式的に示すもので、次のような順序
で行われる。先ず、導電性を有する支持基体１、たとえ
ば厚さ 3mmのステンレス板、および絶縁フイルム２、た
とえば厚さ30μm のポリイミド樹脂フイルムをそれぞれ
用意する。そして、図１(a) に断面的に示すごとく、前
記導電性を有する支持基体（ステンレス板）１面上に、
絶縁性フイルム（ポリイミド樹脂フイルム）２を貼合わ
せる。次いで、図１(b) に断面的に示すごとく、前記絶
縁性フイルム２面上に、レーザ感度の高い材料層３、た
とえば厚さ 0.5μm 程度のＮｉＯx 層もしくはＣｕＯx
層を一様に被着形成してから、図１(c) に断面的に示す
ごとく、前記絶縁性フイルム２およびレーザ感度の高い
材料層３を貫通して支持基体１面に達する孔４をレーザ
ビーム照射で、所定の箇所に選択的に穿設する。こうし
て所定の箇所にレーザビーム照射で選択的に貫通孔４を
穿設した後、前記レーザ感度の高い材料層３をレーザビ
ーム照射して、図１(d) に断面的に示すごとく、穿設貫
通孔４周辺部を一部として含む所要のパターンニング
（下地配線パターンの形成）５を行う。つまり、前記レ
ーザ感度の高い材料層３にレーザビームを照射して、選
択的な蒸発・飛散によるパターンニングと選択的な還元
・金属化による下地配線パターン５を行う。かくして、
所要の下地配線パターン５を形成した後、前記支持基体
１を陰極として電気銅メッキ処理を施して穿設されてい
る貫通孔４内およびパターンニング（下地配線パター
ン）５面上に銅メッキ層６を成長させる（図１(e))。こ
の電気銅メッキ工程では、前記貫通孔４内が絶縁性フイ
ルム２面と同一平面を成すように銅6aで埋め込まれる一
方、下地配線パターン５面上に銅メッキ層6bが成長（銅
の析出）して、柱状ピラー6aと絶縁性フイルム２面上の
銅メッキ層（主配線パターン）6bとが、確実に接続一体
化した層間接続構造が形成される。この後は、前記形成
した主配線パターン6b面を支持基体とした形で、前記工
程を繰り返して所要の多層配線層を構成し、要すれば最
上層として絶縁層を配置一体化したり、導電性を有する
支持基体１面から剥離して多層配線板として実用に供す
る。Example 1 FIGS. 1 (a) to 1 (e) schematically show an example of an embodiment of a method for manufacturing a first wiring board according to the present invention, which is carried out in the following order. First, a conductive support substrate 1, for example, a stainless plate having a thickness of 3 mm, and an insulating film 2, for example, a polyimide resin film having a thickness of 30 μm are prepared. Then, as shown in a sectional view in FIG. 1 (a), on one surface of the conductive support base (stainless plate),
The insulating film (polyimide resin film) 2 is attached. Then, as shown in a sectional view in FIG. 1 (b), a material layer 3 having high laser sensitivity, for example, a NiO x layer or CuO x having a thickness of about 0.5 μm is formed on the surface of the insulating film 2.
After the layers are uniformly deposited, holes 4 reaching the surface of the supporting substrate 1 through the insulating film 2 and the material layer 3 having high laser sensitivity are formed as shown in a sectional view in FIG. 1 (c). By laser beam irradiation, holes are selectively formed at predetermined locations. In this way, after the through holes 4 are selectively drilled by laser beam irradiation in a predetermined portion, the material layer 3 having high laser sensitivity is laser beam irradiated and drilled as shown in a sectional view in FIG. 1 (d). Required patterning (formation of underlying wiring pattern) 5 including part of the periphery of the through hole 4 is performed. That is, the material layer 3 having high laser sensitivity is irradiated with a laser beam to perform patterning by selective evaporation / scattering and underlying wiring pattern 5 by selective reduction / metallization. Thus,
After forming the required underlying wiring pattern 5, a copper plating layer 6 is formed in the through holes 4 formed by electrolytic copper plating using the supporting substrate 1 as a cathode and on the surface of the patterning (underlying wiring pattern) 5. Grow (Fig. 1 (e)). In this electrolytic copper plating step, the inside of the through hole 4 is filled with copper 6a so as to be flush with the surface of the insulating film 2, while the copper plating layer 6b grows on the surface of the underlying wiring pattern 5 (deposition of copper). Then, the pillar-shaped pillar 6a and the copper plating layer (main wiring pattern) 6b on the surface of the insulating film 2 are securely connected and integrated to form an interlayer connection structure. After that, the above-mentioned main wiring pattern 6b surface is used as a supporting substrate, and the above steps are repeated to form a required multilayer wiring layer. If necessary, an insulating layer is arranged and integrated as the uppermost layer, or a conductive layer is formed. It is peeled off from the surface of the supporting substrate 1 having the above to be practically used as a multilayer wiring board.
【００１１】実施例２ 図２(a) 〜(e) は、本発明に係る第二の配線板の製造方
法の実施態様例を模式的に示すもので、次のような順序
で行われる。先ず、導電性を有する支持基体１、たとえ
ば厚さ 3mmのステンレス板、およびレーザビーム照射で
予め所定箇所に選択的に貫通孔４を穿設した絶縁フイル
ム２、たとえば厚さ50μm のポリイミド樹脂フイルムを
それぞれ用意する。そして、図２(a) に断面的に示すご
とく、前記導電性を有する支持基体（ステンレス板）１
面上に、絶縁性フイルム（ポリイミド樹脂フイルム）２
を貼合わせる。ここで、絶縁フイルム２への貫通孔４の
穿設は、支持基体１に貼合わせた後に行ってもよい。次
に、前記支持基体１を陰極として電気銅メッキ処理を施
し、図２(b) に断面的に示すごとく、穿設されている貫
通孔４内を銅メッキの成長で埋設する（柱状ピラー6aの
形成）。なお、この電気銅メッキ処理による貫通孔４内
の銅メッキ成長・充填は、上面が絶縁性フイルム２上面
と同一平面を成す程度に行われる。上記により貫通孔４
内を銅メッキで埋設して柱状ピラー6aを形成した後、図
２(c) に断面的に示すごとく、その埋設面上にレーザ感
度の高い材料層３、たとえば厚さ 0.5μm 程度のＮｉＯ
x 層もしくはＣｕＯx 層を一様に被着形成を被着形成し
てから、図２(d) に断面的に示すごとく、前記レーザ感
度の高い材料層３にレーザビーム照射して、銅メッキの
成長による埋設6a面を一部として含むパターンニング
（下地配線パターンの形成）５を行う。その後、前記支
持基体１を陰極として電気銅メッキ処理を施すことによ
り、前記パターンニング（下地配線パターンの形成）５
面上に、主配線パターン6bが一体的に形成される。つま
り、柱状ピラー6aと絶縁性フイルム２面上の銅メッキに
より形成された主配線パターン6bとが、確実に接続一体
化した層間接続構造を成す配線となる。この後は、前記
形成した主配線パターン6b面を支持基体とした形で、前
記工程を繰り返して所要の多層配線層を構成し、要すれ
ば最上層として絶縁層を配置一体化したり、導電性を有
する支持基体１面から剥離して多層配線板として実用に
供する。Example 2 FIGS. 2 (a) to 2 (e) schematically show an example of an embodiment of a method for manufacturing a second wiring board according to the present invention, which is carried out in the following order. First, an electrically conductive supporting substrate 1, for example, a stainless steel plate having a thickness of 3 mm, and an insulating film 2 having through holes 4 selectively formed in advance at a predetermined position by laser beam irradiation, for example, a polyimide resin film having a thickness of 50 μm are used. Prepare each. Then, as shown in a sectional view in FIG. 2 (a), the conductive support base (stainless plate) 1
Insulating film (polyimide resin film) on the surface 2
Stick together. Here, the formation of the through hole 4 in the insulating film 2 may be performed after the bonding to the supporting substrate 1. Next, electrolytic copper plating is performed using the supporting substrate 1 as a cathode, and the through holes 4 that have been bored are buried by copper plating growth (columnar pillars 6a), as shown in a sectional view in FIG. 2 (b). Formation). The copper plating growth / filling in the through holes 4 by this electrolytic copper plating process is performed to such an extent that the upper surface is flush with the upper surface of the insulating film 2. Through hole 4
After the columnar pillars 6a are formed by burying the inside with copper plating, a material layer 3 having a high laser sensitivity, for example, NiO having a thickness of about 0.5 μm, is formed on the burying surface as shown in a sectional view in FIG. 2 (c).
After the x layer or the CuO x layer is uniformly deposited, the material layer 3 having high laser sensitivity is irradiated with a laser beam as shown in a sectional view in FIG. Patterning (formation of the underlying wiring pattern) 5 including a part of the surface of the embedded 6a by the growth of is performed. Thereafter, the supporting substrate 1 is used as a cathode to perform an electrolytic copper plating process to perform the patterning (formation of a base wiring pattern) 5
The main wiring pattern 6b is integrally formed on the surface. That is, the pillar-shaped pillars 6a and the main wiring pattern 6b formed by copper plating on the surface of the insulating film 2 are wirings that form an interlayer connection structure that is surely connected and integrated. After that, the above-mentioned main wiring pattern 6b surface is used as a supporting substrate, and the above steps are repeated to form a required multilayer wiring layer. If necessary, an insulating layer is arranged and integrated as the uppermost layer, or a conductive layer is formed. It is peeled off from the surface of the supporting substrate 1 having the above to be practically used as a multilayer wiring board.
【００１２】なお、前記実施例において、絶縁フイルム
２への貫通孔４の穿設を、たとえば同一ピッチの格子状
に設定しておくと、貫通孔４の穿設工程がより簡易にな
るし、また配線パターン層間の接続箇所の選択も楽にな
る。そして、いずれの場合も、前記絶縁フイルム２へ穿
設する貫通孔４の径は、同一に選択・設定することが望
ましい。つまり、電気銅メッキによる貫通孔４内の銅の
成長・肉盛り、もしくは充填を一様に行ったり、あるい
は主配線パターン6bを形成する際の一様な電気銅メッキ
を進行させたりし得るからである。In the above-described embodiment, if the through holes 4 are formed in the insulating film 2 in a grid pattern having the same pitch, the through holes 4 can be formed more easily. Also, it becomes easy to select the connection point between the wiring pattern layers. In any case, it is desirable that the diameters of the through holes 4 formed in the insulating film 2 be selected and set to be the same. That is, it is possible to uniformly grow, build up, or fill the copper in the through-holes 4 by electrolytic copper plating, or to promote uniform electrolytic copper plating when forming the main wiring pattern 6b. Is.
【００１３】また、導電性支持基体としては、前記ステ
ンレス薄板の代わりに、たとえば銅やアルミの箔ないし
薄板などを始め，要するに電気メッキの電極として十分
機能し得る導電性を有するものであれば特に限定されな
い。一方、絶縁フイルムは、前記例示のポリイミド樹脂
フイルムの代りに、たとえばポリカーボネート樹脂層，
ポリエステル樹脂層，ポリエーテルエーテルケトン樹脂
層，ポリエーテル−イミド樹脂層，ポリフェニレンサル
ファイド樹脂層などでもよい。Further, as the conductive supporting substrate, in place of the stainless thin plate, for example, a foil or a thin plate of copper or aluminum, etc., that is, a conductive substrate which has a conductivity which can sufficiently function as an electrode for electroplating, is particularly preferable. Not limited. On the other hand, the insulating film is made of, for example, a polycarbonate resin layer, instead of the polyimide resin film exemplified above.
It may be a polyester resin layer, a polyether ether ketone resin layer, a polyether-imide resin layer, a polyphenylene sulfide resin layer, or the like.
【００１４】さらに、レーザビームの照射により被照射
部が飛散するタイプの感レーザ材料としては、前記Ｎｉ
Ｏx やＣｕＯx の他、たとえば、酸化銅、酸化鉄、酸化
コバルト、酸化モリブデン、酸化インジウム、酸化錫、
酸化鉛、酸化アンチモンなどを主成分とする金属酸化物
でも同様の効果が達成出来る。Further, as the laser sensitive material of the type in which the irradiated portion is scattered by the irradiation of the laser beam, the above Ni is used.
Other than O x and CuO x , for example, copper oxide, iron oxide, cobalt oxide, molybdenum oxide, indium oxide, tin oxide,
The same effect can be achieved by using a metal oxide containing lead oxide, antimony oxide, or the like as a main component.
【００１５】[0015]
【発明の効果】上記説明から分かるように、本発明に係
る配線板の製造方法によれば、操作が比較的簡単で、信
頼性の高い層間接続を備えた配線板を容易に、かつ歩留
まりよく製造し得る。すなわち、配線パターン層間の電
気的な接続に関与する柱状ピラーの上端面が層間絶縁を
成す絶縁層面と一平面を保持した形で構成されるため、
それらの段差に起因する膜切れ、電気的接続の不良発生
なども容易に、かつ確実に解消される。つまり、回路的
にも常に信頼性の高い配線板を歩留まりよく製造し得る
ことになる。As can be seen from the above description, according to the method for manufacturing a wiring board of the present invention, a wiring board having an interlayer connection which is relatively easy to operate and has high reliability can be easily and efficiently produced. Can be manufactured. That is, since the upper end surface of the pillar-shaped pillars involved in the electrical connection between the wiring pattern layers is configured to hold a plane with the insulating layer surface that forms the interlayer insulation,
It is possible to easily and surely eliminate the film breakage due to the step and the occurrence of a defective electrical connection. In other words, it is possible to always manufacture a wiring board having a high reliability in terms of a circuit with a high yield.
【図１】本発明に係る第一の配線板の製造方法の実施態
様例を模式的に示すもので、(a) は導電性支持基体に絶
縁フイルムを貼合わせた状態を示す断面図、(b) は絶縁
フイルム面上にレーザ感度の高い材料層を被着形成した
状態を示す断面図、(c)はレーザ感度の高い材料層を被
着形成した後、所要の貫通孔を穿設した状態を示す断面
図、(d) はレーザ感度の高い材料層をパターンニングし
た状態を示す断面図、(e) は導電性支持基体を陰極とし
て電気銅メッキした状態を示す断面図。FIG. 1 schematically shows an example of an embodiment of a method for manufacturing a first wiring board according to the present invention, in which (a) is a cross-sectional view showing a state in which an insulating film is attached to a conductive supporting substrate, (b) is a cross-sectional view showing a state in which a material layer having high laser sensitivity is deposited on the insulating film surface, (c) shows a material layer having high laser sensitivity is deposited, and then a required through hole is formed. Sectional view showing a state, (d) is a sectional view showing a state in which a material layer having high laser sensitivity is patterned, and (e) is a sectional view showing a state in which electroconductive copper is used as a cathode and electrolytic copper plating is performed.
【図２】本発明に係る第二の配線板の製造方法の実施態
様を模式的に示すもので、(a)は導電性支持基体に一体
的に配置・積層した絶縁層に所要の貫通孔を穿設した状
態を示す断面図、(b) は導電性支持基体を陰極として電
気銅メッキして貫通孔内を銅で充填した状態を示す断面
図、(c) はレーザ感度の高い材料層を被着形成した状態
を示す断面図、(d) はレーザ感度の高い材料層をパター
ンニングした状態を示す断面図、(e) は導電性支持基体
を陰極として電気銅メッキしてパターンニング面上に主
配線パターンを形成した状態を示す断面図。FIG. 2 schematically shows an embodiment of a second wiring board manufacturing method according to the present invention, in which (a) is a through hole required for an insulating layer integrally arranged and laminated on a conductive supporting substrate. , (B) is a cross-sectional view showing a state in which the conductive support substrate is used as a cathode for electrolytic copper plating and the through holes are filled with copper, (c) is a material layer with high laser sensitivity (D) is a cross-sectional view showing a state in which a material layer with high laser sensitivity is patterned, and (e) is a patterning surface after electrolytic copper plating with a conductive support substrate as a cathode. Sectional drawing which shows the state which formed the main wiring pattern on it.
１…導電性支持基体 ２…絶縁フイルム ３…レー
ザ感度の高い材料層 ４…貫通孔 ５…パターンニング（下地配線パター
ン） 6a…電気銅メッキで形成した層間接続（柱状ピ
ラー） 6b…電気銅メッキで形成した主配線パターンDESCRIPTION OF SYMBOLS 1 ... Conductive supporting substrate 2 ... Insulating film 3 ... Laser sensitive material layer 4 ... Through hole 5 ... Patterning (underlying wiring pattern) 6a ... Interlayer connection formed by electrolytic copper plating (columnar pillar) 6b ... Electrolytic copper plating Main wiring pattern formed by
Claims (2)
イルムを貼合わせる工程と、 前記絶縁性フイルム面上にレーザ感度の高い材料層を被
着形成する工程と、 前記絶縁性フイルムおよびレーザ感度の高い材料層を貫
通して支持基体面に達する孔をレーザビーム照射で選択
的に穿設する工程と、 前記レーザ感度の高い材料層をレーザビーム照射して穿
設貫通孔周辺部を一部として含むパターンニングする工
程と、 前記支持基体を陰極として電気銅メッキ処理を施して穿
設されている貫通孔内およびパターンニング面上に銅メ
ッキを成長させる工程とを具備してなることを特徴とす
る配線板の製造方法。1. A step of laminating an insulating film on the surface of a conductive support substrate; a step of depositing a material layer having a high laser sensitivity on the surface of the insulating film; and the insulating film and laser. A step of selectively piercing a hole reaching the surface of the supporting substrate through the material layer having high sensitivity by laser beam irradiation, and a step of irradiating the material layer having high laser sensitivity with the laser beam to form a peripheral portion of the through hole. And a step of growing copper plating in the through-holes and on the patterning surface that have been formed by performing electrolytic copper plating on the supporting substrate as a cathode. A method of manufacturing a characteristic wiring board.
通孔を有する絶縁性フイルムを貼合わせた導電性を有す
る支持基体を陰極として電気銅メッキ処理を施して穿設
されている貫通孔内を銅メッキの成長で埋設する工程
と、 前記銅メッキの成長による埋設面上にレーザ感度の高い
材料層を被着形成する工程と、 前記レーザ感度の高い材料層をレーザビーム照射して銅
メッキの成長による埋設面を一部として含むパターンニ
ングする工程と、 前記支持基体を陰極として電気銅メッキ処理を施してパ
ターンニング面上に銅メッキを成長させる工程とを具備
してなることを特徴とする配線板の製造方法。2. A through hole formed by performing electrolytic copper plating with a conductive support substrate, which is laminated with an insulating film having a through hole selectively formed by laser beam irradiation, as a cathode. A step of burying copper with growth of copper plating, a step of depositing a material layer having high laser sensitivity on the buried surface by the growth of copper plating, and copper plating by irradiating the material layer having high laser sensitivity with a laser beam. Patterning step including a part of the buried surface formed by growth of copper, and electrolytic copper plating treatment using the supporting substrate as a cathode to grow copper plating on the patterned surface. Wiring board manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24924792A JPH06104568A (en) | 1992-09-18 | 1992-09-18 | Production of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24924792A JPH06104568A (en) | 1992-09-18 | 1992-09-18 | Production of multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06104568A true JPH06104568A (en) | 1994-04-15 |
Family
ID=17190120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24924792A Withdrawn JPH06104568A (en) | 1992-09-18 | 1992-09-18 | Production of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06104568A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997032817A1 (en) | 1996-03-05 | 1997-09-12 | Goro Sato | Alumina sol, process for preparing the same, process for preparing alumina molding using the same, and alumina-based catalyst prepared thereby |
| US6405431B1 (en) | 1996-06-27 | 2002-06-18 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing build-up multi-layer printed circuit board by using yag laser |
| JP2003304063A (en) * | 2002-04-09 | 2003-10-24 | Shinko Electric Ind Co Ltd | Method of manufacturing metal core board |
| JP2010529693A (en) * | 2007-06-11 | 2010-08-26 | ピーピージー インダストリーズ オハイオ， インコーポレイテッド | Method for forming a solid blind via through a dielectric coating on a high density interconnect (HDI) substrate material |
-
1992
- 1992-09-18 JP JP24924792A patent/JPH06104568A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997032817A1 (en) | 1996-03-05 | 1997-09-12 | Goro Sato | Alumina sol, process for preparing the same, process for preparing alumina molding using the same, and alumina-based catalyst prepared thereby |
| US6171573B1 (en) | 1996-03-05 | 2001-01-09 | Goro Sato | Alumina sol, process for preparing the same, process for preparing alumina molding using the same, and alumina-based catalyst prepared thereby |
| US6405431B1 (en) | 1996-06-27 | 2002-06-18 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing build-up multi-layer printed circuit board by using yag laser |
| JP2003304063A (en) * | 2002-04-09 | 2003-10-24 | Shinko Electric Ind Co Ltd | Method of manufacturing metal core board |
| JP2010529693A (en) * | 2007-06-11 | 2010-08-26 | ピーピージー インダストリーズ オハイオ， インコーポレイテッド | Method for forming a solid blind via through a dielectric coating on a high density interconnect (HDI) substrate material |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5369881A (en) | Method of forming circuit wiring pattern | |
| JP3759754B2 (en) | How to make raised metal contacts on electrical circuits | |
| JP4564342B2 (en) | Multilayer wiring board and manufacturing method thereof | |
| US6350365B1 (en) | Method of producing multilayer circuit board | |
| CN103874326A (en) | Printed circuit board and method of manufacturing printed circuit board | |
| KR100720049B1 (en) | Multilayer wiring board and method of producing the same | |
| JPH06104568A (en) | Production of multilayer wiring board | |
| JP2003347700A (en) | Wiring board | |
| WO2005002304A1 (en) | Method of manufacturing electronic part and electronic part | |
| JP4052434B2 (en) | Multilayer substrate and manufacturing method thereof | |
| CN105282968A (en) | Method for producing wiring board | |
| JP2003273516A (en) | Successive multilayer wiring board and method for manufacturing the same | |
| JP2003264368A (en) | Multilayered electric wiring circuit board and its manufacturing method | |
| JP4227967B2 (en) | Substrate and electronic component manufacturing method | |
| TWI690249B (en) | Fine interlayer circuit structure and method for making the same | |
| KR100772294B1 (en) | Production method for electronic component | |
| KR100593211B1 (en) | Method for manufacturing through hole electrode for wafer | |
| JP2005244140A (en) | Method for manufacturing wiring board | |
| JPS61179598A (en) | Formation of multilayer interconnection | |
| TWM589955U (en) | Fine interlayer circuit structure | |
| JP2013045960A (en) | Wiring board and manufacturing method of the same | |
| JPH07226589A (en) | Manufacture of thin film multilayer wiring board | |
| JP2013045959A (en) | Manufacturing method of wiring board | |
| KR100468195B1 (en) | A manufacturing process of multi-layer printed circuit board | |
| CN116095990A (en) | Fine circuit substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991130 |