JPH06104240A - Method of etching semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of etching a semiconductor device, wherein the depth of an etching operation or the thickness of a thin part can be controlled accurately. CONSTITUTION:According to an experimental result, it is confirmed that the distance up to an etching stop position from a P-N junction face is nearly equal to the width of a depletion layer on the substrate side of the P-N junction part when a P-type substrate (a second-conductivity-type semiconductor part) on which an N-type epitaxial layer (a first-conductivity-type semiconductor part) has been formed is immersed in an etching liquid such as KOH or the like, a voltage which reverse-biases the P-N junction is applied across an electrode plate faced with the substrate and the epitaxial layer so as to perform an electrochemical etching operation. That is to say, the etching operation is finished at the tip of the depletion layer. Consequently, since the width of the depletion layer on the substrate side has been controlled to be a magnitude obtained by subtracting the depth required for the etching operation from the thickness of the semiconductor substrate excluding the semiconductor layer, it is possible to accurately control the depth of the etching operation or the thickness of a thin part left by the etching operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a semiconductor acceleration sensor or a semiconductor pressure sensor (hereinafter collectively referred to as a semiconductor dynamic sensor).

[0002]

In Japanese Patent Laid-Open No. 62-61374, a P-type substrate having an N-type layer is immersed in an etching solution to face an electrode plate and a voltage is applied between the N-type layer and the electrode plate. Disclosed is an electrochemical etching method for a silicon substrate, in which a P-type substrate is anisotropically etched to form a strain generating portion and a separation groove of a semiconductor dynamic sensor.

The aforementioned publication also discloses that the etching is automatically stopped when it reaches the N-type layer.

[0004]

However, according to the experiments by the present inventor, the etching is performed on the P
It was found that the distance from the bonding surface to the etching end position ends on the mold substrate side, and varies depending on the impurity concentration of the N-type layer and the P-type substrate and the variation of the applied voltage. Therefore, for example, the thickness of the strain generating portion (for example, the diaphragm portion) of the semiconductor dynamic sensor is conventionally set by the thickness of the N-type layer, but the actual thickness of the strain generating portion is more than that.
As a result, the amount of strain actually obtained in the strain-flexing part is smaller than the theoretically calculated value, which deteriorates the sensor design accuracy.

Particularly, conventionally, the thickness of the strain generating portion of the semiconductor dynamic sensor thinned by the electrochemical etching is relatively large, for example, several tens of μm, so that the strain generating portion due to the variation in the etching end position is generated. Sensitivity fluctuation due to thickness variation was small, but the strain-generating part is, for example, several μm.
In the case of achieving high sensitivity as a thin wall, the above variation causes a great variation in sensitivity.

There is also a problem that the etching depth or the thickness of the strained portion cannot be accurately predicted. The present invention is
The present invention has been made in view of the above problems, and an object thereof is to provide an etching method of a semiconductor device capable of accurately controlling the etching depth or the thickness of a thin portion formed by etching.

[0007]

A method of etching a semiconductor device according to the present invention comprises a first conductivity type single crystal semiconductor portion and a second conductivity type single crystal semiconductor portion.
A semiconductor member that forms a PN junction with the conductivity type single crystal semiconductor portion is immersed in an etching solution so that the second conductivity type single crystal semiconductor portion faces an electrode, and the first conductivity type single crystal semiconductor portion and A method for etching a semiconductor device, wherein a voltage is applied between the electrodes to electrochemically etch the second conductivity type semiconductor portion, and the etching is stopped at the PN junction portion. The width of the depletion layer of the PN junction extending to the side is controlled to be a size obtained by subtracting the required depth of the etching from the thickness of the second conductivity type single crystal semiconductor portion.

[0008]

According to the experimental results of the present inventor, the distance from the PN junction surface to the etching stop position is determined by the width of the depletion layer of the second conductivity type semiconductor portion of the PN junction portion (the semiconductor portion on the etched side). It turned out to be almost equal to. That is, the etching ends at the tip of the depletion layer.

Therefore, in the method for etching a semiconductor device according to the present invention, the width of the junction depletion layer of the second conductivity type semiconductor portion at the end of etching is obtained by subtracting the required etching depth from the thickness of the second conductivity type semiconductor portion. Since the size is controlled, it is possible to accurately control the etching depth or the thickness of the thin portion left by etching.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor acceleration sensor to which the present invention is applied will be described below with reference to the drawings. FIG. 1 shows a perspective view of this semiconductor acceleration sensor, FIG. 2 shows a plan view of the semiconductor acceleration sensor, and FIG. 3 shows a cross section taken along the line AA of FIG.
This sensor is used in the ABS system of an automobile.

A square plate-shaped silicon chip 2 is bonded onto a square plate-shaped base 1 made of Pyrex glass. The silicon chip 2 has a rectangular frame-shaped first supporting portion 3 whose back main surface is joined to the pedestal 1, and the first supporting portion 3 is formed by using four sides of the silicon chip 2. The upper separation groove 4 is formed inside the first support portion 3 of the silicon chip 2.
a, 4b, 4c, 4d and the lower separation groove 10 are provided as recesses, and the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10 communicate with each other to form a through groove penetrating the chip 2. . A C-shaped upper separation groove 4d formed in the rectangular frame-shaped first supporting portion 3 and a lower separation groove 10 below the upper separation groove 4d.
The thick-walled U-shaped second support portion 11 and the thick-walled connecting portion 1
2 is divided and formed, and the second support portion 11 is connected to the first support portion 3 by the connection portion 12. Furthermore, the second support portion 1
A thin thin strain element 5, 6, 7, 8 is extended from the inner side surface of 1, and a thick square weight portion 9 is connected to the tip of the thin strain element 5, 6, 7, 8. Has been done.

That is, the second support portion 11 is connected to the thick first support portion 3 joined to the pedestal 1 through the connecting portion 12,
The weight portion 9 is provided from the second support portion 11 through the thin wall strain generating portions 5 to 8.
Is supported at both ends. The lower separation groove 10 is formed below the upper separation grooves 4a, 4b, 4c, 4d and the thin-walled strain generating portions 5-8, and the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10 communicate with each other. , A through groove penetrating the chip 2 is formed.

Two thin piezoresistive regions 13a, 13b, 14a, 14b, 15 are provided on the surface of each of the thin-walled strained portions 5-8.
a, 15b, 16a, 16b are formed. Further, as shown in FIG. 3, a concave portion 17 is formed in the central portion of the upper surface of the pedestal 1 so that the concave portion 17 does not come into contact when the weight portion 9 is displaced due to acceleration. The aluminum wiring pattern on the surface of the silicon chip 2 is shown in FIG.

A wiring 18 for grounding, a wiring 19 for applying a power supply voltage Vcc, and wirings 20 and 21 for output for taking out a potential difference according to acceleration are laid. or,
Another set of four wires is prepared for these wires. That is, the wiring 22 for grounding, the wiring 23 for applying the power supply voltage, and the wirings 24, 25 for outputting for extracting the potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the wiring 19 for applying the power supply voltage, and the wiring 18 for grounding intersects with the impurity diffusion layer 26 via the silicon oxide film. Similarly, the wiring 23 for applying the power supply voltage is connected to the wiring 19 for applying the power supply voltage via the impurity diffusion layer 27, and the wiring 22 for grounding is connected to the wiring 18 for grounding via the impurity diffusion layer 28. Further, the output wiring 24 is connected to the output wiring 20 via the impurity diffusion layer 29. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wirings 18 to 21 are used for connection.

Each piezoresistive region 13a, 13b, 14
a, 14b, 15a, 15b, 16a, 16b constitute a Wheatstone bridge circuit as shown in FIG. 4, a terminal 31 is a ground terminal, a terminal 32 is a power supply voltage applying terminal, and a terminal 33 and 34 are output terminals for extracting the potential difference according to the acceleration. Next, a method of manufacturing this sensor will be described with reference to FIGS. However, FIGS. 5 to 9 show AA cross sections of FIG.

First, as shown in FIG. 5, the plane orientation is (10
0) p-type substrate (second conductivity type semiconductor part in the present invention)
A wafer (semiconductor member according to the present invention) 40 having an n-type epitaxial layer (first-conductivity-type semiconductor portion according to the present invention) 42 on 41 is prepared, and piezoresistive regions 13a and 13 are provided.
b, 14a, 14b, 15a, 15b, 16a, 16b
As a result, the p ⁺ diffusion layer 43 is formed, and the n ⁺ diffusion layer 44 is formed on the surface portion of the region where the upper isolation trenches 4a, 4b, 4c, 4d are to be etched as electrode contacts during electrochemical etching. Then, a silicon oxide film (not shown) formed on the epitaxial layer 42 is selectively opened, and aluminum wirings 18 to 25 (see FIG. 2, not shown in FIGS. 5 to 8) are formed on the silicon oxide film to form an aluminum film. Wiring 18 to 25 is p ⁺ diffusion layer 4
3, and then a passivation insulating film (not shown) made of a silicon oxide film or the like is deposited, and the passivation insulating film is selectively opened to form a contact hole for wire bonding. This passivation insulating film is opened to provide an aluminum contact portion (not shown) for conduction that contacts the n ⁺ diffusion layer 44.

Next, a plasma nitride film (P-Si) is formed on the back surface of the wafer 40, that is, the front surface (back main surface in the present invention) of the substrate 41 excluding the etching planned region of the lower isolation trench 10.
N) 45 is formed, and the plasma nitride film 45 is photopatterned using a resist film (not shown) not shown. Next, a resist film (resist film in the present invention) 49 is spin-coated on the front main surface of the wafer 40, that is, on the surface of the epitaxial layer 42, which will be the regions to be etched in the upper isolation trenches 4a, 4b, 4c, 4d. Photo-pattern. The upper separation grooves 4a, 4b, 4c,
The silicon oxide film and the passivation insulating film on the region to be etched 4d have been removed in advance, and the above-mentioned aluminum contact portion for conduction is exposed on the surface of the epitaxial layer 42 exposed by the photo-patterning of the resist film 49. There is. The resist film 49 is PIQ.
(Product name, polyimide) film.

Next, as shown in FIG. 6, the wafer 40 is electrochemically etched to form the lower isolation trench 10. Hereinafter, this electrochemical etching will be described with reference to FIGS.
Will be described in detail with reference to. First, a hot plate (200 ° C., not shown) is bonded to the back surface of the support substrate 46, a resin wax W is placed on the support substrate 46 to soften it, and a platinum ribbon 59 is sandwiched on the resin wax W to hold the wafer 40. The front main surface is placed and adhered, and then the support substrate 46 and the wafer 40 are removed from the hot plate to cure the resin wax W. The tip of the platinum ribbon 59 is formed in a wavy shape, and in the cured state of the resin wax W, the tip of the platinum ribbon 59 is pressed by the aluminum contact portion by its own elasticity to make good electrical contact with the aluminum contact portion. To be The resin wax W covers the side surface of the wafer 40. In this state, the wafer 40 and the supporting substrate 46 are suspended in the etching bath 61 and immersed in an etching solution (for example, 33 wt% KOH solution, 82 ° C.). A platinum electrode plate 62 is hung so as to face the back main surface of the wafer 40, and a predetermined voltage (at least 0.6 V, here 2 V) is applied between the platinum ribbon 59 and the platinum electrode plate 62 with the wafer 40 side as positive. ) Is applied and electrochemical etching is performed. By doing this, from the platinum ribbon 59 to the aluminum contact portion, to the n ⁺ diffusion layer 4
4. An electric field for reverse biasing the junction between the two is formed on the P-type substrate 41 through the epitaxial layer 42, and
Electrochemical etching (anisotropic etching) of the substrate 41 is performed to form the lower isolation trench 10 in the substrate 41. When the etching reaches the vicinity of the junction between the substrate 41 and the epitaxial layer 42, an anodic oxide film (not shown) is formed and the etching rate is remarkably reduced, so the etching is stopped near the junction.

Next, as shown in FIG. 7, after removing the nitride film 45 with hydrofluoric acid, the support substrate 46 is placed on a hot plate to soften the resin wax W, and the wafer 40 is separated from the support substrate 46. The wafer 40 is immersed in an organic solvent (for example, trichloroethane), the resin wax W is dissolved and washed to take out the wafer 40, and then the resist 50 is applied to the entire back main surface of the wafer 40.

Since the resist 50 is not used for photo patterning, it is only necessary to allow the resist solution to flow down. As in the case of resist application for photo patterning (for example, the second resist film 49), a spinning device is used. It is not necessary to vacuum chuck the wafer 40 on the spinning table. Next, as shown in FIG. 8, the epitaxial layer 42 is dry-etched from the opening of the second resist film 49 to form upper isolation trenches 4a, 4b, 4c and 4d.

Next, as shown in FIG. 9, the resist film 49 is removed by oxygen ashing and the resist 50 is removed to complete the upper isolation trenches 4a, 4b, 4c, 4d. 4c, 4d and the lower separation groove 10 are communicated with each other to form a through groove. Subsequently, the wafer 40 is bonded onto the pedestal 1 and finally diced into chips.

Hereinafter, the thin-walled strain generating portion 5 which is an essential part of this embodiment.
The wall thickness setting methods of ~ 8 will be described below. In this embodiment,
The impurity concentration of the substrate 41 is 1 × 10 ¹⁵ atoms / cm ³ , and the impurity concentration of the epitaxial layer 42 is 7 × 10 ¹⁵ atoms / cm 3.
³ , the applied voltage Vc was 2V. This applied voltage Vc may be applied to the PN junction layer between the substrate 41 and the epitaxial layer 42. Therefore, the width (width of the depletion layer on the side of the substrate 41) wp of the portion of the junction depletion layer extending to the side of the substrate 41 in this case is 1.7 for the single crystal silicon from the following equation.
μm. wp ² = 2KεVt / (qNa (1 + Na / Nd)) where K is the relative permittivity of silicon, ε is the vacuum permittivity, and Vt
Is the sum of the applied voltage Vc and the barrier voltage at 0 bias, q is the charge amount of electrons, Na is the impurity concentration of the P-type substrate 41, and Nd is
Is the impurity concentration of the N-type epitaxial layer 42.

Now, assume that the bridge sensitivity of the sensor of this embodiment is 0.7 mV / G. From the relation between the bridge sensitivity shown in FIG.
The thickness of No. 8 may be 5.3 μm. It was found from an experiment described later that the thickness of the thin strained portions 5 to 8 after etching was equal to the sum of the thickness t of the epitaxial layer 42 and the depletion layer width wp on the substrate 41 side. It can be seen that the thickness t of the above can be set to 3.6 μm. (Experimental Example 1) FIG. 13 shows the changes in the thickness of the thin strained portions 5 to 8 when the thickness t of the epitaxial layer 42 was set to 6 μm and the applied voltage Vc was changed in the above-described embodiment. Further, the sum of the depletion layer width wp on the substrate 41 side and the thickness t of the epitaxial layer 42 is shown as a characteristic line.

From FIG. 13, the thickness of the thin-walled strain generating portions 5 to 8 is wp.
It can be seen that it matches + t. (Experimental Example 2) In the above-described example, the epitaxial layer 4 was used.
The thickness t of 2 is 6 μm, the applied voltage Vc is 2 V, and the impurity concentration of the epitaxial layer 42 is 7 × 10 ¹⁵ atoms / cm ^3.
FIG. 14 shows changes in the thicknesses of the thin strained portions 5 to 8 when the impurity concentration of the substrate 41 is changed. Further, the sum of the depletion layer width wp on the substrate 41 side and the thickness t of the epitaxial layer 42 is shown as a characteristic line.

From FIG. 14, the thicknesses of the thin-walled strain generating portions 5 to 8 are wp.
It can be seen that it matches + t. From the above experimental results, it can be understood that T = t + wp can be set in order to make the wall thickness T of the thin wall strain generating portions 5 to 8 the designed wall thickness. Further, from this equation, it is possible to accurately form a groove having a predetermined depth d by the electrochemical etching. That is, if the thickness of the substrate 41 is t ', then d = t'-wp.

However, even if the above-mentioned electrochemical etching reaches the end of the junction depletion layer, if the applied voltage is 0.6 V or less, the anodic oxide film is not well formed on the etched surface, so the etching does not stop. Therefore, it is necessary to apply a voltage higher than this minimum voltage. Further, in the above embodiment, the single crystal silicon substrate has been described, but it goes without saying that it can be applied to other semiconductor materials.

(Modification) In the above-described embodiment, the impurity concentration of the P-type substrate 41 is set to be constant and the thickness of the epitaxial layer 42 is set in consideration of the depletion layer width wp. It is also preferable to provide a P ⁺ layer (for example, 10 ¹⁸ atoms cm ³ or more) on the bonding surface of the P-type substrate 41 in contact with 42.

By doing so, the epitaxial layer 42 is formed.
The amount of extension of the junction depletion layer extending from the junction surface between the P ⁺ layer and the P ⁺ layer to the P ⁺ layer side becomes extremely small, and as a result, it can be considered that the etching almost stops at the above-mentioned junction surface. The thickness of the second conductivity type single crystal semiconductor portion) can be regarded as the required etching depth, and the work is simplified. Further, the width of the junction depletion layer extending to the substrate 41 side can be reduced even if the applied voltage is reduced or the impurity concentration of the P-type substrate 41 is increased, and the same effect as described above can be obtained.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plan view of a semiconductor acceleration sensor.

FIG. 3 is a sectional view taken along line AA of FIG.

FIG. 4 is a bridge circuit diagram of this sensor.

FIG. 5 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 6 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 7 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 10 is a cross-sectional view showing an electrochemical etching method.

11 is a plan view of the wafer and supporting substrate of FIG.

FIG. 12 is a characteristic diagram showing the relationship between the thin flexure portion (beam) thickness and the bridge sensitivity of the sensor of FIG.

13 is a characteristic diagram showing the relationship between the applied voltage and the thickness of the thin strained portion in the etching of FIG.

14 is a characteristic diagram showing the relationship between the impurity concentration of the substrate and the thickness of the thin strained portion in the etching of FIG.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshi Yoshino, 1-1, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd.

Claims (1)

[Claims] 1. A second conductivity type single crystal semiconductor part is formed by immersing a semiconductor member in which a first conductivity type single crystal semiconductor part and a second conductivity type single crystal semiconductor part form a PN junction in an etching solution. Facing the electrode, a voltage is applied between the first conductivity type single crystal semiconductor part and the electrode to electrochemically etch the second conductivity type semiconductor part, and the etching is stopped at the PN junction part. In a method of etching a semiconductor device, a width of a depletion layer of the PN junction portion extending toward a side of the second conductivity type single crystal semiconductor portion is determined from a thickness of the second conductivity type single crystal semiconductor portion to a required depth of the etching. A method for etching a semiconductor device in which the size is controlled to a value less than.