JPH06103863B2 - Data multiplexing controller - Google Patents

Description

The present invention relates to a digital data multiplexing control device.

[Prior Art] FIG. 9 shows, for example, the transmission rate 1. shown in CCITT Recommendation G.704.
544MBPS, a diagram illustrating a frame format of a 24 multiframe structure, in the figure, (1) the F bit 1 bit / frame, (2) each assigned to 8 bits / frame, T _S1 ~ with a capacity of 64KBPS There are 24 data channels up to T _S24 . FIG. 10 is a diagram showing how 9600 BPS synchronization data is multiplexed in the transmission frame shown in FIG. 9, and (3) is a 9600 BPS synchronization data signal,
In (4), the 9600 BPS synchronous data signal sequence (3) is grouped into 6 bits, and 2 bits in total, 1 bit for each F bit and 6 bits for S bit, are added to form an envelope, and the speed is increased by 8/6 times. Envelope signal of 12.8KBPS, (5) is a data signal sequence that is configured as a 64KBPS signal sequence by multiplexing the envelope signal (4) in units of 5 channels, and (6) is a 64KBPS data signal sequence (5). 1.544M
A transmission frame were multiplexed by inserting the BPS of T _S (time slots). Further, FIG. 11 is a diagram showing the configuration of a device on the transmission side when multiplexing data as described above, “New Data Transmission System” (second edition) (Sangyo Tosho Co., Ltd. edition) P.186. This is an excerpt of the transmission unit of 01 MUX and DO MUX shown in ~ 187.

In the figure, (7) is a speed conversion buffer for outputting the interfaced data from the terminal in accordance with the multiplexing timing, and (8) is multiplexing the data of a plurality of channels accumulated in the speed conversion buffer (7). A multiplexing controller, (9) is a multiframe generator for multiplexing a multiframe pattern by F'bits in a 64KBPS envelope signal (4), and (10) is a circuit for temporarily storing the multiplexed data, An elastic buffer for transmitting in synchronization with the clock, and (11) is a frame synchronization pattern generator for generating and adding F bits of the frame synchronization pattern to be added in the transmission data signal sequence.

Next, the operation will be described. The transmission frame length is 193 bits, and this transmission frame length is an 8-bit time slot T consisting of 1-bit F bit (1) and T _S1 (2) to T _S24 (2). It is divided into _S24 channels.

Since the transmission speed is 1.544MBPS, the transmission capacity allocated for each bit of 193 bits is Becomes Therefore, the transmission capacity to which F bit (1) and each T _S (2) are allocated is given as F bit; 8KBPS × 1 = 8KBPS, each T _S ; 8KBPS × 8 = 64KBPS, and each T _S (2) has 64KBPS Data is multiplexed with the basic transmission capacity as. Further, the F bit (1) is information used inside the multiplex transmission system and is used as a frame synchronization code or the like indicating a delimiter for each transmission frame, and is not used for data multiplexing from the terminal.

The manner in which the 9600 BPS synchronization data signal (3) is multiplexed for each T _S (2) will be described with reference to FIGS. 10 and 11.

9600BPS synchronization data signal synchronized with line clock (3)
Terminal data is sampled by the 9600Hz clock synchronized with the line clock and the speed conversion buffer (7)
Is taken into.

The 9600 BPS synchronization data signal (3) is read out in bursts from the speed conversion buffer (7) under the control of the multiplexing controller (8). The multiplexing control unit (8) outputs a 6-bit width gate signal to each speed conversion buffer (3), and a multi-frame generation unit (before and after the 6-bit data read by the gate signal). The F'bit and the S'bit of 2 bits in total generated in 9) are added in accordance with the multiframe multiplexing timing signal from the multiplexing controller (8). This 8-bit data signal string surrounded by F'bits and S'bits has a speed of 8/6.
It is doubled and becomes an envelope signal sequence (4) of 12.8KBPS. This envelope signal train (4) is written in the speed conversion buffer (7) in the subsequent stage as a continuous envelope train.

However, the multiplexing control unit (8) following the speed conversion buffer (7) sequentially outputs multiplex gate signals for multiplexing the five channels of the envelope signal (4), and in synchronization with this, the 12.8 KBPS envelope signal ( 4) is multiplexed on 5 channels and made into a 64KBPS data signal sequence (5), which is multiplexed into one T _S (2) having a transmission capacity of 64KBPS and written in the elastic buffer (10). On the other hand, the transmission data input to the elastic buffer (10) undergoes timing matching with the transmission path, and then the F-bit (1), which is a frame synchronization bit, is added as a delimiter for each 193 bit transmission frame, Sent to. 64KB
Each F'bit in the PS data signal string (5) is CCITT Recommendation X.5
Bit patterns are assigned as 20 multi-frame patterns at 0.

Signals of other speeds are also multiplexed in the transmission frame based on 64 KBPS in the same manner as described above.

On the receiving side, the data multiplexed and transmitted as described above is frame-synchronized as a data signal string (5) of 64 KBPS, and further multi-frame synchronized to match the terminal data rate. Demultiplexing is performed as 9600 BPS data (3).

Next, a configuration example of the speed conversion buffer (7) will be described with reference to FIG.

When the write gate signal is input to the write control unit (7b), the write signal is output to the FIFO (First-In, First-Out) memory (7a) so that each channel data has a predetermined number of bits in the FIFO memory ( Stick to 7a). At this time, at the same time, the accumulation amount detection section (7b) performs a count-up operation to count the number of bits written in the FIFO memory (7a). If a certain number or more of data is
When it is determined that the data is accumulated in the FIFO memory (7a), the multiplex gate signal that coincides with the multiplex timing is read by the read controller (7
The read control section (7c), which is supplied to c) and receives this, outputs a read signal to the FIFO memory (7a), whereby multiplexed data is output to the next stage.

In the accumulated amount detector (7b), the readable signal is output only when the amount of data in the FIFO memory (7a) has accumulated more than a certain amount. As a result, a measure is taken to make bit slippage less likely to occur on the output side.

[Problems to be Solved by the Invention] The conventional multiplexing device is configured as described above due to the relationship with the data multiplexing format, and requires two stages of multiplexing processing with different processing timings and bursts. 2 speed conversion buffers for smoothing the multiplexed data
There is no choice but to increase the circuit scale by connecting in cascade.
Since the envelope is configured to match the data rate of 1200BPS x N series to 64KBPS series, it is less than 75% (6/8 times) of the actual data bit occupied in the time slot (TS). Therefore, there is a problem that the multiplexing efficiency is lowered.

The present invention has been made in order to solve the above problems, and an object of the present invention is to obtain a data multiplexing control device that further simplifies the multiplexing process and improves the multiplexing efficiency.

[Means for Solving Problems] A data multiplexing apparatus according to the present invention includes a multi-stream existing in each transmission frame for a data string having a transmission frame format of a bit length that is easy to match with a multiplexing speed. Generation of frame synchronization bits and multiplexing processing of each data channel are performed in the same circuit in a unified manner, this multiframe is further divided into smaller multiframes, and stuff bits are added at the break point of the small multiframes. The processing is performed uniformly for various data rates.

[Operation] According to the present invention, the phase synchronization between the interface clock of each speed and the division of the small multi-frames is performed uniformly by the least common multiple timing of a plurality of small multi-frame cycles for various data rates to be multiplexed. It is possible to add the stuff bit in the speed change buffer having various configurations.

[Embodiment] The present invention will be described below based on an embodiment shown in FIG. 1 to FIG. It should be noted that the same or corresponding portions as those of the conventional one are designated by the same reference numerals, and the description will focus on the features of the present invention. Figure 1 is 320
It is a figure which shows the transmission frame format which consists of bit length, (12) in the figure is a frame synchronization bit F _{A of} 1 bit which inserts an alternating pattern of "1" and "0" for every frame,
Is header information, (14) is a control data link, and (15) is a 1-bit frame synchronization bit for multiframe synchronization.
F _B , (16) is a time slot set for each frame of each channel in the multiplexed channels provided with N channels, and (17) is a check word ECC of the error correction code. However, the transmission capacity assigned to 1 bit in the transmission frame is obtained by C = T _S / 320 [BPS], and T _S is the transmission rate [B
PS]. According to this, 64KBPS × N (N = 1 to 1
The allocated capacity per bit / frame for the transmission rate of 6) is obtained as shown in FIG. The figure shows 64KBPS x N (N = 1 to 6) and the transmission frame length is 320.
It shows the correspondence between the bit transmission frame period and the line capacity per bit. Further, in the case of 56 KBPS, the transmission frame length is 320 × 7/8 = 280 bits. Here, for the transmission rate of 56 KBPS, the transmission frame length is set to 280 hits so that the allocated capacity of 1 bit / frame becomes the same as 64 KBPS × N series. From now on, the allocated capacity per bit / frame is 200 × N (N = 1 to 1).
6) It becomes [BPS], which is the interface speed with normally used terminals 1200, 2400, 4800, 7200, 9600, 19.2K, 4
32K, 6 used for 1200BPS series such as 8K [BPS] and audio PCM
The relationship between the data rate such as 4K [BPS] and the allocated capacity does not necessarily have an integer ratio, but it can be seen that the ratio becomes an integer ratio in units of every 2 frames, every 3 frames, and every 5 frames. It

The relationship at this time is expressed by the following equation.

Here, Y is a terminal interface speed, n is the number of bits multiplexed in one transmission frame, c is 1 bit / allocated transmission capacity per frame, m is a multiframe period when stuff bits are added, and r is a multiframe period. The number of effective bits (n x
m-the number of stuff bits).

Therefore, data multiplexing is achieved by the embodiment apparatus shown in FIG. In the figure, (7) is a speed conversion buffer that stores each terminal interface data, and (8)
Is a multiplexing control unit that multiplexes a predetermined number of bits of interface data from a terminal, (10) is an elastic buffer that temporarily stores multiplexed transmission data, (11)
Is a frame synchronization pattern generation unit that generates and adds a frame synchronization bit F _A (12) in a transmission frame, (18) is a multi-frame pattern generation unit that generates a frame synchronization bit F _B pattern in a transmission frame, (19) Is a multi-frame pulse generator that generates a multi-frame pulse corresponding to the multi-frame established by the frame synchronization bit F _B (15) and a signal that divides this multi-frame into smaller multi-frames. A clock generator that smoothes the jitter component of the transmission clock including jitter and generates an interface reference clock and a frame synchronization signal that have a fixed synchronization relationship with this transmission clock. (21) divides the interface reference clock. Terminal interface clock generation that circulates to generate interface clocks of various speeds , (22) is a divider reset times for initializing the terminal in tough ace clock generating unit (21) with a period of a small multi-frame.

However, the transmission data interfaced from the terminal is
It is taken into the speed conversion buffer (7) by the interface clock of each terminal generated in the terminal interface clock generator (21). Here, in order to synchronize the transmission clock with the line clock, the interface reference clock having a fixed synchronous relationship with the line clock in the clock generation unit (20) is subjected to predetermined frequency division in the terminal interface clock generation unit (21). 1200Hz, 240
Used for terminal interface clocks such as 0Hz. Next, each terminal interface data taken into the speed conversion buffer (7) is stuffed by the multiplexing gate signal received from the multiplexing control unit (8) and sequentially multiplexed by a predetermined number of bits. . The multiplexing control section (8) is a multiplexing gate for header information H (13), control data link C (14), frame period bit F _B (15), data channel time slots CH _{1 to} CH _N (16), etc. A signal is output, multiplexing of each data channel is performed in a burst manner, header information H (13), control data link C (14),
Frame sync bit F _B (15), timeslots CH _{1 to} CH _N
Each data of (16) is written in the elastic buffer (10). On the other hand, the data written in the elastic buffer (10) in units of 301 bits is added with the frame period bit F _A (12) and the check language ECC (17) generated at the frame synchronization pattern generation unit (11) at the beginning. And is transmitted in synchronization with the line clock (64 KBPS × N). Further, the small multi-frame pulse generation section (19) divides this based on the frame synchronization signal output from the clock generation section (20) and outputs 2, 3, 5, etc. small multi-frame pulses. At this time, the multi-frame pulse generator (18) generates 30 multi-frame patterns, which is the least common multiple of 2,3,5 multi-frames, and outputs the frame synchronization bit F _B (15) from the multiplexing controller (8). Multiplex according to the gate signal. Next, each component of the above-described embodiment apparatus will be described in detail below. FIG. 4 is a diagram showing the structure of the speed conversion buffer (7). In FIG. 4, (7e) is composed of two surfaces, and double memory (7f) performs read / write at the same time apparently. Write address counter that specifies the write address for (7e), (7
g) is a read address counter that specifies a read address for the double memory (7e), (7h) is a read / write bank select unit that switches between reading and writing of the double memory (7e), and (7i) is either the double memory (7e). This is a selector that outputs one of the read data to the outside.
However, when the terminal interface data is input to the speed conversion buffer (7), this data is stored in the memory # 1 (7e),
It is given to the memory # 2 (7e). Then the memory (7e),
(7e) continuously captures data in synchronization with the terminal interface clock. At this time, a predetermined write address is given to the memory (7e) from the write address counter (7f). Which of the two-sided memory # 1 (7e) or memory # 2 (7e) the data is written to is determined by the instruction from the read / write bank select section (7h), and the memory of which writing is designated. The write address and the write signal are given only to (7e). On the other hand, the read address counter (7e) is read from the memory (7e) whose read is designated by the read / write bank select section (7h).
During the period in which the multiplex gate signal is input to g), data is read by a predetermined number of bits in synchronization with the multiplex clock. Since the read data exists in two systems, the memory # 1 (7e) side and the memory # 2 (7e) side, the selector (7i) outputs only one of the data according to an instruction from the read / write bank select section (7h). Output to the latter stage.
The read / write bank reselect unit (7h) switches between writing and reading with a pulse of a small multi-frame cycle determined by the line speed and the terminal interface speed. The operation of the speed exchange buffer (7) is shown in FIG. 5, which shows the stuffing operation when the stuff bit is added every three transmission frames. That is, the data interfaced with the terminal interface clock from the terminal is written in the M-bit unit in the speed conversion buffer (7) which switches between writing and reading every three transmission frames. After the speed conversion buffer (7) switches from writing to reading, data is read in m-bit bursts at the timing of the multiplexing gate signal,
The data m × 3 bits read during this reading period include n bits of indefinite data other than the terminal interface data. The n bits are used as stuffing bits and multiplexed with the terminal data. The indefinite data n bits of the stuffing bit are M = m × 3-n clocks in the terminal interface clock number of 3 when transferring data to the terminal from the speed conversion buffer (7) similarly configured on the receiving side. The stuffing bit is destuffed by selecting and interfacing with a number. In this way, in order to reliably perform stuffing on the transmitting side and destuffing on the receiving side, the switching timing of the double memory (7e) for each small multi-frame pulse and the phases of the writing and reading clocks are aligned. There is a need.

Next, a terminal interface clock generation unit (21) for giving a terminal interface to the speed conversion buffer (7) and a frequency division reset circuit (22) for initializing the terminal interface clock generation unit (21) will be described with reference to FIG. Detailed description. In the figure, (21a) is an independently arranged frequency dividing counter for dividing and outputting various terminal interface clocks, (22a) is an R / S flip-flop, and (22b) is a D-type flip-flop. However, speed conversion buffer (7)
The plurality of frequency dividing counters (21a) for synchronizing the phases of the writing and reading clocks in (1) divide the interface reference clock with a constant frequency division ratio and output a predetermined terminal interface clock. In addition, the small multi-frame pulse sets the RS flip-flop (22a) to generate a reset request signal. The reset request signal is sampled by the interface reference clock and becomes a reset signal synchronized with the interface reference clock. By this reset signal, the frequency division counters (21a) are reloaded to the initial pattern and the frequency division is started again. The reset signal is sampled again by the D-type flip-flop (22b) in the subsequent stage, and the RS flip-flop (22a) is reset to release the reset request signal. Since the interface reference clock uses a value of 5.76 MHz, for example, even if the timing of the small multi-frame pulse and the phase of the terminal interface clock deviate, the maximum is about 170 nsec (1 / 5.76 MHz). Clock
Even if it is 64 KHz, the jitter is only about 1%, which is not a practical problem.

The speed conversion buffer (7) is further multiplexed by receiving the multiplexing gate signal from the multiplexing controller (8) shown in FIG. The multiplexing control section (8) will be described with reference to the same drawing. (8a) is a slot number counter for counting the time slot number for multiplexing, and (8b) is a multiplexing for supplying the multiplexing bit length for each time slot. Bit length recording part, (8
c) is a multiple bit length counter that counts the multiple bit length of each time slot, (8d) is a comparator that detects whether or not multiplexing for a predetermined bit length is completed, and (8e) is a multiplex during multiplexing of N lines. A decoder for sequentially outputting M multiple gate signals based on the slot number signal, and (8f) is a gate for controlling output of the multiple gate signals. However, the slot number counter (8a) reset by the frame synchronization signal indicating the division of the transmission frame outputs N signals indicating the time slot number in the multiplexing as the slot number "0". At the same time, the frame synchronization signal also resets the multiplex bit length counter (8c) and outputs "0" as the count value, which indicates that multiplexing in slot number 0 has not been executed yet. The multiple bit length recording section (8b) outputs to the comparator (8d) what the multiplexed bit length is in the time slot for the N slot number signals output from the slot number counter (8a). . When the multiplex processing is started and the multiplex bit length counter (8c) starts counting, the comparator (8d) which receives the output from the multiplex bit length recording unit (8d) and the output from the multiplex bit length counter (8c) Monitor both signals until they match. When the multiplex processing continues and both input signals to the comparator (8d) match, the comparator (8d) passes the match signal output to the multiple bit length counter (8c) and the slot number counter (8a), Notify that the multiplexing for the slot is completed. The coincidence signal output from the comparator (8d) resets the multi-bit length counter (8c) and causes the slot number counter (8a) to count up by 1, thereby starting the multi-processing for the next time slot. By performing this operation in sequence, the N multiplexed slot number signals from the slot number counter (8a) hold each pattern for a time corresponding to a predetermined bit length. On the other hand, the N → M decoder (8e) operates so as to validate only one of the M output signals corresponding to the N input signal patterns. Since the N input signals are the slot number signals during multiplexing from the slot number counter (8a), the output signals from the N → M decoder (8e) can be used as they are as multiple gate signals. But,
When the transmission / transmission frame synchronization of the local station is not established, the multiplexing process is meaningless from the beginning, so the N → M decoder (8
In step e), all the M output signals are invalidated until the frame synchronization establishment signal is input. Once the frame synchronization establishment signal is input, the M output signals are sequentially validated and handed over to the outside. However, until the synchronization with the game is established, only the frame synchronization bit F _B multiple gate signal is operated so that the gate ( 8f) closes. In this way, the multiple gate signals to the respective units are sequentially output by a predetermined bit length by a series of operations.

The multi-frame pattern generator (18) and the multi-frame pulse generator (19) are constructed as shown in FIG. In the figure, (18a) is a 30-division counter that divides the frame synchronization signal, (19a) is a 5-division counter, (19b) is a 3-division counter, (19c) is a 2-division counter, and (19d). Is a selector that outputs a small multi-frame pulse for the frequency division reset circuit (22) based on the combination of the line speed and the multiplexed terminal data rate, and (18b) is a multi-frame pattern storage unit that outputs 30 multi-frame patterns, ( 18c) is a D-type flip-flop, (18d) is a delay for delaying the frame synchronization signal by 3 CLK, and (18e) is F _B.
It is a gate that opens according to the multiplexing timing of bit (15). However, the frequency division counter (19a), the frequency division counter (19b), and the frequency division counter (19b) reset by the frequency division reset signal
The frequency division counter (19c) outputs the frame sync signal to 5/3
/ Divide by two. The output of each frequency division counter is ANDed with the frame sync signal to form a signal with the same time width as the frame sync signal.
The multi-frame pulse is output to each unit.

On the other hand, in the selector (19d), the least common multiple of the 5/3/2 multi-frame pulse and the frame synchronization signal (corresponding to 1 multi-frame pulse) corresponding to the line speed and multiplexing format at that time, which is actually used. The small multi-frame pulse to be selected is output as a small multi-frame pulse for the frequency division reset circuit.

Also, the 30-division counter (18a) reset by the frequency-division reset signal counts the frame synchronization signal, and the output of the counter is input to the multi-frame pattern storage unit (18b) and the multi-frame pattern storage unit (18b) The multi-frame pattern corresponding to the input counter value is output. The output multi-frame pattern is latched by the pulse obtained by delaying the frame synchronization signal by 3 clocks by the delay (18b) and passes through the gate (18e). This gate (18e) is opened by the F _B bit multiplexing gate signal, and the frame synchronization bit F _B (15) pattern is multiplexed in synchronization with the F _B multiplexing timing.

In the above embodiment, when bit stuffing is performed, a method of reading extra data by the number of stuffing bits from the terminal interface data written in the speed conversion buffer (7) and multiplexing is used. It is also possible to provide a portion for generating a stuffing bit required for the addition and add this to the multiplexed data. Further, the frequency division reset circuit (22) includes one RS flip-flop (22a) and two D flip-flops (22a). Shaped flip-flop (22b)
Thus, the reset signal synchronized with the interface reference clock is generated. However, by generating a small multi-frame pulse having a width sufficiently longer (for example, 5 times) than the cycle of the interface reference clock, two D-type flip-flops are generated. You may comprise the differentiator by an AND circuit.

[Effects of the Invention] As described above, according to the present invention, since the speed conversion processing and the multiplexing processing are each configured to have one stage, the circuit scale can be reduced, and the maintenance and adjustment can be easily performed accordingly. In addition to being able to perform bit stuffing processing as needed in units of several multi-frames, most data rates of 100% multiplexing efficiency can be achieved, and a specific data rate and line speed can be combined. This has the effect that the multiplexing efficiency does not decrease.

[Brief description of drawings]

FIG. 1 is a transmission frame structure diagram showing an embodiment of a data multiplexing format handled by the data multiplexing controller according to the present invention, and FIG. 2 is a transmission rate and 1 bit / frame in the transmission frame structure shown in FIG. FIG. 3 is a diagram showing an internal configuration of an embodiment of a data multiplexing control device of the present invention, FIG. 4 is a configuration diagram of a speed conversion buffer, and FIG. 5 is a speed conversion buffer. 6 is an operation timing diagram of the terminal interface clock generator, FIG. 6 is a block diagram showing a terminal interface clock generator and a frequency division reset circuit, FIG. 7 is a block diagram showing a multiplexing controller, and FIG. Configuration diagram showing a frame pattern generation unit, ninth
FIG. 10 is a diagram showing a transmission frame configuration taken by a conventional data multiplexing control device, FIG. 10 is a frame configuration diagram showing an example of a conventional multiplexing process, and FIG. 11 is an internal view of the conventional data multiplexing control device. The configuration diagram shown in FIG. 12 is a configuration diagram of a conventional speed conversion buffer. In the figure, (7) is a speed conversion buffer, (9) is a multi-frame generator, (7a) is a FIFO memory, (7b) is a write controller, (7c) is a read controller, and (18) is a multi-frame pattern. A generation unit, (19) is a multi-frame pulse generation unit, and (21) is a terminal interface clock generation unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. Repeating a fixed length transmission frame in a line having a transmission rate of 64 KBPS × N (N is an integer of 1 or more) For a multiplexing control circuit for a multiplexed data frame having a P-bit fixed-length transmission frame in which P is an integer, a multi-frame generation unit for each P-bit fixed-length transmission frame K frame, and from this multi-frame generation unit A data pulse multiplexing unit that generates an output K multi-frame signal and a small multi-frame pulse that divides the K frame into smaller sections, and a data multiplex having a double buffer for terminal interface data input that alternates by the small multi-frame pulse. Control device. 2. A data multiplexing control apparatus according to claim 1, further comprising a terminal interface clock signal generation unit for phase-locking a delimiter of a small multiframe and a terminal interface clock by the small multiframe pulse. . 3. The data multiplexing control device according to claim 1, wherein the generation of multi-frame synchronization bits in a transmission frame and the multiplexing of data are processed in a unified manner by a single multiplexing process. 4. A fixed length transmission frame length P according to claim 1.
The data multiplexing control apparatus according to claim 1, wherein the value of is 320 bits × M (M is an integer of 1 or more).