JPH06103097A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by using a part of an error flag circuit as a path indicator for the error detecting circuit which detects an error of an arithmetic processor, etc. CONSTITUTION:A circuit system including plural error detecting circuits 20-26 and two error flag circuits 30 and 31 corresponding to the error detecting circuits 20-23 and 24-26 is divided into two circuit systems. Then a means which selects and holds all or some of error information in its system and error auxiliary information of the other system or a means which selects and holds the former part or some of the error information in its system and the error auxiliary information of the other system in coded form, and a means which segments the error information of its system and the error auxiliary information of the other system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection circuit, and more particularly to an error detection circuit for an arithmetic processing unit or the like.

[0002]

2. Description of the Related Art Many of today's computer systems
In order to detect an error in a circuit such as an arithmetic processing device, a parity bit is added to the data, and a parity check circuit for checking this is incorporated in a part of the logic circuit. In such a case, since a hardware amount increases if a parity check circuit is provided for each input data, a parity check circuit is often provided at the output of the selection circuit. However, with this configuration, it is not possible to identify which input data is in error when an error occurs. Therefore, a circuit called a path indicator that holds selection control information when an error occurs is provided as error auxiliary information for specifying this. FIG. 3 shows an example of this kind of error detection circuit.

In FIG. 3, selection circuits 10 to 12 are input data 101 to 105 including parity bits, respectively.
106 to 110 and 111 to 115 are input, and selection signals 131 to 133 are (000), (001),
At (010), (011), and (100), the input data (101, 106, 111), (102, 107,
112), (103, 108, 113), (104, 1)
09, 114) and (105, 110, 115) are selected.

The error detection circuits 24, 25 and 26 are parity check circuits of the selection circuits 10, 11 and 12 which require the error auxiliary information of the path indicator 50 when an error occurs. The error detection circuits 20, 21, 22, and 23 are parity check circuits of circuits that do not require the error auxiliary information of the path indicator 50. Error flag circuit 3
0 is the output signal 145-14 of the error detection circuit 20-23
8 is set, the error flag circuit 31 is set with the output signals 141-143 of the error detection circuits 24-26,
OR circuit 41 for output signals of error flag circuits 30 and 31
It is held by the output signal of.

The path indicator 50 has a selection signal 131,
A total of 9 bits of 3 bits 132, 133 are set, and the logical sum result of the output signal 160 of the OR circuit 40 and the output signal 161 of the OR circuit 41, which receive the outputs of the error detection circuits 20 to 26, in the OR circuit 42. Is held by the output signal 162.

For example, if the input data 101 has a parity error and the selection signal 131 is "000", the data 101 input to the selection circuit 10 is the selection signal 1
It is selected by 31 and input to the error detection circuit 24. At the same time, the selection signal 131 is sent to the path indicator 50, and the path indicator 50 has 9-bit "00".
0XXXXXXX "(" X "is an undefined value) is set.

The detection circuit 24 detects an error in the input data 101, and outputs the error signal from the error flag circuit 3 according to the output signal 141.
When it is set to 1, it is input to the OR circuit 40 at the same time.
The output signal 160 of the OR circuit 40 becomes "1", the output signal 162 input to the OR circuit 42 becomes "1", and the path indicator 50 is held. Error flag circuit 3
1 becomes “100”, and the output signal 161 of the OR circuit 41.
Becomes "1", and the error flag circuit 31 holds. Further, the OR circuit 42 becomes "1" by the output signal 161 of the OR circuit 41 being "1", and the path indicator 50 is continuously held. Since the data of the selection signal at the time of error is set in the path indicator 50, it is possible to identify which of the input data is in error from the value.

[0008]

As described above, in the conventional error detection circuit, a path indicator is provided when it is desired to check the output of the selection circuit for an error and identify which input data has an error. However, there is a drawback that the amount of hardware increases as the number of selection circuits that require path indicators increases.

[0009]

The circuit of the first aspect of the present invention is
A plurality of error detection means, a plurality of error flag means respectively corresponding to the plurality of error detection means, a circuit system including each of the error detection means and the error flag means corresponding to the error detection means, In an error detection circuit divided into two systems, an error detection circuit system that requires error auxiliary information and an error detection circuit system that does not require error auxiliary information, the error detection circuit system that does not require error auxiliary information is All or part of the error information supplied from the plurality of error detecting means in the error detecting circuit that does not require error auxiliary information, and one supplied from the error detecting circuit system that requires the error auxiliary information. Alternatively, a means for selecting a plurality of error auxiliary information and an OR operator corresponding to each system for logically ORing error information of all error detecting means in each system Characterized in that a and.

The circuit of the second aspect of the present invention includes a plurality of error detecting means, a plurality of error flag means respectively corresponding to the plurality of error detecting means, each of the error detecting means and the error detecting means. In an error detection circuit in which a circuit system including a corresponding error flag means is divided into a plurality of error detection circuit systems, all or part of each system is supplied from a plurality of the error detection means in its own system. The error information of all or part of the error information and the error auxiliary information of the other system supplied from the error detection circuit system of one or more other systems and the error information of all the error detection means in each system are displayed. OR means corresponding to the respective systems for logical OR,
An error system division information output unit that receives the information of the OR unit and outputs the division information of a plurality of error detection circuit systems, and a unit that holds the output information of the error system division information output unit are provided. And

[0011]

According to the present invention, when one of the error flag circuits for holding an error holds an error, the error flag circuit other than the target is still held in the state of "0". If the flags that are not set and can be distinguished, the flag that the error is not set can be used as a path indicator.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which the selection circuits 10 to 12, the error detection circuits 20 to 26, the error flag circuits 30 and 31 and the OR circuit 41 are the same as the circuits with the same reference numerals in FIG. Circuit. This embodiment is different from the conventional example shown in FIG.
Selection signals 131, 132, 133 and error detection circuit 2
An encoder circuit 51 for coding the output signals 141, 142, 143 of 4, 25, 26 as inputs and an error information selection circuit 60 are provided.

The error information selection circuit 60 outputs 4 bits of the output signal 134 of the encoder circuit 51 and the output signals 145 to 148 of the error detection circuits 20, 21, 22, and 23.
Selection is made by the output signal of the OR circuit 43 which receives the 3-bit output signals 141 to 143 of the error detection circuits 24, 25 and 26 as inputs. Further, the output signal of the OR circuit 44 that receives the output signals of the error detection circuits 20 to 23, the output signal of the OR circuit 43, and the output signal of the OR circuit 41 that receives the output signals of the error flag circuits 30 and 31. An OR circuit 46 that logically ORs is provided, and the output of the OR circuit 46 is "1".
At this time, the error flag circuits 30 and 31 are held.

The error information selection circuit 60 outputs the 4-bit output of the encoder circuit 51 when any one of the error detection circuits 24, 25 and 26 detects an error, for example, when the output signal 141 is "1". The selection is made and the output is inputted to the error flag circuit 30. The error flag circuit 30 also serves as a circuit as a pine indicator for setting the error information of the error detection circuits 20 to 23 and the error auxiliary information of the selection signals 31 to 133.

Table 1 shows the operation of the encoder circuit 51. The selection signals 131, 132 and 133 each have 3 bits, and a total of 9 bits output signals 141, 142 and 143 each having 1 bit, and a total of 3 bits as input. It is encoded into a 4-bit output signal 134.

[0017]

[Table 1]

For example, if the input data 101 has a parity error and the selection signal 131 is "000", the input data 101 input to the selection circuit 10 is input to the error detection circuit 24 selected by the selection signal 131. .

The error detection circuit 24 detects an error, the output signal 141 becomes "1", and the output signal 141 is guided to the encoder circuit 51, the error flag circuit 31, and the OR circuit 43. In addition, the encoder circuit 51 has a selection signal 13
Since "000" of 1 is input, the output signal 134 becomes "0000" according to the logic shown in Table 1, and is input to the error information selection circuit 60. The error information selection circuit 60 selects the output signal 134 of the encoder circuit 51 according to “1” of the output signal 151 of the OR circuit 43 and inputs it to the error flag circuit 30. Also, the output signal 1 of the OR circuit 43
The “1” of 51 is input to the OR circuit 46, and the output signal 153 thereof becomes “1” to hold the error flag circuits 30 and 31.

As a result, the error flag circuit 31 has "0".
000 "and" 100 "are set in the error flag circuit 31, and the input data 10
It turns out that 1 is in error. Error flag circuit 3
Since 1 becomes "100", the output signal 15 of the OR circuit 41
2 becomes "1", the error flag circuits 30 and 31 are continuously held, and the error flag circuits 30 and 31 are held, so that the error thereafter cannot be set.

As described above, the error flag circuit 31
If "1" is set to any one of the bits, an error has occurred in the error detection circuit system that requires the path indicator, and the error flag circuit 30 outputs the output signal of the encoder circuit 51. Will be used as a path indicator to set 134. If "000" is set in the error flag circuit 31, it means that an error has occurred in the error detection circuit system that does not require the path indicator, and the error flag circuit 30 causes the error detection circuits 20 to 23 to operate. Therefore, it is used as an error flag circuit in which the output of is set.

The encoder circuit 5 in this embodiment
An embodiment in which 1 is removed and the input to the encoder circuit 51 is set as it is in the error flag circuit 30 as a path indicator can be easily realized.

Next, another embodiment of the present invention will be described with reference to FIG. 2 and 1 are assigned common reference numerals.

The selection circuits 13-15 select the input data 116-120, 121-125, 126-130 by the selection signals 138, 137, 136, respectively, and the selection order is the same as in the selection circuits 10-12. . The error detection circuits 21 to 26 need the error auxiliary information as a path indicator when an error occurs.
15 parity check circuit, error detection circuit 2
Reference numerals 0 and 27 are parity check circuits of a circuit that does not require error auxiliary information as a path indicator.

The circuit of this embodiment is composed of the error detection circuits 20 to 20.
Error detection circuit system including 23 and error detection circuit 24 to
It is divided into two error detection circuit systems including 27. The error information selection circuit 61 includes error detection circuits 20-2.
OR circuit 44 to which the output signals 145 to 148 of 3 are input
The 4-bit error information from the error detection circuits 20 to 23 and the 4-bit error auxiliary information which is the output signal 134 of the encoder circuit 51 are selected by the output signal 150 of FIG. On the other hand, the error information selection circuit 62 receives the output signals 151 of the error detection circuits 24 to 27 from the OR circuit 45 and receives the output signals 151 to 144 of the error detection circuits 24 to 27.
The 4-bit error information from 4 to 27 and the 4-bit error auxiliary information which is the output signal 135 of the encoder circuit 52 are selected. The error information selection circuits 61 and 62 are connected to the error flag circuits 30 and 31, respectively.

The encoder circuit 52 outputs the selection signals 138, 1
This is a circuit for inputting 9 bits each of 3 bits of 37 and 136 and 3 bits each of 1 bit of output signals 146, 147, and 148 to code into an output signal 135 of 4 bits, the logic of which is an encoder circuit. Same as 1.

The OR circuit 45 is an error detection circuit 24-7.
Of the output signals 141 to 144 of the error flag circuit 31, the OR circuit 47 is a circuit of the output signal of the error flag circuit 30, and the OR circuit 48 is the error flag circuit 31.
Of the output signal of the OR circuit 48, and the OR circuit 48 is the circuit of ORing the output signal of the error flag circuit 31. The OR circuit 46 is a circuit that ORs the output signals of the OR circuits 44, 45, 47 and 48, and holds the error flag circuits 30 and 31 when the output of the OR circuit 46 is "1".

The output of the OR circuit 44 is set in an error switching information holding circuit 70 for holding information as to which system has detected the error. When the value set in the error switching information holding circuit 70 is "1", it indicates that an error has occurred in the error detection circuit system including the error detection circuits 20 to 23. At this time, the error flag circuit 3
Error information is set to 0 and error auxiliary information is set to the error flag circuit 31. When it is "0", it indicates that an error has occurred in the group of error detection circuits 24 to 27, and at this time, error auxiliary information is set in the error flag circuit 30.

For example, if the input data 101 has a parity error and the selection signal 131 is "000",
The data 101 input to the selection circuit 10 is the selection signal 131.
Is input to the error detection circuit 24.

The error detection circuit 24 detects an error and the output signal 141 becomes "1", and at the same time, the encoder circuit 51
And the error flag circuit 31 and the OR circuit 45. The encoder circuit 51 also receives the selection signal 131 “00”.
0 "is input and the output signal 134 becomes" 0000 "according to the logic shown in the display, and is input to the error information selection circuit 61.

The error information selection circuit 61 selects the output signal 134 of the encoder circuit according to "0" of the output signal 150 of the OR circuit 44, and sets the flag circuit 3 as error auxiliary information.
“0000” is set to 0.

The error information selection circuit 62 receives the output signal 151 of the OR circuit 45 from "1", and the error detection circuits 24-2.
7 output signals 141 to 144 are selected, and "1000" is set in the flag circuit 31 as error information.

"1" of the output signal 151 of the OR circuit 45 is input to the OR circuit 46, the output signal 153 becomes "1", and the error flag circuits 30 and 31 are held. Since the error flag circuit 31 becomes "1000", the output signal 154 of the OR circuit 48 becomes "1" and is supplied to the OR circuit 46, and the output signal 153 of the OR circuit 46 becomes "1", and the error flag circuits 30 and 31 continue to operate. Hold on. Since the error flag circuits 30 and 31 are held, it becomes impossible to set the error thereafter. As a result, the error flag circuit 30 holds “0000”, the error flag circuit 31 holds “1000”, and the error switching information holding circuit 70 holds “0”. It turns out that is in error.

The encoder circuit 5 in this embodiment
An embodiment in which 1, 52 are removed and the output signals to the encoder circuits 51, 52 are directly set as the path indicators can be easily realized.

Further, although the embodiment shown in FIG. 2 is divided into two error detection circuit systems, the present invention is not limited to this, and it is possible to divide into a plurality of circuit systems. The good news is clear.

[0036]

As described above, according to the present invention, the flag circuit in which an error is set and the flag circuit in which an error is not set can be separated so that the flag circuit in which the error is not set can be provided. By using a circuit configuration that is used as a path indicator,
This has the effect of reducing the amount of hardware of the path indicator.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional error detection circuit.

[Explanation of symbols]

 10-15 selection circuit 20-27 error detection circuit 30, 31 error flag circuit 40-48 OR circuit 50 path indicator 51-52 encoder circuit 60-62 error information selection circuit 70 error switching information holding circuit

Claims (4)

[Claims] 1. A plurality of error detecting means, a plurality of error flag means respectively corresponding to the plurality of error detecting means, each of the error detecting means and the error flag means corresponding to the error detecting means. An error detection circuit in which the circuit system including the error detection circuit system that requires the error auxiliary information and the error detection circuit system that does not require the error auxiliary information are divided into two systems. In the circuit system, all or part of the error information supplied from the plurality of error detecting means in the error detecting circuit that does not need the error auxiliary information, and the error detecting circuit system that needs the error auxiliary information. Means for selecting one or more error auxiliary information supplied, and each of the above-mentioned logical OR of the error information of all error detection means in each system Error detecting circuit, characterized in that a the corresponding OR means. 2. An encoding means for encoding a plurality of error auxiliary information supplied from an error detecting circuit system requiring the error auxiliary information as an input, and an error detecting circuit system not requiring the error auxiliary information. All or part of the error information supplied from the plurality of error detecting means in the error detecting circuit that does not require the error auxiliary information, and one supplied from the error detecting circuit system that requires the error auxiliary information. The means for selecting one or a plurality of pieces of error auxiliary information, and the OR means corresponding to each system for logically adding the error information of all error detecting means in each system are provided. Error detection circuit. 3. A plurality of error detecting means, a plurality of error flag means respectively corresponding to the plurality of error detecting means, and each error detecting means and an error flag means corresponding to the error detecting means. In an error detection circuit in which the circuit system is divided into a plurality of error detection circuit systems, all or a part of the error information supplied from a plurality of the error detection means in the own system to all or part of each system And means for switching error auxiliary information of another system supplied from one or a plurality of error detection circuit systems of other systems, and each system corresponding to the logical sum of error information of all error detection means in each system OR means for receiving the information of the OR means, and error system isolation information output means for outputting isolation information of a plurality of error detection circuit systems, and error system isolation information output means. An error detection circuit provided with means for holding output information of a stage. 4. Encoding means corresponding to all or part of each system for encoding with error auxiliary information supplied from a plurality of said error detection circuits in its own system, and a plurality of encoding devices in its own system Selecting means for selecting all or part of the error information supplied from the error detecting means and output of the encoding means of one or more other systems, corresponding to all or part of each system. An OR system corresponding to each system for logically calculating error information of all error detecting units in each system, and error system division information for receiving information of the OR unit and outputting division information of a plurality of error detection circuit systems 4. The error detection circuit according to claim 3, further comprising output means and means for holding output information of the error-system-separation-information output means.