JPH06101818B2 - Multi-screen display control circuit and video equipment including the same - Google Patents

Description

TECHNICAL FIELD The present invention relates to a multi-screen display control circuit that displays a reduced sub-screen on a part of a main screen, and a video device including the same.

(B) Conventional technology In recent years, in order to make effective use of the cathode ray tube screen of a television receiver, a part of the original TV screen (parent screen) is reduced by reducing the playback screen of another TV program or VTR. Television receivers, VTRs, etc. equipped with so-called picture-in-picture technology, which displays images as screens, have been announced. Generally 1 / vertically and horizontally in part of the parent screen
When displaying a N (N> 1) reduced child screen, all horizontal scan lines per field of the child screen are the same as those of the parent screen.
Since it becomes 1 / N times, by appropriately weighting the information for each horizontal scanning line in units of N lines among all the horizontal scanning lines, by adding the information for each N horizontal scanning lines. ,
Information for one horizontal scan is obtained from information for N horizontal scans, and
The information for horizontal scanning is written in the field memory, and then the information written in the field memory is time-compressed to 1 / N for each horizontal scanning and read out at the display position of the sub-screen. Was being synthesized.

(C) Problems to be Solved by the Invention However, when displaying a 1 / N reduced child screen in both the vertical and horizontal directions on a part of the parent screen, N of all horizontal scanning lines in the parent screen are displayed. Information for each horizontal scanning line in units of is multiplied by an appropriate weighting coefficient, and the multiplication result is added every N horizontal scannings, whereby information for one horizontal scanning can be obtained from the information for N horizontal scannings. become. However, the weighting coefficient for each of the N horizontal scanning lines is a coefficient less than 1 having a decimal point and is set so that the total of the weighting coefficients for the N horizontal scannings becomes 1. The information below the decimal point of the multiplication result obtained by multiplying the line information by the weighting coefficient will be truncated. Therefore, since a truncation error has already occurred in the multiplication result of each horizontal scanning line, even if the multiplication results of each horizontal scanning line in which these truncation errors have occurred are added, a large error will occur in the addition result. , More appropriate one
There is a problem that information for horizontal scanning cannot be obtained and a predetermined portion of information to be displayed on the child screen is missing.

(D) Means for Solving the Problem The present invention is a multi-screen display control circuit that displays a vertically and horizontally reduced child screen on a part of a parent screen. An A / D converter for quantizing a signal into a plurality of digital data of predetermined bits;
The digital data output from the / D converter and applied to the first input terminal of one horizontal scanning line is selectively multiplied by any of a plurality of coefficients, and the multiplication result is output from the first output terminal,
The digital data applied to the second input terminal is prohibited or permitted to pass the digital data for one horizontal scan before the predetermined horizontal scanning than the digital data applied to the first input terminal, and the permitted digital data is converted to the first digital data. A data selection circuit that outputs from two output terminals, an adder that adds the digital data output from the first and second output terminals of the data selection circuit, and an upper predetermined bit of each addition data obtained by the adder Are written for one horizontal scan, and the lower remaining bits of each addition data obtained by the adder are written for one horizontal scan, and the read digital data is read by the data selection circuit. A third line memory that returns to the second input terminal and either the digital data read from the first or second line memory is selected, and the selected one is selected. A first memory data selection circuit that returns digital data to the second input terminal of the data selection circuit, and one of the digital data read from the first or second line memory is selected, and the selected digital data is selected. Second memory data selection circuit for writing data into the data memory for each horizontal scanning line, and clock selection for selecting a predetermined write clock or a read clock having a frequency lower than the write clock for the first and second line memories. A circuit, and by constantly applying the write clock to the third line memory, the first and third circuits are selected based on the selected output of the clock front end circuit.
The above problem is solved by driving a line memory or a combination of the second and third line memories.

(E) Action The present invention is provided in a multi-screen display control circuit that displays a reduced child screen on a part of the parent screen, and is effective as follows. First, the video signal included in one horizontal scanning line is quantized by the A / D converter into a plurality of digital data of predetermined bits. The quantized digital data for one horizontal scan is applied to the first input terminal of the data selection circuit, and the multiplication result of the digital data and any one of the plurality of coefficients is output from the first output terminal of the data selection circuit. It On the other hand, the digital data for one horizontal scan before the predetermined horizontal scan is applied to the second input terminal of the data selection circuit rather than the digital data applied to the first input terminal of the data selection circuit, and the digital data is passed through. Is permitted or prohibited, the permitted digital data is the second data of the data selection circuit.
It is output from the output terminal. In this way, the digital data output from the first and second output terminals of the data selection circuit are added by the adder to be digital data for one horizontal scan. Then, the upper predetermined bits of each addition data obtained by the adder are written to the first and second line memories for one horizontal scanning, and the remaining lower bits of each addition data obtained by the adder are set to 1 in the third line memory.
The digital data written for the horizontal scanning and read from the third line memory is fed back to the second input terminal of the data selection circuit as the lower remaining bits of the digital data before the predetermined horizontal scanning. Also, any of the digital data read from the first or second line memory based on a write clock to be described later is transferred to the second input terminal of the data selection circuit via the first memory data selection circuit before the predetermined horizontal scanning. Is returned as upper predetermined bits of the digital data of the first digital data,
Any of the digital data read from the line memory will be written into the data memory for each horizontal scanning line via the second memory data selection circuit. Here, the predetermined write clock and the read clock having a frequency lower than the write clock are selected by the clock selection circuit for the first and second line memories, and the write clock is always applied to the third line memory. Is. As described above, the first and third line memories or the combination of the second and third line memories are alternately driven based on the output of the clock selection circuit.
The third line memory will be used as a memory of bits representing the fractional part of the data.

(F) Example The details of the present invention will be specifically described with reference to the illustrated example.

FIG. 1 is a block diagram showing a multi-screen display control circuit of the present invention, and FIG. 2 is an explanatory diagram for obtaining a video signal of a child screen which is reduced by 1/3 in the vertical direction and the horizontal direction.
A solid line and a broken line each represent one horizontal scanning line, and it is assumed that a screen for one field is formed as a whole. FIGS. 3A and 3B are timing charts showing the operation of the first and second line memories of FIG. 1, respectively.
It is a horizontal scanning period, and the time a _{0 to} a ₀ ′, a ₀ ′ to a ₀ ″ is one cycle of the operation.

Describing the symbols and the configuration of FIG. 1, (1) is MP
X (multiplexer), and the MPX (1) is, for example, 5M
With the sampling frequency of Hz, the luminance signal Y and the color difference signals RY and BY that compose the composite video signal included in each horizontal scanning line are repeated in the order of Y, RY, Y, and BY. To sample. That is, the sampling frequency of the luminance signal Y is 2.5 MHz, and the sampling frequencies of the color difference signals RY and BY are 1.25 MHz, respectively. (2) is an ADC (A / D converter), and the ADC (2) is a signal Y, RY, Y, B- sampled for each horizontal scanning line by the MPX (1).
Each Y, ... Is quantized into 6-bit digital data.
(3) is a data selection circuit, which is determined for each horizontal scanning line when the 6-bit digital data output from the ADC (2) is applied to the first input terminal a according to the sampling order. Either the weighting coefficient "1" or "2" is multiplied by the digital data for one horizontal scan. In the multiplication in the data selection circuit (3),
When multiplying by "2", "0" is added to the least significant bit of the input digital data of 6-bit configuration to make the whole into 7-bit configuration. When multiplying by "1", the input 6 "0" is added to the least significant bit of the bit-structured digital data, and the whole is output as a 7-bit structure.
Here, the factors of “2” and “1” are that the sub-screen is 1 /
In order to compress it to 3, the horizontal scan line n- shown in FIG.
When performing the compression operation with three horizontal scan lines of 1, n, n + 1 as one horizontal scanning line, the weighting of the sampling data of n−1, n + 1 and the sampling data of n is added as 1: 2, and after the addition, This is to make the data 1/4. The process of making the data 1/4 is performed by truncating the lower 2 bits of the data, which will be apparent later. The result of this multiplication is output from the first output terminal a ′ as 7-bit digital data, and the 8-bit data corresponding to one horizontal scan before the predetermined horizontal scan is output from the digital data applied to the first input terminal a. When digital data is applied to the second input terminal b, its passage is prohibited or permitted, and
Digital data having a bit structure is output from the second output terminal b '. Reference numeral (4) is an adder, which adds digital data of 7-bit structure and 8-bit structure sequentially output from the first output terminal a ′ and the second output terminal b ′ of the data selection circuit (3) to carry. The 8-bit addition result including is output. (5) is a shift register group having 6 columns of 252 bit shift registers (first line memory), and (6) is a shift register group having 6 columns of 252 bit shift registers (second line memory). Is. The shift register groups (5) and (6) each have an input connected to the upper 6 bits of the 8-bit output of the adder (4), and the higher order of the digital data output from the adder (4). It stores and holds 252 6 bits, that is, data for one horizontal scanning period. The reason for providing the shift register groups (5) and (6) will be clarified later, but one of the shift register groups (5) and (6) is used for sampling data applied from the ADC (2). This is so that the data can be simultaneously taken out from the other one of the shift register groups (5) and (6) in which the already compressed data is held, while the compression operation is being performed. (1
1) is a shift register group (third line memory) provided with two rows of shift registers having a 252 bit configuration, the input of which is connected to the lower 2 bits of the 8-bit output of the adder (4), The output is connected to the lower 2 bit inputs of the second input terminal b of the data selection circuit (3). The shift register group (11) is used only for data compression operation in combination with the shift register group (5) or (6), and the 8-bit data output from the adder (4) Of these, the lower 2 bits are stored and held for one horizontal scanning period of data. That is, as mentioned above, 1:
The shift register group (11) holds the lower 2 bits which are truncated to perform the process of halving the data after adding the data weighted to 2 until the end of the compression operation. In other words, the shift register group (11) is 1 /
This is a register that holds the fractional part generated by the operation. (7) is the shift register group (5)
It is a clock selection circuit for selecting the shift clock of (6), and the output of the counter (8) that counts the horizontal synchronizing signal of the main screen outputs a write clock of 5 MHz or 1.67 MHz which is 1/3 frequency of the write clock. Any one of the read clocks is selected. That is, the clock selection circuit (7) applies a write clock to the other one of the shift register groups (5) and (6) while a read clock is applied to one of the shift register groups (5) and (6). Here, the write clock and the read clock are
PLL circuit (not shown) based on the horizontal sync signal of the child screen
A write clock of 5 MHz, which is created by the above, is always applied to the shift register group (11). (9) is a first memory data selection circuit, and the first memory data selection circuit (9) is shifted by one horizontal scanning from any of the shift register groups (5) and (6) by a write clock. 6-bit digital data is selected, and the selected digital data is fed back to the upper 6 bits of the 8-bit input of the second input terminal b of the data selection circuit (3). Therefore, the second input terminal b of the data selection circuit (3)
The 8-bit addition digital data is fed back to. Reference numeral (10) is a second memory data selection circuit, and the second memory data selection circuit (10) is read from one of the shift register groups (5) and (6) for one horizontal scanning by a read clock. By selecting the 6-bit digital data and outputting the selected digital data as it is, the lower 2 bits of the 8-bit data after the addition processing are truncated, and the 1/4 processing is performed. Here, the first memory data selection circuit (9) and the second memory data selection circuit (10) select one of the outputs of the shift register groups (5) and (6) according to the output of the counter (8). To do.

(12) is a group of shift registers provided with 6 columns of 4-bit shift registers (12a), (13) is a group of shift registers provided with 4 columns of 6-bit shift registers (13a), and (14) of a chain line is a bit It is a conversion circuit. Here, 6-bit digital data output from the second memory data selection circuit (10) according to the sampling order, that is, signals Y, RY,
The high-order 6-bit digital data corresponding to Y and BY are respectively y ₇ y ₆ y ₅ y ₄ y ₃ y ₂ , r ₇ r ₆ r ₅ r ₄ r ₃ r ₂ , y ₇ y ₆ y ₅ y ₄ y ₃ y ₂ , b ₇ b ₆ b ₅
b ₄ b ₃ b ₂ , and the 6-bit digital data is serially written in the shift register group (12) in 4-bit units, that is, 6-bit digital data is y ₇ y ₆ y ₅ y ₄
y ₃ y ₂ , r ₇ r ₆ r ₅ r ₄ r ₃ r ₂ , y ₇ y ₆ y ₅ y ₄ y ₃ y ₂ , b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ When the shift register (12a) is sequentially shifted from the left end to the right end, the six columns of the shift register (12a) are
6-bit digital data set in each bit of a) y ₇ y ₆ y ₅ y ₄ y ₃ y ₂ , r ₇ r ₆ r ₅ r ₄ r ₃ r ₂ , y ₇ y ₆ y ₅ y ₄ y ₃ y ₂ , b ₇ b ₆ b ₅
b ₄ b ₃ b ₂ are preset input to the shift register (13a) of 4 columns in parallel respectively, and then 4 bits of digital data y ₇ r ₇ y ₇ b ₇ , y ₆ r ₆ y ₆ b ₆ , y ₅ r ₅ y ₅ b ₅ , y ₄ r ₄ y ₄ b ₄ ,
y ₃ r ₃ y ₃ b ₃ and y ₂ r ₂ y ₂ b ₂ are sequentially shifted from the upper bits of the shift register (13a) in four columns as bit-converted digital data. It should be noted that all of the 4-bit digital data must be read from the shift register group (13) during a period in which the next 6-bit digital data is written to the shift register group (12). Therefore, the shift clock of the shift register group (13) is 6/4 = 1.5 times that of the shift register group (12), that is, 2.5 MHz. (15) is RAM
(Data memory) and the shift register group (13)
The data for one field, which is sequentially shifted from, is stored. When a general-purpose RAM is used, the RAM basically has a 4-bit structure, so that the RAM can be one chip.

The operation of FIG. 1 will be described below with reference to FIGS. 2 and 3.

First, in order to display the child screen which is vertically and horizontally reduced by 1/3 in a part of the parent screen, the number of horizontal scan lines of the child screen must be reduced to 1/3 of that of the parent screen. No, that is, the second
By appropriately weighting the information of the three horizontal scanning lines n-1, n, n + 1 on the original screen in the figure, for example, the weighting of the horizontal scanning line n is made the heaviest, and the information of the horizontal scanning line n is forward and backward. The information of one horizontal scanning line in the sub-screen may be obtained by supplementing the information of the horizontal scanning lines n-1 and n + 1. As described above, in the present embodiment, n-1, n + 1 and n are 1: 2.
I am trying. Here, the selections by the clock selection circuit (7), the first memory data selection circuit (9), and the second memory data selection circuit (10) are switched synchronously every time the counter (8) counts three. To do. First 3rd
In the period a ₀ a _{1 in the} figure, the counter (8) counts the horizontal synchronizing signal, the count number of the counter (8) is incremented by 1, and the write clock of 5 MHz is applied to the shift register group (5). With the first memory data selection circuit (9) controlled to select the output of the shift register group (5), a luminance signal Y and a color difference signal that form a composite video signal included in the horizontal scanning line n-1. R
-Y, BY is sampled by MPX (1) in the order of Y, RY, Y, BY, and signals Y, RY, Y, BY, ...
By (2), it is quantized into digital data of 6-bit structure at 5 MHz. If all digital data of 6-bit configuration of the horizontal scanning line n-1 is Hn- ₁ , digital data Hn- ₁
Is applied to the first input terminal a of the data selection circuit (3),
A 7-bit multiplication result Hn _-1 obtained by multiplying the digital data Hn _-1 by the weighting coefficient 1 is output from the first output terminal a'and applied to the adder (4). At this time, the second input terminal b
The passage of digital data applied to is prohibited, and zero is output from the second output terminal b '. Therefore adder (4)
Adds zero represented by 8 bits to the multiplication result Hn _-1 ,
The bit addition result Hn _-1 is output. And adder (4)
The lower 2 bits of the 8-bit addition result Hn _-1 output from are sequentially written to the shift register group (11) which is always shifted at 5 MHz, while the upper 6 bits of the addition result Hn _-1 are , 5 MHz are sequentially written in the shift register group (5). Therefore, the horizontal scanning line n-1
At the end of the period of, the shift register groups (5) and (11) receive all the data Hn _-1 (252) in one horizontal scanning period.
Stored in bits. Next, in period a ₁ a _{2 of} Fig. 3,
The counter (8) counts the second horizontal synchronizing signal, the count number of the counter (8) is further incremented by 1, and the write clock of 5 MHz is continuously applied to the shift register group (5) as well. With the first memory data selection circuit (9) controlled to select the shift register group (5), the composite video signal included in the horizontal scanning line n is sampled by the MPX (1),
The sampled signals Y, R−Y, Y, B−Y, ...
By (2), it is quantized into digital data of 6-bit structure at 5 MHz. Assuming that all 6-bit digital data of the horizontal scanning line n is Hn, the digital data Hn is applied to the first input terminal a of the data selection circuit (3) and multiplied by the digital data Hn and the weighting coefficient “2”. The 7-bit multiplication result 2Hn is output from the first output terminal a'and applied to the adder (4). At this time, the 6-bit data of the shift register group (5) from the first memory data selection circuit (9) and the shift register group (11) are supplied to the second input terminal b.
Hn _-1 composed of 2-bit data is sequentially fed back,
It is output from the second output terminal b ′ via the data selection circuit (3), applied to the adder (4), and added to the multiplication result 2Hn. Then, the lower 2 bits of the addition result Hn _-1 + 2Hn of each bit configuration output from the adder (4) are written to the shift register group (11) at 5 MHz, while the addition result Hn
The upper 6 bits of _-1 + 2Hn are written in the shift register group (5) at 5 MHz. When the period of the horizontal scanning line n is finished, the horizontal scanning line n- is stored in the shift register group (5).
All data Hn _-1 + 2Hn of the weighted sum of 1 and n are stored. Next, in the period a ₂ a 3 in FIG. ₃ , the counter (8) counts the third horizontal synchronizing signal, the count number of the counter (8) is further incremented by 1, and the write clock of 5 MHz is also shifted. Register group (5)
, The composite video signal included in the horizontal scanning line n + 1 is MPX (1) while the first memory data selection circuit (9) is controlled to select the shift register group (5). The sampled signals Y, RY, Y, BY, ... are respectively sampled by ADC (2)
Is quantized into digital data of 6 bits at 5 MHz. Assuming that the 6-bit horizontal digital data of the horizontal scanning line n + 1 is Hn _{+ 1} , the digital data Hn _{+ 1} is applied to the first input terminal a of the data selection circuit (3), and the digital data Hn _{+ 1} and the weighting are applied. The 7-bit multiplication result Hn _{+ 1} multiplied by the coefficient "1" is output from the first output terminal a'and applied to the adder (4). At this time, the second
8-bit digital data fed back to input terminal b
Hn _-1 + 2Hn is allowed to pass, is output from the second output terminal b ', is applied to the adder (4), and is added to the multiplication result Hn ₊₁ in the adder (4). Then, the lower 2 of the addition result Hn _-1 + 2Hn + Hn ₊₁ of the 8-bit configuration output from the adder (4)
Bits are written to the shift register group (11) at 5 MHz, and the upper 6 bits of the addition result are written to the shift register group (5) at 5 MHz. Therefore, the horizontal scanning line n
When the +1 period ends, the shift register group (5)
In this case, the data obtained by compressing the sampling data for three horizontal scanning lines, that is, the digital data Hn _-1 + 2Hn + Hn ₊₁ for one horizontal scanning of the child screen is stored.

Then, in the period a ₃ a ₀ ′ in FIG. ₃ , when the counter (8) counts the horizontal synchronizing signal of the horizontal scanning line n + 2 and the count number of the counter (8) is incremented by 1, the clock selection circuit ( Since the output by 7) is controlled so that it can be switched in units of 3 counts by the counter (8), the read clock 1.67MHz is applied to the shift register group (5), and the second memory data selection circuit (10) Since the shift register group (5) is selected, the compressed data held at the end of the period a ₀ a ₃ Hn _-1 + 2H
n + Hn _{+ 1} is sequentially read at 1.67 MHz, that is, 1/3 the speed of the data compression operation. The read data is the upper 6 bits of the 8 bits obtained by the data compression operation,
That is, it is the result of performing 1/4 processing. Furthermore, during a ₃ a ₀ ′ period, the write clock of 5 MHz is applied to the shift register group (6).
Is applied to the first memory data selection circuit (9) and is controlled to select the shift register group (6),
The shift register groups (6) and (11) are combined, and in this state, digital data Hn ₊₂ + 2Hn ₊₃ + Hn ₊₄ for one horizontal scan is generated in the same manner as in the a ₀ a ₃ period.
Will be stored and stored in. Thereafter, the same operation is repeated with the a ₀ a ₀ ′ period as one cycle, and the shift register groups (5) and (6) repeat the data compressing operation and the data reading operation.

And digital data for one horizontal scan Hn _-1 + 2Hn + Hn ₊₁
When the upper 6 bits of 4 are serially set in the shift register group (12) by 4 bits in accordance with the sampling order, the digital data is bit-converted as described above and set in the shift register group (13) to form a 4-bit configuration. Is output from the shift register group (13) and stored in the RAM (15). This operation is repeated for 1 field, and the data for 1 field of the child screen is stored in RAM (1
It will be remembered in 5).

From the above, 3 using shift register group (5) or (6)
The other shift register group (6) or (5) in the period for creating digital data for one horizontal scanning line from the horizontal scanning line.
Since the digital data for one horizontal scanning line created in the period three horizontal scans before the creation period is read from the shift register group (6) or (5) by, the shift register groups (5) and (6) The frequency of the read clock may be lower than that of the write clock, and even if a high-speed shift register group is used, there is a margin in its specifications.

Also, the multiplication result of multiplying the sampling data by the coefficient,
And the addition result of adding the already-multiplied data to the multiplication result, without performing truncation for bit alignment, shift register group dedicated to bits to be truncated (11)
By providing the compressed data without the truncation error, the image quality of the small screen is improved.

The present invention is effective when installed in a video device such as a VTR, a TV receiver, a word processor and the like.

(G) Effect of the Invention According to the present invention, when a child screen reduced in the vertical direction and the horizontal direction is displayed on a part of the parent screen, a predetermined number of all horizontal scanning lines in the parent screen are used as a unit. By multiplying the information for each horizontal scanning line by an appropriate weighting coefficient and adding the multiplication result for each predetermined horizontal scanning, the information for one horizontal scanning line can be obtained from the information for the predetermined horizontal scanning line. However, since there is no truncation error in the multiplication result before the addition, information for one horizontal scan having a small error can be obtained, and an advantage that the information to be displayed on the child screen can be prevented from being lost can be obtained. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a multi-screen display control circuit of the present invention, FIG. 2 is an explanatory diagram for obtaining a video signal of a child screen, and FIG. 3 is a timing diagram showing an operation of the line memory of FIG. is there. (2) ... ADC, (3) ... Data selection circuit, (4) ... Adder, (5) (6) (11) ... Shift register group, (7) ...
Clock selection circuit, (9) ... First memory data selection circuit, (10) ... Second memory data selection circuit, (15) ... RA
M.

Claims (2)

[Claims] 1. A multi-screen display control circuit for displaying a child screen reduced in a vertical direction and a horizontal direction on a part of a main screen, wherein a video signal included in one horizontal scanning line is a plurality of digital data of predetermined bits. And an A / D converter that quantizes to, and digital data output from the A / D converter and applied to the first input terminal of one horizontal scanning line by selectively multiplying one of a plurality of coefficients, and the multiplication result Is output from the first output terminal and is prohibited or permitted to pass digital data for one horizontal scan before the predetermined horizontal scan than the digital data applied to the second input terminal and applied to the first input terminal. Then, a data selection circuit that outputs the permitted digital data from the second output terminal, an adder that adds the digital data output from the first and second output terminals of the data selection circuit, and an adder First and second line memories in which the upper predetermined bits of each of the added data obtained by writing are written for one horizontal scanning, and the lower remaining bits of each of the added data obtained by the adder are written for one horizontal scanning and read. A third line memory that returns the output digital data to the second input terminal of the data selection circuit, and one of the digital data read from the first or second line memory is selected and selected. A first feedback of digital data to the second input terminal of the data selection circuit
A memory data selection circuit, and a second memory data selection circuit for selecting one of the digital data read from the first or second line memory and writing the selected digital data into the data memory for each horizontal scanning line. And a clock selection circuit that selects a predetermined write clock or a read clock having a frequency lower than the write clock for the first and second line memories, and always applies the write clock to the third line memory. By doing so, the multi-screen display control circuit is characterized by driving the first and third line memories or the combination of the second and third line memories based on the selection output of the clock selection circuit. 2. A video equipment comprising the multi-screen display control circuit according to claim 1.