JPH06100927B2 - Programmable controller - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a programmable controller (hereinafter abbreviated as PC) having a function of selectively outputting high frequency pulses of various frequencies suitable for use in precision positioning control and the like. .

BACKGROUND OF THE INVENTION As an example of positioning control using a high frequency pulse, there is a case where a long electric wire is cut into a predetermined length by a cutter. For example, an electric wire that moves at a speed of 40 m / s
When cutting every m, in order to reduce the error, it is controlled to input a pulse into the counter every 1 ms, that is, every time the wire moves 4 cm, and cut it when 10 pulses are counted, but the timing of cutting A deviation of 1 ms will cause an error of 4 cm in the length of the cut wire, so high-speed and time-accurate control using high-frequency pulses of 1 kHz or more in terms of frequency is required.

Therefore, when a commercially available oscillator is used as the pulse supply source, the oscillator itself is expensive, and the commercially available oscillator is for measurement and is not made for general industry.
There were problems such as lack of reliability and difficulty in mounting on the board surface at the factory site where environmental conditions such as temperature, humidity and noise were bad.

In recent years, more general-purpose PCs have been adopted for sequence control of various devices than dedicated relay control boards.
The PC is specially designed to withstand the environmental conditions at the factory site, so if the high-frequency pulse required for positioning control can be output from the PC, the above problems will be solved.

In order to output the pulse signal from the PC, there is also a method of turning on / off the output every scan by a sequence command. However, with this method, the frequency of the output pulse is
It is determined by the arithmetic processing speed of the PC, the so-called scan time (generally 10 to 20 ms). As described in JP-A-58-195902, the conventional 2 to 10 is used with special measures to improve the arithmetic processing speed. Even if the speed is doubled, 1k
It is not possible to obtain a stable pulse output with a cycle of Hz or higher, and it is not possible to select and take out a pulse with an arbitrary frequency.

This is because the microcomputer is used for arithmetic processing inside the PC and serial serial processing is performed, so when processing many sequence programs, the scan time becomes longer,
Further, it is inevitable that the calculation processing time varies depending on the processing content.

[Object of the Invention] The present invention supplies a pulse signal synchronized with the signal of the reference pulse generation circuit to the external load together with the calculation result of the calculation processing unit, thereby improving the control accuracy of the external load and, for example, a factory site. The purpose is to provide a programmable controller (PC) that is adaptable even in noisy low environment conditions and can be easily used.

SUMMARY OF THE INVENTION The present invention provides a program section for inputting a sequence program, a first memory for storing the sequence program, an arithmetic processing section for performing a logical operation according to the sequence program, and an arithmetic processing section for the arithmetic processing section. A second memory for storing the processing procedure; an input section connected to the arithmetic processing section for receiving a signal from the outside;
An output unit for transmitting the calculation result of the calculation processing unit to an external load to be controlled, a reference pulse generation circuit connected to the calculation processing unit for supplying a timing signal necessary for sequence calculation processing, and the reference pulse generation circuit A frequency dividing circuit for dividing the output signal from the frequency division circuit, and signal selecting means for selecting one of a plurality of frequency dividing signals output from the frequency dividing circuit,
A first interrupt terminal for inputting the timing signal from the frequency dividing path to the arithmetic processing section and the frequency dividing signal are designated by a key operation input of the program section, and the designated signal is given through the arithmetic processing section. It has a latch circuit for holding it and a second interrupt terminal for preferentially inputting the frequency-divided signal held in the latch circuit from the signal selecting means to the arithmetic processing section, and the arithmetic processing section inputs the input signal. By performing interrupt processing corresponding to the generated interrupt signal, the processing with the highest priority is processed, and the divided signal is amplified and output to the external load as a pulse signal synchronized with the divided signal. It is a programmable controller.

[Operation of the invention]

With the above configuration, it is possible to easily select and specify the divided signal by the key operation input of the program section regardless of the specific signal specifying means, and the pulse signal divides the signal of the reference pulse generation circuit. Since the cycle is stable and the pulse signal is synchronized with the signal of the reference pulse generation circuit, it is possible to match the timing with the calculation result supplied from the calculation processing unit and to perform the cooperative operation. It is easy and the frequency-divided signal is amplified so that it is less susceptible to noise.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In the figure, 1 is an input signal source by an external contact or the like, 2 is an input unit for receiving the signal of the contact or the like, 3 is an arithmetic processing unit (CPU) for performing a logical operation according to a sequence program, and the sequence program is a user RAM 4 The system ROM 5 stores the processing procedure. 6 is an output section for transmitting the calculation result of the calculation processing section 3 to an external load, 7 is a program section for inputting a sequence program, 8,
Reference numeral 9 denotes an input terminal group and an output terminal group for connecting the PC and an external device.

Reference numeral 10 is a reference pulse generation circuit composed of a crystal oscillator or the like, which generates a high-frequency (for example, 1 MHz) reference pulse (clock) with high temporal accuracy, which is a reference unit of the processing time in the arithmetic processing unit 3, and its output signal is It is input to the clock input terminal (CP) of the arithmetic processing unit 3. In addition, the reference pulse generation circuit 10
The output signal of is divided into, for example, 100 to 10 Hz by the frequency dividing circuit 11, and is input to the interrupt input terminal (INT ₁ ) of the arithmetic processing unit 3 as a timing signal for timer arithmetic and watchdog timer. There is.

The above 2 to 11 are general components of the PC, and in the present embodiment, in order to further realize the selection output function of the high frequency pulse to the external load, the selection circuit 12 as the signal selection means, the pulse selection input terminal 13 and , A dedicated output section 15 as an output means,
A pulse output terminal 16 is provided.

Since a counter IC or the like is generally used for the frequency dividing circuit 11 for frequency-dividing the output signal of the reference pulse generating circuit 10, the frequency dividing circuit 11 outputs a plurality of frequency dividing signals including high-frequency pulses of around 1 kHz. Is obtained.

The selection circuit 12 is for selecting one of the plurality of frequency-divided signals, is composed of an electronic circuit such as a multiplexer, and is divided by a signal from an external contact 14 connected to the pulse selection input terminal 13. It is possible to specify the selection of the frequency signal.

The output unit 15 is a pulse output terminal for the selected divided signal
16 is provided for the purpose of transmission to the output unit 6, and is provided with a configuration similar to that of the output unit 6, that is, at least an insulating element such as a transformer or a photocoupler that electrically insulates the arithmetic processing unit from the external circuit and a power element that drives an external load. It has been configured. There are various types of power elements used in the output unit 6, such as electromagnetic relays, semiconductor relays (SSRs), and switching transistors, but 5-20ms for electromagnetic relays and about 11ms for SSRs.
Since there is an output delay and the output of the high frequency pulse cannot be dealt with, it is preferable to use a switching transistor having a small output delay and suitable for the output of the high frequency pulse as the power element of the output unit 15.

In this embodiment, when a power switch (not shown) is turned on, a reference pulse is generated from the reference pulse generating circuit 10, and the respective parts 2 to 9 perform the original functions of the PC in synchronization with the reference pulse. Further, the frequency dividing circuit 11 is the reference pulse generating circuit 10 described above.
Output signal is divided into several times and output to the INT ₁ terminal of the arithmetic processing unit 3 as a timing signal of a predetermined cycle to enable functions such as timer calculation and watchdog timer.

Here, since the frequency dividing circuit 11 outputs a plurality of frequency dividing signals including a high frequency pulse of around 1 kHz, the selecting circuit 12 selects one of the frequency dividing signals specified by the external contact 14. The selected divided signal is transmitted to the output unit 15. The selected divided signal is power-amplified by the output unit 15, and then the pulse output terminal
It is transmitted to the external load through 16. In this embodiment, the divided signal thus selected by the selection circuit 12 is output to the dedicated output section.
Since it is output to the outside through the output terminal 16 and the output terminal 16, the high-frequency pulse with a stable cycle has no relation to the scan time in the arithmetic processing unit 3 and does not affect the original arithmetic processing function of the PC. Output is obtained.

In the above embodiment, the frequency division signal can be selected and designated by the signal from the external contact 14. However, when the selection and designation by the external signal is not necessary, the selection circuit 12 is provided in the PC as shown in FIG. Designating means such as a DIP switch 17 for giving a pulse selection input may be provided so that the divided signal can be selected and designated as required. In this case, the pulse selection input terminal 13 in FIG. 1 becomes unnecessary.

When it is desired to avoid the inconvenience of the DIP switch 17 in that the selection and designation form is a binary number, a rotary switch 18 as shown in FIG. Although not shown, one of the plurality of output terminals of the frequency dividing circuit 11 may be switchably connected to the output section 15 by wiring. As still another example of the signal selecting means, as shown in FIG. 4, a plurality of frequency-divided signals output from the frequency dividing circuit 11 are transmitted to a plurality of pulse output terminals 16a via the output section 15a, respectively. Pulse output terminal 1
One of 6a may be selected so that an external load can be connected, and in this way, the selected divided signal can be output to a plurality of external loads at the same time.

FIG. 5 shows a second embodiment of the present invention. In this embodiment, the operation keys of the program section are used to select and specify the above-mentioned frequency division signal, and each section of 1 to 12 and 15, 16 is the same as the first embodiment, but in this embodiment, When the frequency-divided signal is selected and designated by the operation key of the program unit 7, the designated content is output to the latch circuit 19 via the arithmetic processing unit 3 according to the processing procedure stored in the system ROM 5. Then, according to the designated contents held in the latch circuit 19, the selection circuit 12
Selects one of a plurality of frequency-divided signals output from the frequency dividing circuit 11, transmits it to the output unit 15, and causes the pulse output terminal 16 to output the signal.

According to this embodiment, since the frequency division signal can be selected and designated by operating the keys of the program section 7, the dip switch is used.
There is no need for another specifying means such as 17.

FIG. 6 shows a third embodiment of the present invention having different output means.

This embodiment is intended for the case where the output portion 6 of the PC is constituted by a switching transistor suitable for outputting a high frequency pulse as a power element, and each portion 1 to 12 and 19 is the embodiment of FIG. Same as the above, but the output of the selection circuit 12 is input to the second interrupt input terminal INT ₂ of the arithmetic processing unit 3, and a pulse signal synchronized with the divided signal selected via the arithmetic processing unit 3 is output. It is configured to let.

Generally, the arithmetic processing unit 3 often has a plurality of interrupt input terminals like the INT ₁ terminal and the INT ₂ terminal described above, and interrupts one of these interrupt input terminals during normal arithmetic processing. When a signal is input, the arithmetic processing is temporarily interrupted, another specific arithmetic processing (interrupt processing) according to the interrupt signal is performed, and when this is completed, the interrupted arithmetic processing is continued. In addition, the priority order of interrupt processing is set for multiple interrupt input terminals. If interrupt signals are received at the same time, the processing with the highest priority is processed, and the processing with the lowest priority is processed. When an interrupt signal with a high priority is input, the above process is temporarily interrupted, the process with a high priority is performed, and when it ends, the process returns to the interrupted process and continues the process. .

This embodiment utilizes the above-mentioned function, puts the output signal of the selection circuit 12 into the interrupt input terminal (INT ₂ ) having the highest priority, and performs the interrupt processing at the rising edge (or falling edge) of the output signal. The calculation result is output from the calculation processing unit 3 to the output unit 6, and is transmitted to any one of the output terminal groups 9 as a pulse output.

This operation will be described with reference to FIGS. 8 and 9.

FIG. 8 is a flowchart showing how the arithmetic processing unit 3 performs a logical operation based on the sequence program stored in the user RAM 4.

First, in the flow chart of the main program shown in FIG. 7A, when the sequence operation process is started by a predetermined operation, the program counter not shown in FIG. 6 is reset and the contents of the user RAM 4 are read out. Logical operation based on
3). In the next step 104, the above calculation result is the latch circuit.
It is determined whether or not the content is to be output to 19, and if the content is to be output, the content is output to the latch circuit 19 (step 105). That is, this content specifies the frequency-divided signal output from the frequency dividing circuit 11, and is given from the latch circuit 19 to the selection circuit 12. If this is the content for designating the frequency-divided signal of (b) in FIG. 6, the output signal (e) of the selection circuit 12 becomes the same signal as (b), and the timing chart shows it as shown in FIG.

In FIG. 9, (a) to (d) show the waveform of the divided signal, (e) shows the output signal waveform of the selection circuit 12, and (f) shows the timing of outputting the designated contents to the latch circuit 19.

When the operation result is not the content to be output to the latch circuit, that is, if it is a general logic operation output, it is output to the output unit 6 (step 106), the program counter is incremented (step 107), and one scan is completed. It is determined whether or not (step 108), and if NO, step 102
Then, the contents of the user RAM 4 are continuously read out and the arithmetic processing is performed one after another. If one scan is completed, the process returns to step 101 to reset the program counter, and then the contents of the user RAM 4 and the arithmetic processing are repeated.

Since the output signal e of the selection circuit 12 enters the INT ₂ terminal of the arithmetic processing unit 3 during the operation of the above-mentioned flowchart (a), the operation of the flowchart (a) is temporarily interrupted by the rise of the above-mentioned output signal e, and the interrupt Processing is performed. Fig. 8 (b)
In the flowchart of the interrupt processing, first, the contents of the pulse register built in the arithmetic processing unit 3 (logical value “1” or “0”) is read out, and the prespecified port of the output unit 6 (output terminal group 9 Of the pulse register is inverted (steps 109 to 1).
11).

This reversing process means reversing the contents output to the output unit 6 at the next interrupt.

When the interrupt process is completed as described above, the process returns to where the flowchart (a) was interrupted and the process is continued.

These timings are shown by the interrupt processing and the waveform of FIG. That is, a and b in FIG.
The processing time of the flowchart (a) and the flowchart (b) of the figure is shown, and g shows the pulse waveform output to the output terminal group 9. This output pulse waveform G is synchronized with the selected divided signal waveform E, and corresponds to the divided signal further divided by 1/2.

In this embodiment, since the pulse output is performed by the interrupt process having the highest priority, the output pulse having a stable cycle can be obtained without being affected by the variation in the scan time.

By the way, when the above-mentioned interrupt processing is performed, the processing time is added by that amount, and the scan time is delayed, but since the content of the interrupt processing is extremely simple, even a general-purpose microcomputer takes 10 to 20 μs. Processing is completed, and the delay is not a particular problem. For example, when the normal scan time is 10ms, the pulse frequency you want to output is 1k.
If it is set to Hz, interrupt processing (10 to 20 μs) should be performed every 0.5 ms, and the delay due to this is 10 ms / 0.5 ms × (10 to 20 μs) = 200 to 400 μs.
This value is negligible compared to the scan time (10ms).

According to the present embodiment, it is not necessary to provide the dedicated output section 15 and the output terminal 16 for pulse output as in the embodiments of FIGS. If necessary, the latch circuit 19 (or the selection circuit 12) can be controlled through the control input terminal 20 by a signal from the external contact 21 as shown in FIG. 7 to prohibit the interrupt.

FIG. 6 shows a method of selecting and designating the divided signal using the latch circuit 19. However, the divided signal is selected by referring to FIGS.
It may be performed by another method as shown in the figure.

FIG. 10 shows a fourth embodiment of the present invention in which the pulse output can be controlled according to the result of the logical operation in the arithmetic processing section.

This embodiment is the same as the first embodiment except for the control line 22, the latch circuit 23, and the AN.
In addition to the D gate 24, the arithmetic processing unit 3 performs a logical operation on the input signal from the input signal source 1 based on the contents of the sequence program stored in the user RAM 4, and the external input signal has a specific logic. Only in the state, the calculation result is output to the control line 22 assigned to a part of the output section 6, and the latch circuit 23 is made operable. Next, since the output of the latch circuit 23 is turned on by the rise of the output signal of the selection circuit 12, the AND gate 24 is opened in response to this output, and the output signal of the selection circuit 12 is output via the AND gate 24. Reported to Part 15. These timings are the 11th
Shown in the figure.

That is, according to the present embodiment, the output pulse can be output to the peripheral force terminal 16 substantially in synchronization with the logical state of various input signals from the input signal source 1. As shown in FIG. 12, when controlling one controlled device 25 by a plurality of PCs (PC1 to PC3), the pulse output from one of the PCs (PC1) to the controlled device 25 is controlled. This is useful when the output of another PC (PC2, PC3) is to be performed only when it is in a specific logic state.

[Advantages of the Invention] The present invention uses a reference pulse generating circuit and a frequency dividing circuit built in a PC as a supply source of a timing signal necessary for sequence operation processing, and in particular, does not require a specific designating means, The frequency division signal can be selected and specified simply by inputting the key operation in the program section, and the operation is easy, and it is suitable for time measurement in precision positioning control, etc., regardless of the calculation processing speed (scan time) of the PC itself. A high-frequency pulse output with a stable cycle can be obtained, and it is possible to improve the control accuracy of the external load.Moreover, a pulse with a cycle suitable for the application can be selected from the multiple frequency-divided signals of the frequency divider circuit. You can select and output it,
It has resistance to noise and can be added to PC as a stable supply source of high frequency pulse that can be easily used even in a low environment factory.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
4 to 4 are block diagrams showing a partially modified example of the first embodiment, FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG. 6 is a third embodiment of the present invention. Block diagram showing an example,
FIG. 7 is a block diagram showing a partially modified example of the third embodiment, FIGS. 8 (a) and 8 (b) are operation flowcharts of the third embodiment, and FIG. 9 is a flowchart of the third embodiment. Timing chart, FIG. 10 is a block diagram showing a fourth embodiment of the present invention,
FIG. 11 is a timing chart of the fourth embodiment, and FIG. 12 is a block diagram showing an application example of the fourth embodiment. 10: reference pulse generation circuit, 11: frequency divider circuit, 12, 13, 14, 16a, 17, 18, 19: signal selection means, 15, 15a, 16, 109, 110, 111: output means

Claims (1)

[Claims] 1. A program section for inputting a sequence program, a first memory for storing the sequence program, an arithmetic processing section for performing a logical operation according to the sequence program, and a processing procedure of the arithmetic processing section. A second memory, an input unit connected to the arithmetic processing unit for receiving a signal from the outside, an output unit for transmitting the arithmetic result of the arithmetic processing unit to an external load to be controlled, and an arithmetic unit for the arithmetic processing unit. A reference pulse generation circuit that is connected and supplies a timing signal required for sequence calculation processing, a frequency division circuit that divides the output signal from this reference pulse generation circuit, and a plurality of frequency division circuits that are output from this frequency division circuit. Signal selecting means for selecting one of the signals, and a first interrupt terminal for inputting the timing signal from the frequency dividing circuit to the arithmetic processing section , A latch circuit that specifies the divided signal by a key operation input of the program unit and holds the specified signal via the arithmetic processing unit, and a divided signal held in the latch circuit from the signal selection means. A second interrupt terminal that is preferentially input to the arithmetic processing unit, and the arithmetic processing unit performs the interrupt processing corresponding to the input interrupt signal, and processes from the highest priority. A programmable controller which amplifies the frequency-divided signal and outputs it as a pulse signal synchronized with the frequency-divided signal to an external load.