JPH0599989A - Test circuit for ram with gate array - Google Patents

Abstract

PURPOSE:To test a plurality of RAM macros simultaneously when the function of a RAM part of a RAM with a gate array is to be tested. CONSTITUTION:Output signals of RAM macros 21, 22,..., 2N are input to the corresponding comparison circuits 31, 32,..., 3N, and compared with the comparison data input from a comparison data input terminal 13. Each detecting result as to the agreement/disagreement is input to a selecting circuit 41. In the selecting circuit, in accordance with the content of the select signal input from a select signal input terminal 14, outputs of a plurality of comparison circuits are selected or subjected to a logical operation to obtain OR. Tone result is output from an output terminal 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for RAM with gate array.

[0002]

2. Description of the Related Art Conventionally, a RAM with a gate array of this kind has a plurality of memory cells (RAM macros) and gate arrays in which memory cells for storing 1-bit information are arranged vertically and horizontally in a matrix. And have.
In addition, the RAM can be evaluated directly from the external terminal to evaluate the RAM characteristics.
The built-in RAM test circuit enables the above test. Conventionally, a test circuit for a RAM with a gate array of this type has a large bit width of a RAM macro or a large number of RAM macros. Therefore, a large number of output terminals are required to directly output each RAM output to an output terminal. In order to reduce the number of normal output terminals, a circuit for selecting RAM output is built in.

[0003]

In the conventional RAM with a gate array described above, since a select circuit output is connected to an external terminal through a circuit for selecting a plurality of RAM outputs, a plurality of RAM bits are tested at the same time. Therefore, there is a drawback that the same test must be performed multiple times by changing the selection condition.

[0004]

A test circuit for RAM with a gate array according to the present invention has a plurality of memory cell arrays each of which has memory cells for storing 1-bit information arranged vertically and horizontally in a matrix. (Hereinafter referred to as RAM macro) and a gate array RAM having a gate array, a comparison circuit for inputting comparison data from an external terminal at the time of testing the RAM and independently comparing the output with the RAM macro is provided. Has been.

Further, in the RAM test circuit with a gate array according to the present invention, in the comparison circuit, a latch circuit which operates by a clock signal is provided in a portion for inputting the output signal of the RAM macro.

Further, the test circuit for RAM with gate array of the present invention is provided with a selection circuit for outputting an arbitrary output to the output terminal by the selection signal from the output of the comparison circuit.

[0007]

The RAM test circuit with a gate array according to the present invention inputs the comparison data from the outside, simultaneously outputs all the RAM macro outputs, takes the logical sum of the respective results, and outputs the results. All RAM at the same time
Macro testing can be done.

[0008]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The address signal input from the address input terminal 11 is input to the address signal input portions AD of the RAM macros 21, 22, ..., 2N, respectively. The write data signals input from the write data input terminal 12 are input to the write data signal input sections WD of the RAM macros 21, 22, ..., 2N, respectively. RAM macros 21, 22, ..., 2
The output signals of N are comparison circuits 31, 32 for comparing data,
... 3N are input respectively. The clock signal input from the clock signal input terminal 15 is compared with the comparison circuits 31, 3
2, ..., 3N are input to the respective clock input sections.
The comparison data input from the comparison data input terminal 13 is input to the comparison circuits 31, 32, ..., 3N, respectively. The outputs of the comparison circuits 31, 32, ..., 3N are input to the selection circuit 41, and the signals of the comparison circuits 31, 32, ..., 3N are selected by the select signal input from the select signal input terminal 14, and the results are displayed. Output to the output terminal 16.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. The write data signal input from the write data input terminal 12 is stored at the address designated by the address signal input from the address input terminal 11, and the stored data is stored in the RAM.
2N are respectively output from the macros 21, 22, ..., 2N and are input to the comparison circuits 31, 32 ,. Each comparison circuit includes a latch circuit, and latches the output from the RAM macro with the clock signal input from the clock signal input terminal 15. Each of the comparison circuits 31, 32, ..., 3N compares the latched data with the comparison data input from the comparison data input terminal 13, determines whether they match or not, and outputs the result. The result is input to the selection circuit 41,
The select signal input from the select signal input terminal 14 is used to select an arbitrary signal output from the comparison circuit or to OR the outputs of the comparison circuit. The result is output to the output terminal 16 and the test result is monitored.

When the select mode of the selecting circuit 41 is set to the mode for taking the logical sum, if any one of the RAM macro outputs has an error, the error becomes the output of the selecting circuit 41. On the other hand, when the mode for selecting an arbitrary RAM macro is set, the result of the arbitrary RAM macro becomes the output of the selection circuit 41.

[0012]

As described above, according to the present invention, it is possible to input comparison data from the outside and compare all RAM macro outputs at the same time, take the logical sum of the respective comparison results, and output the results. There is an effect that the pass / fail of all the RAM macros can be determined. Further, there is also an effect that the pass / fail judgment of an arbitrary RAM macro can be made by selecting the comparison circuit corresponding to an arbitrary RAM macro output by the selection circuit. Further, by latching the RAM macro output with the input of the comparison circuit, comparison can be performed at any timing, and there is an effect that the access time of the RAM can be measured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 11 address input terminal 12 write data input terminal 13 comparison data input terminal 14 select signal input terminal 15 clock signal input terminal 16 output terminal

Claims (3)

[Claims] 1. A memory cell for storing 1-bit information is arranged vertically and horizontally in a matrix and has a plurality of independent memory cell arrays (hereinafter referred to as a RAM macro) and a gate array. R with gate array
In the AM, a test circuit for RAM with a gate array, comprising a comparison circuit for inputting comparison data from an external terminal at the time of testing the RAM and comparing each with the output of the RAM macro independently. 2. The latch circuit, which operates with a clock signal, is provided in a portion of the comparison circuit for inputting an output signal of the RAM macro.
A test circuit for a RAM with a gate array as described. 3. The test circuit for a RAM with a gate array according to claim 1, further comprising a selection circuit that outputs an arbitrary output from the comparison circuit to an output terminal according to a selection signal.