JPH059987B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is applicable to CCD (Charge Completed Device) and
The present invention relates to a video signal readout device for a solid-state imaging device using a CPD (Charge Priming Device).

[Prior art]

FIG. 1 is a diagram showing the principle of a conventional CCD type solid-state imaging device. A photosensitive section 9 consisting of photodiodes 2 arranged in a matrix, and a vertical CCD 11 for reading out optical signals accumulated in the photodiodes.
~1N and horizontal CCD 3, and an output AMP 4 that amplifies and outputs the transferred signal.

FIG. 2 is a circuit example of the output AMP 4 in FIG. 1. 30 is a small capacitance that converts the signal charge Q _S transferred by the horizontal CCD 3 into voltage.
C ₀ , 31 is a source-follower MOS type FET 3 that outputs the signal voltage V ₀ =Q _S /C ₀ generated between the capacitance C ₀ in proportion to the signal charge Q _S with low impedance.
2 is a reset MOS type FET for removing the signal charge amount Q _S in the capacitor C ₀ to the outside.

In the device having the structure shown in FIGS. 1 and 2, signals are read out in the following manner. That is, first, the signal charges accumulated in the photodiode 2 during one frame period are transferred to the vertical CCDs 11 to 1 during the vertical retrace period.
Move inside N. The vertical CCD transfers one line per horizontal retrace period, and the signal charge is transferred horizontally.
Transfer to CCD3 sequentially. The horizontal retrace period is the horizontal retrace period.
The signal charge transferred to the CCD is sequentially transferred into the capacitor C ₀ by applying a horizontal scanning clock pulse to the CCD in the horizontal direction during one subsequent horizontal period. The signal charge Q ^(l) _S transferred to the capacitor C ₀ by the lth clock pulse generates a voltage V ^(l) ₀ between the capacitor C ₀ and a hold pulse of voltage V ^(l) ₀ is generated from the source follower output terminal 33. (Figure 3 pulse 4l) is output. Thereafter, the signal charge Q ^(l) _S is removed to the outside through the reset MOS type FET 32. Also, at the next l+1st clock pulse, the next signal charge Q ^(l) _S is transferred to the capacitor C ₀ again,
Hold pulse of voltage V ^(l) ₀ (Fig. 3 pulse 4 (l+
1) Output. By repeating the same operation, the signal is sequentially output as a train of hold pulses (FIG. 3c) with a voltage V ^(l) ₀ proportional to the signal charge Q ^(l) _S. The signal component is obtained by extracting the modulated signal component of the output signal of FIG. 3c using an LPF.

By the way, in the output AMP circuit shown in FIG. 2, the reset MOS type FET 32 for removing the signal charge amount Q _S held in the capacitor 32 to the outside is not an ideal switch element but has an ON resistance. Therefore, the reset MOS type FET32 is turned on.
In this state, a noise voltage is generated between the capacitor _C0 due to the thermal noise of this ON resistance, but the reset MOS
When the type FET 32 is in the OFF state, the instantaneous value of the noise voltage generated during that time capacitance C ₀ is held and mixed into the output signal.

Including this held noise signal, Figure 3c
A rewritten version of the output signal is shown in FIG. 4c.
In the figure, 61 is the ON state of the reset MOS FET.
The noise voltage portion 62 generated across the capacitor C ₀ due to resistance thermal noise indicates a noise waveform generated by the noise voltage being held at the moment the switch is turned off. As is clear from the figure, the noise voltage of 61 occurs with equal probability of positive and negative voltages, and its average value is small, whereas the held noise of 62 (hereinafter referred to as reset noise) is
Since the instantaneous value of the noise voltage 61 itself is held, a very large noise signal is generated.

Conventionally, this reset noise has been removed using a clamp circuit. FIG. 5 shows an example of the circuit configuration, and FIG. 6 is an explanatory diagram of the principle of reset noise removal by this circuit. That is, the output signal wave of the solid-state imaging device 7 in FIG.
1 and clamps at position 63 where only reset noise is included. The reset noise portion of the output signal wave immediately after being clamped is removed by the clamp, as shown in FIG. 6c, leaving only the signal portion.
Therefore, by further extracting the modulated signal component using the LPF 52, a signal component free of reset noise can be obtained.

On the other hand, in the output AMP circuit shown in Figure 2, the MOS type for the switch, which causes the reset noise mentioned above, is
Not only FET32 but also MOS for source and follower
Type FET 31 also generates white random noise due to a thermal noise source. Therefore, the actual solid-state imaging device output signal waveform is the waveform shown in FIG. 4c further superimposed with white random noise.

Therefore, the signal readout circuit using the clamp circuit 51 shown in FIG.
The reset noise generated as a result of holding the noise voltage generated between the capacitance C ₀ can be almost completely removed by holding the noise voltage generated between the capacitance C 0 , but on the other hand, the thermal noise voltage of the source-follower MOS type FET 31 is held and the noise is reduced. As a result, the level is increased (Fig. 6 d), and the improvement rate of the SN ratio of the extracted signal remains low.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal readout circuit and a method for driving a solid-state imaging device that eliminates the reset noise without increasing the noise caused by the source follower MOS FET, while eliminating the above-mentioned drawbacks. .

[Summary of the invention]

In order to achieve the above object, the present invention divides the output of a solid-state imaging device into two, and delays the output signal of one of the two for a certain period (within 1/2 of the horizontal scanning reset pulse period T) from the output signal of the other. After subtracting
It was configured to sample the signal part. Furthermore, the solid-state imaging device is characterized in that it is configured to be driven so that the time period T-τ _r -τ including only the reset noise is equal to the time period τ including the signal.

[Embodiment of the Invention] FIG. 7 is an embodiment of a signal readout circuit according to the present invention, and FIG. 8 is an explanatory diagram of a signal readout method using the circuit of FIG.

In FIG. 7, 57 is a drive circuit for driving the solid-state imaging device 7, which controls the clock frequency of clock pulses φ _H1 and φ _H2 in horizontal scanning and the reset pulse φ _R
Set the frequency to 7.16MHz. Therefore, the period T of the reset pulse φ _R is approximately 140 nsec. In addition, the width τ _r of the reset pulse φ _R (Fig. 4b) is the capacitance shown in Fig. 2
Set the time to about 20 nsec, which is sufficient to remove the signal charge accumulated in _C0 . On the other hand, signal transfer pulse φ _H2
The rising position of is set approximately 60 ns later than the falling position of reset pulse φ _R , and is set so that the period T-τ _r -τ containing only the reset noise is approximately equal to the period τ containing the signal.

The solid-state imaging device output signal waveform V ₀ obtained by the above driving method is shown in FIG. 8a. Output signal V ₀ in Fig. 8a
is first divided into two parts, one of which is shifted by a time of approximately 60 nsec (Δ~τ) by a delay circuit 54 (FIG. 8 bV ₀ '), and then subtracted from the other output signal V ₀ which is not delayed by a subtracter 55 ( Figure 8cV ₁ ). By the way, the reset noise is removed from the waveform _V1 resulting from this subtraction, as is clear from Fig. 8c.
There is a region 64 containing only the signal portion and the noise of the source follower MOS FET. FIG. 7 56 is a sampling circuit for sampling this portion with the sampling pulse φ _S (FIG. 8 d).
The waveform _eV2 in FIG. 8 after sampling no longer contains reset noise. Furthermore, the noise level of the source-follower MOS FET is low because there is no operation to hold the instantaneous value of the noise voltage. Therefore, the modulated signal component of waveform _V2 in FIG. 8e is extracted by the LPF 52, and the signal processing circuit
By inserting necessary synchronization signals such as SYNC into the television signal according to 3, it is possible to obtain a television signal with a high SN ratio.

In addition, in the above signal readout method, the eighth
It is sufficient that the region 64 in figure c exists, and arbitrary τ _r , τ
On the other hand, the delay time Δ is within the range of 0<ΔT−τ _r ...(1), and the sampling pulse width τ _S is within the range of 0<τ _S MIN (τ, 4, T−τ _r −Δ, T−τ _r − τ)
...It can be set arbitrarily within the range of (2). However, in order to widen the area 64 and obtain a high SN signal,
The pulse width τ, τ _S and delay time Δ are respectively It is desirable to set it to . The above embodiment is set according to the condition of equation (3).

The present invention has been explained above using the example of the output AMP circuit shown in FIG. 2. However, the output AMP circuit such as the output AMP circuit shown in _FIG . It can also be used to read signals from a CCD type solid-state imaging device having a circuit, a solid-state imaging device of a type combining MOS type and CCD type as shown in FIG. 10, a CCD type line sensor, a CCD type delay line, etc.

In Figure 10, T _x2 is a transfer gate for reading signal charges or pseudo signal charges from vertical lines, T _x1 is a transfer gate for reading signal charges or pseudo signal charges, T Switch MOS gate for sorting and taking out, φ _t , φ _X , φ _R ,
V _R represents a pulse applied to the terminals T _X2 , T _X1 , BLC, and BLD, respectively, and φ _V represents a pulse applied to the vertical switch MOS gate.

〔Effect of the invention〕

As explained above, according to the present invention, the output AMP of the type that amplifies the power or voltage of the signal voltage appearing between the input end capacitance _C0 of the CCD type equal output AMP
In a solid-state imaging device having the following, it is possible to hold the noise voltage of the output AMP source/follower MOS FET, remove reset noise without amplifying the noise level, and obtain a television signal with a high signal-to-noise ratio.

[Brief explanation of drawings]

Figure 1 is a principle diagram of a CCD solid-state imaging device, Figure 2
The figure shows an example of the output AMP circuit, Figure 3 is an explanatory diagram of its output waveform, Figure 4 is an explanatory diagram of reset noise, and Figure 5 is an illustration of the output waveform.
6 are a conventional signal readout circuit for removing reset noise and its explanatory diagram, FIGS. 7 and 8 are a signal readout circuit for removing reset noise according to the present invention and its explanatory diagram, and FIG. 9 is an explanatory diagram thereof. is an example of an output AMP circuit other than Figure 2, and Figure 10 is an example of an output AMP circuit other than Figure 2, and Figure 10 is an example to which the present invention can be applied.
FIG. 2 is a principle diagram of a solid-state imaging device other than a CCD type.

Claims (1)

[Claims] 1. An output circuit that sequentially accumulates continuous pulse-shaped signal charges within the electrostatic charge amount at the input terminal of the amplifier circuit in accordance with signal transfer pulses of a predetermined period, and amplifies and outputs the signal voltage appearing between the electrostatic charge amounts. The device generates the signal transfer pulse, a reset pulse having the same period as the signal transfer pulse and a predetermined pulse width, and a signal read pulse from the rising edge of the signal transferring pulse to the rising edge of the reset pulse. After dividing the output signals from the drive circuit and the output circuit into two, and delaying the output signal of one of them from the other output signal by the period from the fall of the reset pulse to the rise of the signal transfer pulse. , a subtracter for subtracting from the other signal, a circuit for outputting the output of the subtracter in response to the signal readout pulse, and a low-pass filter for extracting a modulation signal component of the output signal of the circuit. A signal readout device for a solid-state imaging device, characterized in that: