JPH0594532A - Method for correcting image data - Google Patents

Abstract

PURPOSE:To attain high speed image processing by quickly obtaining a correction variable for image data. CONSTITUTION:This image data correcting system is provided with four delay lines 1A to 1D for delaying image data only by a prescribed time so as to remove an input timing difference in plural image data time-sequentially inputted at the time of adding the image data of all picture elements in a window, arithmetic circuits 2 to 9 for applying arithmetic processing to image data outputted from respective delay lines 1A to 1D and a delay line control part 10 for inputting read signals and write signals to the four delay lines 1A to 1D at the prescribed timing to control the I/O of image data to/from the delay lines 1A to 1D and inputting a latch signal to latches 7, 8 to control the latch of image data in the latches 7, 8. When the image data of the final picture element are inputted to the window, four delay lines 1A to 1D based upon, prescribed arithmetic formulas to obtain a correction variable S.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data correction method for performing correction such as sharpening and smoothing on digital image data such as a radiation image obtained by image reading.

[0002]

2. Description of the Related Art An image signal is obtained by reading a recorded radiation image, and after subjecting this image signal to appropriate image processing,
Image reproduction and recording are performed in various fields.
For example, an X-ray image is recorded using an X-ray film having a low gamma value designed to be suitable for subsequent image processing,
The X-ray image is read from the film on which the X-ray image is recorded and converted into an electric signal, and this electric signal (image data)
A system has been developed that can obtain a reproduced image with good image quality such as contrast, sharpness, and graininess by reproducing it as a visible image on a copy photograph after performing image processing on the image (Japanese Patent Publication 61). -5193).

In addition, the applicant of the present invention has proposed radiation (X-ray, α
Rays, β rays, γ rays, electron rays, ultraviolet rays, etc.), a part of this radiation energy is accumulated, and when excitation light such as visible light is then irradiated, the stimulated emission light of a light amount corresponding to the accumulated energy is emitted. Stimulable phosphors that emit light (stimulable phosphors)
Using, the radiographic image of a subject such as a human body is once photographed and recorded on a sheet-shaped stimulable phosphor, and the stimulable phosphor sheet is scanned with excitation light such as laser light to generate stimulated emission light,
A radiation recording / reproducing system that photoelectrically reads the obtained stimulated emission light to obtain an image signal, and outputs a radiation image of a subject as a visible image on a recording material such as a photographic light-sensitive material or a CRT based on the image signal. Have already been proposed (Japanese Patent Laid-Open Nos. 55-12429, 56-11395, 55-0163472,
56-164645, 55-116340, etc.).

This system has the practical advantage of being able to record images over a very wide radiation exposure area compared to conventional radiographic systems using silver salt photography. That is, it has been confirmed that the amount of stimulated emission light emitted by excitation after storage is proportional to the radiation exposure amount over a very wide range, and therefore the radiation exposure amount varies considerably depending on various imaging conditions. Even if the stimulated emission light emitted from the stimulable phosphor sheet is read, the gain is set to an appropriate value, it is read by photoelectric conversion means and converted into an electric signal (image data), and this image data number is used. By outputting a radiation image as a visible image on a display device such as a photographic light-sensitive material or a CRT, it is possible to obtain a radiation image that is not affected by fluctuations in radiation exposure.

By the way, in the above system, in order to improve the image quality of the radiation image as the final output, the read image data is usually subjected to correction processing such as sharpening and smoothing.

Conventionally, as a sharpening correction process, a predetermined pixel matrix area of n rows and n columns centering on a pixel to be corrected with respect to two-dimensionally arranged image data (hereinafter,
Set) of "Wind", the correction amount S with respect to the image data a _mm of the center pixel position within this window, for _{^{example, S = n 2 a mm -}} (a 11 + a 12 ... + a 1n + a 21 + ... + a _nn ) (1) However, it is known that m = (n + 1) / 2 a _mm : image information of the central pixel a _{11 to} a _nn : pixel information of each pixel in the window.

In the calculation, n × n in the window
After temporarily storing all the image information a _{11 to} a _nn of the pixels in the line memory in the line memory device, these image information are sequentially read out, and first, (a ₁₁ + a ₁₂ + ...
a _1n + a ₂₁ + ... + a _nn ) is calculated, and then the correction amount S is obtained by computer processing based on the equation (1), and the image data of the central pixel of the original image is corrected by this correction amount S. (JP-A-60-263576, JP-A-60-263579
issue).

[0008]

However, since the two-dimensionally arranged image data is supposed to be temporarily stored in the memory, the address of the memory is added when the addition of a _{11 to} a _{nn is performed.} It is necessary to sequentially specify each of the image information output according to the specification, and therefore it takes a long time to obtain the correction amount S for the image data a _mm of the pixel at the center position in the window. Therefore, high-speed image processing could not be achieved.

The present invention has been made in view of the above circumstances.
The amount of correction for image data can be obtained in a short time,
An object is to provide an image data correction method capable of achieving high-speed image processing.

[0010]

A first image data correction method of the present invention is to input image data obtained by scanning an original image in time series into a plurality of delay means, and to delay each of these delay means. It is characterized in that the image data value is corrected by performing arithmetic processing on the image data output from the.

That is, for the image data obtained in time series by scanning the original image, an n × n pixel matrix (however,
(n is an odd number), and a predetermined calculation process is performed on the image data to obtain a correction amount S for the image data value a _mm of the pixel at the center position of the window, and according to the correction amount S, In the image data correction method for correcting the image data value a _mm , the image data obtained in time series is input to a plurality of image data delay means having a delay amount such that there is no difference in the obtained timing. At the very least, the correction amount S is obtained by performing arithmetic processing on a plurality of image data output from these image data delaying means.

Here, the image data includes both data corresponding to one pixel and data corresponding to an added value of data of a plurality of pixels.

The second image data correction method of the present invention is characterized in that when the latest image data value a _in is obtained _in the first image data correction method, the plurality of image data delay means are provided. Among them, the image data value A of the pixel n rows before in the same column as the pixel having the latest image data value a _in is output from the first delay means, and the latest image data value a is output from the second delay means. n-1 / 2 rows before the pixel having _in and n
The image data value B of the pixel of the -1/2 column before is read from the third delay means _{in the} same column as the pixel having the latest image data value a _in , and of the pixels from the nth row to the 1st row before. The added value C of the image data is output from the fourth delay means to the image data of each pixel from the pixel having the latest image data value a _in to n columns before and (n−1) th row to the same row. The added value D is output respectively, and based on the arithmetic expression n ² B- (T + C−A−D + a _in ) (where B = a _mm , T is the added value of all the image data in the window set last time). Image data value a _mm
It is characterized in that the correction amount S for is obtained.

[0014]

According to the first image data correction method, the correction amount S for the image data value a _{mm is} obtained.
N × centered on the pixel corresponding to this image data value a _mm
When the addition value of each image data in the window of the n pixel matrix is obtained, the image data in the window to be subjected to the addition operation, which is obtained in time series, is simultaneously output to the addition processing unit. These image data are input to a plurality of delay means having a delay amount such that there is no difference in the timing of reading the image data.

That is, since the above-mentioned image data obtained in time series are sent to the image processing section one after another at the obtained timing, it is difficult to add them as they are. Since the image data read from the memory is once stored in the memory and then added successively by the predetermined adder, it takes a long time to read the image data from the memory. However, in the above configuration, the image data is passed through a predetermined delay means, and when the image data is output from this delay means, the image data is in a state in which there is no timing shift between them. No complicated operation such as reading is required, and therefore the image data value can be corrected at a higher speed than in the above-mentioned conventional technique.

In the second image data correction method, the in-window image data obtained in the calculation operation of the correction amount S performed once before the image data value a _mm to be corrected at present. Is used. That is, the window set in the calculation operation of the correction amount S which is currently going to be performed is 1 more in the row direction than the window set in the calculation operation of the correction amount S performed one time before.
It means that there is a pixel shift, and for the overlapping part of both windows, the value obtained in the calculation operation of the correction amount S performed one time before can be used as it is, and only the non-overlapping part can be obtained separately. This separately obtained value is added to or subtracted from the value obtained by the calculation operation of the correction amount S performed once.

The addition value of all the image data set in the window set last time is T, the latest image data value is a _in, and the image data value n rows before _{in the} same column as this latest image data value a _in. A, and n−1 / 2 than the latest image data value a _in
Let B be the image data value before the row and n−1 / 2th column before, the same column as the latest image data value a _in , and let C be the addition value of each image data from the nth previous row to the 1st previous row. If the added value of each image data from the image data value a _in of n columns before and (n-1) th row to the same row is D, the added value of all image data in the window set this time is T + C- A-D + a _in
Required by.

Further, since what is finally obtained is the correction amount S for the image data value a _mm , this correction amount S is calculated by multiplying the image data value a _mm by the number of pixels n ² in the window. It is obtained by subtracting the added value T + C−A−D + a _in of the image data.

After all, the correction amount S is n ² a _mm − (T + C−A−
D + a _in ), but since A, C, D and B (= a _mm ) are obtained at different timings, the values of A, B, C and D are different. By using four delay means for delaying the data from the time when the image data value a _in is acquired to the time when the image data value a _in is acquired, timing adjustment is performed when these values are input to the calculation unit. ..

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of an apparatus for carrying out the image data correction method of the present invention.

This device sets windows of an n × n pixel matrix for image data obtained by scanning an original image, and performs predetermined arithmetic processing on these image data to determine the center position of the window. Image data value of pixel a _mm
For calculating the correction amount S for the image data of all pixels in the window, the image data is input for a predetermined time so that there is no difference in the input timing with respect to the image data input in time series. Four delay lines 1A to 1D for delaying, arithmetic circuits 2 to 9 (including latches 7 and 8) including random logics for performing arithmetic processing on the image data output from each of the delay lines 1A to D, and the above 4
A read signal and a write signal are input to the four delay lines 1A to 1D at predetermined timings to allow the four delay lines 1A to
There is provided a delay line control unit 10 for controlling input / output of image data to / from D to input latch signals to the latches 7 and 8 to control latching of image data in the latches 7 and 8.

That is, in this apparatus, for each pixel of the image data area 11 (corresponding to the image read and scanned) arranged in X pixels in the row direction and Y pixels in the column direction as shown in FIG. The correction amount S is sequentially calculated in the reading order, and the pixel 12 for which the correction amount S is to be calculated is calculated.
A window with n pixels in the row direction and n pixels in the column direction centered at
Set, the additional value P of image data of all the pixels in the window 13, is subtracted from the value n ² a _mm multiplied by n ² to the image data value of the central pixel 12, n ² a is a result _mm- P
Is output as the correction amount S of the central pixel 12. The calculation of the correction amount S is performed in synchronization with the timing when the image data value a _in of the last pixel 15 in the window 13 is obtained.

The image data value of the pixel 16 in the same column as the last pixel 15 in the window 13 and n rows before is A, and the pixel in the same column as this last pixel 15 from n rows before to 1 row before. The added value of the image data of C is C, n columns before this last pixel 15,
When the addition value of the image data of the pixels from the (n−1) th row to the same row is D and the addition value of the image data of all the pixels in the window 14 set last time is T, the addition value P is T
It is obtained by calculating + C−A−D + a _in . Therefore, the correction amount S is n ² a _mm − (T + C−A−D +
a _in ) is calculated.

By the way, since the image data for each pixel in the image data area 11 is sequentially input in time series, each image data is input with a timing shift for each pixel, and is left as it is. Correction amount S described above
Cannot be calculated.

Therefore, in the apparatus according to the present embodiment, the four delay lines 1A to 1D are used to eliminate the timing deviation of the image data for each pixel, and the image data value a _in of the last pixel 15 in the window 13 is input. These delay lines 1A-D
The correction amounts S can be obtained by directly performing the four arithmetic operations on the outputs A to D based on the above-described arithmetic expressions.

The first delay line 1A is a FIF for delaying the image data value A of the pixel n rows before in the same column as the pixel having the finally obtained image data value a _in by n rows of pixels.
O memory. The second delay line 1B sets the image data value B of the pixel n-1 / 2 rows before and n-1 / 2 columns before the pixel having the last obtained image data value a _in to n-1. / FIFO of 2 rows of pixels + n-1 / 2 pixels of delay
It is a memory. In addition, the third delay line 1C is the same column as the pixel having the finally obtained image data value a _in , and the addition value C of the image data of each pixel from n rows before to 1 row before is added for one row of pixels. It is a FIFO memory that can be delayed only by this. Furthermore, the fourth delay line 1D is a sum D of the image data of each pixel from the pixel having the last obtained image data value a _in to n columns before and (n−1) th row to the same row. Is a FIFO memory capable of delaying by n pixels.

The arithmetic circuit 2 has a second delay line 1B.
The output from the B (= a _mm) and the circuit for multiplying the number of pixels n ² in the window, the arithmetic circuit 3 is the output A of the first delay line 1A from the output C from the third delay line 1C The subtracting circuit, the arithmetic circuit 4 outputs the output C- from the arithmetic circuit 3.
This is a circuit that adds A and the image data value a _in of the latest pixel.

Further, the arithmetic circuit 5 is a circuit for adding the addition value T of the image data of all the pixels in the window set last time and the output CA + a _in from the arithmetic circuit 4, and the arithmetic circuit 6 is the above. Output from arithmetic circuit 5 T + CA + a
_This is a circuit for subtracting the output D from the fourth delay line 1D from in.

Further, the latch 7 receives the input T + C
This is a circuit for latching the value of −A + a _in −D until the arithmetic operation of the arithmetic circuit 5 in the next window setting, whereby T + C−A + a _in −D _{in the} current window setting.
The value of can be used as the value of T in the next window setting. The latch 8 is a circuit for latching the value of the output n ² a _mm from the arithmetic circuit 2, whereby the timing of the output from the latch 7 and the output of the value of n ² a _mm are matched.

Further, the arithmetic circuit 9 outputs the output n ² a _mm of the latch 8 to the output T + C-A + a _{in of the} latch 7.
−D is subtracted, and the result is n ² a _mm − (T + C−A
+ A _in −D) value is output as the correction amount S.

The delay line controller 10 comprises an X-direction counter 21, a Y-direction counter 22 and a position detector 23, as shown in FIG.

X direction (row direction) and Y direction (column direction)
X-value signal and Y-value signal indicating the pixel number of
When input to the direction counter 21 and the Y direction counter 22, the X address and the Y address are synchronized with the input of the pixel clock from the X direction counter 21 and the Y direction counter 22.
The address is output to the position detector 23. This position detector
In addition to the X address and Y address, a value n representing the size of the window is also input to 23, and based on these input values, write signals and read signals to the delay lines 1A to D, and further latches 7 and 8 are input. A latch signal for the output signal is output at a predetermined timing.

FIG. 4 shows the image data area 11 when the number of pixels in the X direction is 9, the number of pixels in the Y direction is 9, and the number of pixels n in the X direction and the Y direction in the window 13 is 3. The symbols shown in FIG. 4 indicate the image data value of each pixel at that position, and are a time-series in a predetermined cycle.
_{When the} correction amount S for the image data value a ₄₅ in FIG. 4 is sequentially obtained from ₁₁ , the window 13A of the 3 × 3 pixel matrix centered on the pixel corresponding to this a ₄₅ is set.

At this time, the first delay line 1A has a delay time of three columns (27 pixels), and the second delay line 1B has one column + 1 pixel (10 pixels). The third delay line 1C has a delay time of one column of pixels (9 pixels), and the third delay line 1C has a delay time of 4th.
D is set to have a delay time of 3 pixels.

Therefore, the image data value a _{56 is} stored in this circuit.
Is input, the image data value a ₅₃ is output as the output value A of the first delay line 1A and the output value B of the second delay line 1B is
The image data value a ₄₅ is output as (= a _mm ). Third
Image data values a ₅₃ , a as output values C from the delay line 1C of
The added value of ₅₄ and a _{55 and} the added value of the image data values a ₂₄ , a ₂₅ and a ₂₆ are output as the output value D from the fourth delay line 1D.

The arithmetic circuit 2 multiplies 3 ² by a ₄₅ and outputs the product value 9a ₄₅ . Further, the output value of the third delay line 1C is in the arithmetic circuit _{3 (a 53 + a 54 +} a 55) and the output value a ₅₃ of the first delay line 1A
And the subtraction value (a ₅₃ + a ₅₄ + a ₅₅ ) −
a _53, that is, a ₅₄ + a ₅₅ is output, and in the arithmetic circuit 4, the output value a ₅₄ + a ₅₅ of the arithmetic circuit 3 and the latest image data value a ₅₆ are added, and the added value a ₅₄ + a ₅₅ + a _56.
Is output.

Output value a ₅₄ + a ₅₅ + from the arithmetic circuit 4
a ₅₆ is input to the arithmetic circuit 5, and the addition value T of all the image data of the window 14 set last time (when calculating the correction amount S of the image data value a ₃₅ ) in this arithmetic circuit 5, that is, a ₂₄ + a ₃₄ + A ₄₄ + a ₂₅ + a ₃₅ + a ₄₅ + a ₂₆ + a ₃₆ + a
_It is added with ₄₆ .

In the arithmetic circuit 6, the output value of the arithmetic circuit 5 is a ₂₄ + a ₃₄ + a ₄₄ + a ₂₅ + a ₃₅ + a ₄₅ + a ₂₆ + a ₃₆ +
a ₄₆ + a ₅₄ + a ₅₅ + a ₅₆ and the output value a ₂₄ + a ₂₅ + a ₂₆ from the fourth delay line 1D are subtracted to obtain a ₃₄ + a ₄₄ + a.
₅₄ + a ₃₅ + a ₄₅ + a ₅₅ + a ₃₆ + a ₄₆ + a ₅₆ is output. The output value from the arithmetic circuit 6 is input to the latch 7 and latched.

On the other hand, the output value 9a ₄₅ from the arithmetic circuit 2 is input to the latch 8 and latched.

Since the latching of the data in the latches 7 and 8 is performed in response to the input of the latch signal from the delay line control unit 10, it is performed at the same timing.

[0042] In the arithmetic circuit 9, the subtraction of the output value from the output value of the latch 7 from the latch 8 is made, the subtraction value _{9a 45 - (a 34 + a} 44 + a 54 + a 35 + a 45 + a 55 + a
₃₆ + a ₄₆ + a ₅₆ ) is output as the correction amount S.

The output value from the latch 7 is used as T in the next calculation (when the correction amount S of the image data value a ₅₅ is calculated).

By the way, the delay time in each of the delay lines 1A to 1D described above is the time from the writing of the image data of a predetermined pixel to the reading of the image data. Therefore, these delay times are the delay line control units. It is determined by the difference in the output timing of the write signal and read signal from 10.

FIG. 5 shows the first delay line 1 of the delay line controller 10.
7 is a flowchart showing a write operation and a read operation for A.

According to the flow chart of FIG. 5, for each register corresponding to the write pointers φ to 26 of the first delay line 1A, Y = determined in step S101.
The process of step S1 is performed only for the lines 1, 2, and 3, so that the image data a ₁₁ to
a ₉₃ are sequentially stored. These image data a _{11 to} a ₉₃
Is read from each register by the processing of steps S4 and S104 prior to the write operation of each register of step S2. Next, step S2 only the line of Y = 4, 5, 6 by the determination in step S102 is performed, thereby the image data a ₁₄ ~a ₉₆ are sequentially stored in step S2. These image data a ₁₄
Through a ₉₆ are read from each register by the processes of steps S5 and S105 prior to the write operation of each register of step S3. Next step S3 only the line of Y = 7, 8, 9 the judgment of step S103 is performed, thereby the image data a ₁₇ ~a ₉₉ are sequentially stored in step S3.

[0047] Incidentally, the image data a ₁₇ ~a ₉₉ in this embodiment
Is not used in the operation and is not read from the register.

As described above, this read operation is performed in step S.
Since 6 is set to delay the writing operation by 3 lines (pixels of 3 rows), the reading operation is delayed by 3 lines from the writing operation of the image data. Become. Also, by this, step S
The write operation of 2 and the read operation of step S4 are performed in step S
The writing operation in step 3 and the reading operation in step S5 are performed simultaneously. However, the read operation is performed prior to the write operation for the same register in timing.

FIG. 6 shows the second delay line 1B of the delay line controller 10.
5 is a flowchart showing a write operation and a read operation for the.

According to the flow chart of FIG. 6, for each of the registers corresponding to the write pointers .phi. To 13 of the second delay line 1B, Y = determined in step S121.
For only a few lines, X =
Image data a ₂₂ corresponding to only 2, 3, ..., 8 pixels
a ₈₂ and image data a _{23 to} a ₈₃ are selected, the process of step S11 is performed on them, and the image data a ₂₂
To a ₈₂ and image data a _{23 to} a ₈₃ are sequentially stored.
These image data a _{22 to} a ₈₂ and a _{23 to} a ₈₃ are written in step S125 prior to the write operation of each register in step S12.
, Is read from each register by the processing of steps S25 and S15. Next, in the same manner, the image data a _{24 is} determined by the determinations in step S122 and step S22.
To a ₈₄ and image data a _{25 to} a ₈₅ are selected, the process of step S12 is performed on them and the image data a _{24 is selected.}
To a ₈₄ and image data a _{25 to} a ₈₅ are sequentially stored.
These image data a _{24 to} a ₈₄ and a _{25 to} a ₈₅ are written in step S126 prior to the write operation of each register in step S13.
, Are read from each register by the processing of steps S26 and S16. Next, in the same manner, the image data a _{26 is} determined by the determinations in step S123 and step S23.
To a ₈₆ and image data a _{27 to} a ₈₇ are selected, the process of step S13 is performed on them and the image data a _{26 is selected.}
~a ₈₆ and the image data a ₂₇ ~a ₈₇ are sequentially stored.
These image data a _{26 to} a ₈₆ and a _{27 to} a ₈₇ are written in step S127 prior to the write operation of each register in step S14.
, Are read from each register by the processing of steps S27 and S17. Further, in the same manner, the image data a is determined by the determinations in steps S124 and S24.
_{28 to} a ₈₈ and image data a _{29 to} a ₈₉ are selected, and the process of step S14 is performed on them, and the image data a
_{28 to} a ₈₈ and image data a _{29 to} a ₈₉ are sequentially stored. After that, the image data a _{28 to} a _{88 of the} image data are read out from the respective registers by the processes of steps S128, S28 and S18.

Therefore, the read operation is different from the write operation in that one line (1
Row pixels), and step S21
.. are delayed by one pixel due to the difference between .about.S24 and steps S25 to 28, the image data read operation is eventually delayed by one line and one pixel from the image data write operation. Will be done.

In this embodiment, the image data a _{29 to} a ₈₉
Is not used in the operation and is not read from the register.

FIG. 7 shows a third delay line 1C of the delay line controller 10.
5 is a flowchart showing a write operation and a read operation for the.

According to the flowchart of FIG. 7, in step S31, the added value C of the column-direction three-pixel data is added to each of the registers corresponding to the write pointers φ to 8 of the third delay line 1C in a row cycle. Updated and stored. On the other hand, in step S32, the reading operation of the added value C is performed at the timing delayed from the writing operation of the added value C to the register by the pixels of one line. In addition,
The writing operation of the additional value C is performed after the previous reading operation of the additional value C is completed.

Incidentally, step S131 and step S13
In 4 the timing at which the value of Y is counted up is detected, and in steps S132 and S135 the end is checked. Also, the read operation is started from the second line in step S133. The arithmetic circuit 4 shown in FIG. 1 writes the result of a ₁₁ + a _{12 in} the FIFO memory.

FIG. 8 shows the fourth delay line 1D of the delay line controller 10.
5 is a flowchart showing a write operation and a read operation for the.

According to the flowchart of FIG. 8, in step S41, the added value D of the column-direction three-pixel data is added to each of the registers corresponding to the write pointers φ to 8 of the fourth delay line 1D in a row cycle. Updated and stored. On the other hand, by the operation of step S42, in step S43, the operation of
The read operation of the added value D is performed at a timing delayed by the number of pixels.

Incidentally, steps S141 and S14
In 4 the timing at which the value of Y counts up is detected, and in steps S142 and S145 the end is checked. Further, the read operation is started from the third line in step S143.

FIG. 9 is a flowchart showing the output operation of the latch signal (latch clock) to the latches 7 and 8 of the delay line control unit 10. As shown in this flow chart, the data in the latches 7 and 8 are cleared by the operation of step S51, and new data is latched in the latches 7 and 8 by the latch signal output by the operation of step S52. That is, in step S52, X =
1 calculates a ₁₁ + a ₁₂ + a _13, and when X = 2, a ₁₁ + a ₁₂
+ A ₁₃ + a ₂₁ + a ₂₂ + a ₂₃ is calculated, and when X = 3, a ₁₁ +
Then, a ₁₂ + a ₁₃ + a ₂₁ + a ₂₂ + a ₂₃ + a ₃₁ + a ₃₂ + a ₃₃ is calculated. Actually, T is obtained, and the calculation {n ² a _mm − (T +
C−A + a _in −D)} is possible because Y = 3 and X = 3.
From the time.

Note that latching is started from the third line in step S151, the timing at which the value of Y is counted up is detected in step S152, and step S15
3 detects the end.

It should be noted that it is composed of the above-mentioned FIFO memory 4
Each of the delay lines 1A to 1D needs to be reset to 0 before the operation starts.

As described above, in the above embodiment, the FIs set so as to each have a predetermined delay time.
Since the correction amount S is calculated by the four delay lines 1A to 1D including FO memories and the arithmetic circuits (including latches) 2 to 9 including random logic, the correction amount S is calculated using a microprocessor. The correction calculation can be performed at an extremely high speed as compared with the conventional technique, and the image processing can be speeded up.

The image data correction method of the present invention is not limited to that of the above embodiment, and the X and Y values can be changed appropriately according to the pixel density of reading, for example.

Also, the number of pixels n in the row direction or the column direction in the window is not limited to 3, but can be set to an odd value of 5 or more.

Further, the delay means is not limited to the FIFO memory as long as it can delay the input image data by a predetermined time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of an apparatus for implementing an image data correction method of the present invention.

FIG. 2 is a schematic diagram for explaining the concept of an image data correction method according to an embodiment of the present invention.

FIG. 3 is a block diagram showing in detail a delay line control unit shown in FIG.

FIG. 4 is a diagram conceptually showing an area of image data input to the apparatus shown in FIG.

FIG. 5 is a flowchart showing a write operation and a read operation for the first delay line of the delay line control unit.

FIG. 6 is a flowchart showing a write operation and a read operation with respect to a second delay line of the delay line control unit.

FIG. 7 is a flowchart showing a write operation and a read operation of a delay line control unit with respect to a third delay line.

FIG. 8 is a flowchart showing a write operation and a read operation of a delay line control unit with respect to a fourth delay line.

FIG. 9 is a flowchart showing a latch signal output operation for the latch of the delay line control unit.

[Explanation of symbols]

 1A 1st delay line 1B 2nd delay line 1C 3rd delay line 1D 4th delay line 2-6,9 Arithmetic circuit (four arithmetic operations) 7,8 Latch 11 Image data area 12 Central pixel in window 13 , 14 window 15 Pixel with latest image data

Claims (2)

[Claims] 1. A window of an n × n pixel matrix (where n is an odd number) is set for image data obtained by scanning an original image in a time series, and a predetermined arithmetic processing is performed on the image data. Thus, the correction amount S for the image data value a _mm of the pixel at the center position of the window is obtained, and the correction amount S
In the image data correction method for correcting the image data value a _mm in accordance with the above, a plurality of image data delays having delay amounts such that there is no difference in the obtained timings of the image data obtained in time series An image data correction method, characterized in that the correction amount S is obtained by inputting the correction amount S into the means and performing arithmetic processing on the plurality of image data output from the image data delay means. 2. When the latest image data value a _in is obtained, it is the same as the pixel having the latest image data value a _in from the first delay means of the plurality of image data delay means. The image data value A of the pixel n rows before in the column is transferred from the second delay means to the pixels n−1 / 2 rows and n−1 / 2 columns before the pixel having the latest image data value a _in . The image data value B of the pixel is output from the third delay means to the addition value C of the image data of each pixel in the same column as the pixel having the latest image data value a _in and n rows before to 1 row before. , The fourth delay means outputs the addition value D of the image data of each pixel from the pixel having the latest image data value a _in n columns before and (n-1) th row to the same row. computing equation ^{n 2 B- (T + C-} a-D + a in) ( where, B = a _mm, T is the total in the window that is previously set It said image data value a _mm based on the image sum of data)
2. The image data correction method according to claim 1, wherein a correction amount S for