JPH0594367A - Buffer storage device - Google Patents

Abstract

PURPOSE:To speed up the processing while improving the hit rate by residing the frequently used data in a buffer storage device permitting the resident of arbitrary data. CONSTITUTION:The buffer storage device is provided with a data storage part 2 storing data, a tag storage part 1 storing tag data having a resident bit indicating presence of residence in addition to an effective bit indicating the presence or absence of the address corresponding to the storage data and the storage data and a control part 3 controlling the data storage part 2 and the tag storage part 1 while comparing the state of the host address and a resident bit control line 10 with the tag data information from the tag storage part 1. A resident bit control line 10 is operated to set whether it is resident or not, and the resident data stored in the buffer device will not be replaced by non-resident data. When the frequently used data is set to 'resident', the hit rate is improved and the utilizing efficiency of the buffer storage device is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer storage device, and more particularly to a buffer storage device capable of resident arbitrary data.

[0002]

2. Description of the Related Art A buffer storage device is a storage device provided between a CPU and a main memory and capable of high-speed operation. Data in the main storage is transferred and stored in blocks, and the stored data is repeated. It is intended to speed up the whole process by shortening the time when it is used. The conventional buffer storage device has a configuration in which when the data storage area in the device becomes full, the already stored data is erased in a predetermined order and replaced with newly read data. The data could not be made resident in the buffer device.

[0003]

In the above-mentioned conventional buffer storage device, arbitrary data cannot be made resident, so that different data which are infrequently used are used one after another and stored in the buffer storage device. As a result, the frequently used data is erased, and the processing performance is significantly reduced.

It is an object of the present invention to provide a buffer storage device which can be made resident in the device without erasing any specified data.

[0005]

SUMMARY OF THE INVENTION A buffer storage device according to the present invention includes a data storage unit for storing data read by a CPU, address information and data corresponding to the data stored in the data storage unit. Tag storage unit for storing tag data having a valid bit indicating presence or absence and a resident bit indicating resident or non-resident, control information indicating whether or not resident target data given by a resident bit control line, and the tag. And a control unit for controlling the data storage unit and the tag storage unit according to the tag data information from the storage unit.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

As shown in FIG. 1, the buffer storage device of this embodiment includes a data storage unit 2 for storing data,
A tag storage unit 1 for storing tag data having an address corresponding to stored data and a valid bit indicating presence / absence of stored data, and a resident bit indicating whether or not resident, upper address information and resident bit control line 10 The control information of 1 is compared with the tag data information from the tag storage unit 1 to control the data storage unit 2 and the tag storage unit 1. 2 shows the structure of the tag data stored in the tag storage unit 1.

The operation of this embodiment will be described in detail below with reference to FIGS.

The tag data read from the tag storage unit 1 by the lower address given through the lower address path 4 is passed to the control unit 3 through the tag data path 7. At the same time, the control unit 3 is provided with the upper address path 5
Control information indicating whether or not the access data is resident target data is given through the resident bit control line 10 through.

The control unit 3 first checks the valid bit 12 in the tag data, and if the valid bit 12 is "1" (valid), compares the upper address with the address unit 11 in the tag data. If the contents of the upper address and the contents of the address section 11 are the same and if it is a read operation, the data read from the data storage section 2 by the lower address is output to the data path 6. If it is a write operation, the data given through the data path 6 is stored in the data storage unit 2.

When the contents of the upper address and the address portion 11 do not match and the write operation is performed, the main memory request line 8
To notify the operation request to the main memory, write the data from the CPU directly to the main memory, and complete the operation without updating the data storage unit 2 and the tag storage unit 1.

When the contents of the upper address and the address portion 11 do not match and the reading operation is performed, the resident bit control line 10
And the resident bit 13 in the tag data are compared.
When the state of the resident bit control line 10 is "0" (nonresident) and the resident bit 13 is "1" (resident), an operation request is sent to the main memory, and the data in the main memory is directly passed to the CPU. The operation is completed without updating the data storage unit 2 and the tag storage unit 1.

When the resident bit control line 10 and the resident bit 13 are in a combination other than the above, and when the valid bit 12 is "0" (invalid), the CPU does not directly read the data from the main memory but the buffer memory. A data block containing the target data is stored in the device, and the target data is read out from the data block. That is, the main memory is requested to read the data block, and the data block read from the main memory is stored in the data storage unit 2 through the data path 6. At this time, the corresponding upper address is stored in the tag storage unit 1 through the tag data path 7 as the address unit 11
Stored in. The resident bit 13 stores the contents of the resident bit control line 10, and the valid bit 12 has "1".
(Valid) is stored. The data storage unit 2 and the tag storage unit 1 are controlled by the storage unit control line 9.

As described in detail above, in the buffer storage device of this embodiment, when the resident bit control line 10 is set to "1" (resident) when reading arbitrary data, The data can reside in buffer storage. Therefore, if frequently used data is set to be resident and infrequently used data is set to be nonresident, infrequently used data is mainly read from the main memory,
Frequently used data is mainly read from the buffer storage device.

[0016]

As described above, in the buffer storage device of the present invention, arbitrary data can be made resident in the buffer storage device, so that there is an effect that the use efficiency of the buffer storage device can be improved. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a configuration diagram of tag data stored in a tag storage unit of the present embodiment.

[Explanation of symbols]

 1 Tag Storage Section 2 Data Storage Section 3 Control Section 4 Lower Address Path 5 Upper Address Path 6 Data Path 7 Tag Data Path 8 Main Memory Request Line 9 Storage Section Control Line 10 Resident Bit Control Line 11 Address Section 12 Valid Bit 13 Resident Bit

Claims (1)

[Claims] 1. A data storage unit for storing data read by a CPU, address information corresponding to the data stored in the data storage unit, and a valid bit indicating presence / absence of data, and resident or nonresident. A tag storage unit for storing tag data having a resident bit indicating the data stored by the tag data information from the tag storage unit and control information indicating whether the data is resident target data given by a resident bit control line. And a control unit for controlling the tag storage unit.