JPH0594304A - Interrupt controller - Google Patents

Abstract

PURPOSE:To eliminate pipeline break to the branching due to interrupt in a computer having the instruction execution mechanism of a pipeline control system. CONSTITUTION:The controller is connected to a processor 8 to perform an instruction by a pipeline circuit 1 composed of plural stages 4, has a buffer 2 and an interrupt control part 3, and the buffer 2, when each instruction is controlled by the necessary stages 4 concerning the necessary instruction, holds control information 5 set at the stages. The interrupt control part 3, when the branching to the prescribed interruption destination instruction occurs, inputs and performs each control information 5 of the buffer 2 to the prescribed stages 4 by the prescribed sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller for controlling the execution of an instruction by an interrupt by connecting to a processor having an instruction execution mechanism of a pipeline control system in a computer.

[0002]

2. Description of the Related Art In a processor of a computer, a pipeline control method is used as one method for speeding up execution of instructions by parallelizing them.

The pipeline circuit in the pipeline control system divides the process of instruction fetch, instruction decode, operand address calculation, operand read, operation, and operand write in the execution of one instruction by a plurality of stages. Composed.

Each instruction is controlled so that its execution is completed by passing through those stages in a certain order. At each time point, each stage processes a different instruction, so that the number of instructions up to the stage number is increased. Parallel processing is performed and, for example, when the stage is passed every control cycle, the instruction execution is completed every cycle.

However, when a branch instruction is executed and a branch occurs, the processing of the instruction at the stage subsequent to the branch instruction in the pipeline circuit is cleared and the processing of the instruction at the branch destination is started from the first stage. Have to start.

Therefore, in that case, a so-called pipeline break occurs in which no instruction is completed for several cycles until the instruction sequentially passes through a plurality of stages and finishes the processing of the final stage. Circuit parallelism does not work effectively.

FIG. 5 (a) is a diagram for explaining this situation, showing the timing of instruction execution.
Assuming that the pipeline circuit has four stages up to the stage, and that time elapses from the left to the right, the stages occupied by each instruction in each cycle are indicated by.

As shown in the figure, while the instructions A, B, and C are sequentially fetched and executed, each instruction completes execution in the cycle indicated by each instruction, and thus the instruction completes every cycle.

Here, there is a branch instruction after the instruction C,
Instructions sequentially following the branch instruction are instructions D, E, and F
When a branch occurs as a result of the execution of a branch instruction (shaded in the figure), the instructions D, E, and F at the stage in the middle of that time are interrupted from processing, and the pipeline is executed. The circuit is cleared.

After that, the branch destination instruction designated by the branch instruction is processed from the first stage of the pipeline circuit, and as shown in the figure, a pipeline break occurs until the timing when the processing of the branch destination instruction ends the final stage. Become.

In order to reduce the occurrence of pipeline breaks as described above, there is a delayed branch method. In this method, several instructions following a branch instruction are controlled so that they are always executed regardless of the occurrence of a branch. The instruction sequence is programmed to correspond to the control.

Therefore, even if a branch occurs, it is not necessary to clear the uncompleted subsequent instructions in the pipeline circuit, and the branch destination instruction is executed following these instructions. Further, in the branch prediction method, it is possible to select whether to fetch the instruction following the branch instruction or the instruction at the branch destination, following the branch instruction, for example, by referring to the condition of the branch condition being satisfied in the branch instruction so far. By the control, the number of cases in which the pipeline circuit is cleared by the branch instruction execution result is stochastically reduced.

Therefore, if such measures are taken,
By programming to make effective use of that function, pipeline breaks can be expected to decrease.

[0014]

However, as is clear from the above description, the countermeasure for the pipeline break as described above can be used only when the branch instruction is programmed and the timing at which the branch occurs can be scheduled. It cannot be used when branching to an interrupt routine due to an interrupt that occurs at an unpredictable timing.

An object of the present invention is to provide an interrupt control device capable of eliminating a pipeline break for a branch caused by an interrupt.

[0016]

FIG. 1 is a block diagram showing the configuration of the present invention. FIG. 1 shows the configuration of an interrupt controller, which is a pipeline circuit 1 including a plurality of stages 4.
It has a buffer 2 and an interrupt control unit 3 connected to a processing unit 8 for executing instructions.

The buffer 2 holds, for each of the required instructions, control information 5 which is set in each stage when the instruction is controlled in the required stage 4. The interrupt control unit 3, when a branch to a predetermined interrupt destination instruction occurs,
The control information 5 of the buffer 2 is input to a predetermined stage 4 in a predetermined order and executed.

In that case, the interrupt control section 3 sequentially inputs each control information 5 of the buffer 2 to a specific one stage 4 to be executed, or each control information 5 for each control information 5 is executed. You may make it input into separate stage 4 simultaneously, and may be performed.

Further, the interrupt control device further includes a return buffer 6 and a return control section 7, and the return buffer 6
Holds the control information 5 for the required instructions, which is set in the stage when each instruction is controlled in the required stage 4.

When it is detected that the execution of the specific instruction has reached the specific stage, the recovery control unit 7 inputs each control information 5 of the recovery buffer 6 to the specific stage 4 in the specific order. Let it run.

[0021]

Operation: For example, the instruction of the first part of the interrupt routine is
Except from the program, control information for executing those instructions is prepared in the buffer of the interrupt control device of the present invention.

In this way, even if the pipeline circuit is cleared due to the branch to the interrupt destination due to the occurrence of the interrupt, until all stages of the pipeline circuit are filled with the instruction sequence of the interrupt processing routine. The control information in the buffer will be executed and you can prevent pipeline breaks from occurring.

If a return buffer is provided, the same effect can be obtained even when the interrupt processing is completed and a branch is made to return to the interrupted program.

[0024]

FIG. 2 is a block diagram showing an embodiment of the present invention. A buffer 10 comprises a required number of registers 11, and each register 11 holds control information for one instruction. Buffer 10
The control information can be set in advance by a program.

The required number of registers 11 is one less than the number of stages of the pipeline circuit 12 when a branch destination instruction is immediately input to the pipeline circuit in the next cycle when a branch occurs due to an interrupt. Often, in a system where it takes time to fetch a branch target instruction, it is desirable to increase the number of registers accordingly.

The registers 11 are connected so as to sequentially shift control information among the registers, and the registers 11 at the final stage are connected.
The output of is input to the final stage 13. This pipeline circuit 12 is assumed to write the processing result of the operand in the final stage as in many cases, and the control information held in each register 11 is stored in, for example, FIG. Like

As shown in the figure, the control information of FIG. 3A consists of a valid bit, a transfer source register number, and a transfer destination register number. The valid bit indicates the validity of the content of the control information.
By setting the valid information in the final stage 13, data can be transferred between the general-purpose registers having the designated register numbers.

When the interrupt control unit 14 detects the occurrence of a branch due to an interrupt with a signal from the processing unit, the control information of the register 11 is sequentially shifted in synchronization with the control cycle of the pipeline, and the final stage 13 Since the control information is valid, it is executed in the final stage if the control information is valid.

Therefore, by converting a transfer instruction between general-purpose registers, which needs to be performed in the first part of the interrupt processing, for example, to save the contents of the general-purpose registers, into the control information and place it in the buffer 10. , It is possible to prevent pipeline break at interrupt.

FIG. 5 (b) is a diagram for explaining this situation.
As a pipeline similar to that shown in FIG. 5A, it is assumed that instructions A to D are sequentially fetched and processed by a pipeline circuit as shown in FIG. Assume that a branch has occurred due to an interrupt.

Therefore, the instructions B, C, and D in the intermediate stages are cleared, and the instructions of the interrupt processing routine sequentially enter the pipeline circuit as shown below in the line of the interrupt destination instruction. It will be a pipeline break of 3 cycles until completion.

However, as described above, by executing the control information sequentially supplied from the buffer 10 to the final stage, the pipeline break is filled as shown in the figure, and the processing of the interrupt processing routine becomes efficient. Well done.

In the above description, the control information is limited to the transfer between registers. However, as shown in FIG. 3B, for example, the operation information, the register number of the operand, or the immediate value can be specified by the control information, so that various kinds of data can be specified. The arithmetic instruction of may be in a buffer.

In that case, if necessary due to the configuration of the pipeline circuit, the stage for setting the control information is set to a stage before the final stage, or the first control information is set to the final stage, and at the same time, the second stage is set. The control information is set in the preceding stage, and subsequent control information is sequentially input to the same stage.

FIG. 4 shows another embodiment of the present invention. For example, a required number of registers 21 are provided in the buffer 20 to hold control information, and the output of each register 21 is output to the final stage of the pipeline circuit 22, for example. To the required stage before that, each stage 23 is connected.

The interrupt control unit 24, when detecting the occurrence of a branch due to an interrupt from the processing device, if the control information valid in the buffer 20 is set, the control information held by all the registers 21 is collectively sent to each stage 23. Set to.

The return buffer 15 and the return controller 16 shown in FIG.
Is a mechanism for compensating for a pipeline break caused by a branch for returning from an interrupt to an interrupted program.

In the illustrated example, the return buffer 15 is the buffer 10
The register 17 is connected in the same configuration as the above, and the output of the register 17 at the final stage is connected to the final stage 13 of the pipeline circuit as in the case of the buffer 10.

In general, a specific type of unconditional branch instruction (hereinafter referred to as a specific jump instruction) is provided as a branch instruction used when returning from an interrupt.
The return control unit 16 detects that the specific jump instruction has been executed by a signal from the processing device.

The return control unit 16 operates by the above detection, and similarly to the case of the interrupt control unit 14, the control information held by the return buffer 15 is sequentially input to the stage 13 to be executed. The control information may be in the same format as above.

Therefore, an instruction string such as an inter-register transfer instruction for recovering the register contents, which is necessary in the final part of the interrupt processing routine, is excluded from the program and held in the return buffer 15 as control information. , The pipeline break until the first instruction of the return destination reaches the final stage of the pipeline can be resolved.

FIG. 5 (c) is a diagram for explaining the situation,
As a pipeline circuit similar to (a), an interrupt processing routine is executed like instructions A and B, then the specific jump instruction is executed, and the interrupted program is restored by hatching in the figure. Suppose a branch to the previous instruction occurs.

Therefore, as shown in the figure, the instruction at the return destination sequentially enters the pipeline circuit, but a pipeline break of at least 3 cycles occurs until the first instruction at the return destination is completed 4 cycles later.

However, as described above, the return buffer
By executing the control information sequentially supplied from 15 to the final stage, the pipeline break is filled in as shown, and the final part of the interrupt processing routine is processed.

The instruction to be cleared following the specific jump instruction is, for example, garbage information fetched by regarding the information at the address following the specific jump instruction as an instruction.

As is clear from the above operation, in this example, the original instruction to be held as the control information in the return buffer 15 is a normal program and is executed between the instruction B and the specific jump instruction. Corresponds to the instruction sequence of the interrupt processing routine performed.

[0047]

As is apparent from the above description, according to the present invention, in a computer having a pipeline control type instruction execution mechanism, a pipeline break can be eliminated for a branch due to an interrupt, so that the processing of the computer is performed. There is a significant industrial effect of improving efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of control information.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram illustrating timing of instruction execution.

[Explanation of symbols]

 1, 12, 22 Pipeline circuit 2, 10, 20 Buffer 3, 14, 24 Interrupt control unit 4, 13, 23 Stage 5 Control information 6, 15 Return buffer 7, 16 Return control unit 8 Processor 11, 17, 21 register

Claims (4)

[Claims] 1. A pipeline circuit (1) comprising a plurality of stages (4) is connected to a processor (8) for executing instructions, and has a buffer (2) and an interrupt controller (3), The buffer (2) holds, for each of the required instructions, control information (5) set in the relevant stage when the instruction is controlled in the required stage (4), and the interrupt control unit ( 3) is for each control information (5) of the buffer (2) when a branch to a predetermined interrupt destination instruction occurs.
Is configured to be input to and executed in a predetermined stage (4) in a predetermined order. 2. The interrupt control unit (3) comprises the buffer
From (2) to the control information (5), the specific one of the stages
The interrupt control device according to claim 1, wherein the interrupt control device is sequentially input to (4) and executed. 3. The interrupt control unit (3) is provided with the buffer.
The control information (5) of (2) is simultaneously input to the individual stage (4) for each control information and executed.
The interrupt control device described. 4. The interrupt control device according to claim 1, claim 2, or claim 3, comprising a return buffer (6) and a return controller (7), wherein the return buffer (6) Holds the control information (5) set for each of the required instructions when the instruction is controlled at the required stage (4), and the return control unit (7) When it is detected that the execution of the above has reached the specific stage (4), each control information (5) of the return buffer (6) is input to the predetermined stage in a predetermined order and executed. An interrupt control device having the following configuration.