JPH0590733A - Method for forming conductor pattern on circuit board made of synthetic resin - Google Patents

Method for forming conductor pattern on circuit board made of synthetic resin

Info

Publication number
JPH0590733A
JPH0590733A JP25252891A JP25252891A JPH0590733A JP H0590733 A JPH0590733 A JP H0590733A JP 25252891 A JP25252891 A JP 25252891A JP 25252891 A JP25252891 A JP 25252891A JP H0590733 A JPH0590733 A JP H0590733A
Authority
JP
Japan
Prior art keywords
circuit board
synthetic resin
terminal electrode
electroless plating
injection molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25252891A
Other languages
Japanese (ja)
Other versions
JP3016922B2 (en
Inventor
Takashi Kobayashi
崇司 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP3252528A priority Critical patent/JP3016922B2/en
Publication of JPH0590733A publication Critical patent/JPH0590733A/en
Application granted granted Critical
Publication of JP3016922B2 publication Critical patent/JP3016922B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To enable a circuit pattern for various kinds of electronic parts to be mounted on a circuit board which is formed by injection molding of a synthetic resin and at the same time a terminal electrode pattern for connection to an outside to be formed on a rising surface or a falling surface for a plane part where the circuit pattern is formed. CONSTITUTION:A plane part 4 where electronic parts are mounted and a circuit board 2 which is provided with a rising part or a falling part is formed by injection molding of synthetic resin, the plane part 4 is subjected to injection molding of synthesis resin where a catalysis for electroless plating is blended, and at the same time a terminal electrode pattern forming part 11 made of synthetic resin where the catalysis for electroless plating is blended is subjected to injection molding at the rising or falling parts. Then, electroless plating is performed entirely for forming a terminal electrode pattern 9 on a surface of the terminal electrode pattern forming part 11, while a circuit pattern 5 is formed by patterning by radiation of ultraviolet rays with a mask and by applying photoresist on the surface of the plane part 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、合成樹脂の射出成形に
よって形成するようにした回路基板の表面に、当該回路
基板に搭載した各種の電子部品の相互間を接続する回路
パターン、及びこれらを他の機器に対して接続するため
の端子電極パターンとを有する導体パターンを形成する
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit pattern formed by injection molding of synthetic resin on a surface of a circuit board for connecting various electronic components mounted on the circuit board to each other, and a circuit pattern for connecting these electronic parts. The present invention relates to a method for forming a conductor pattern having a terminal electrode pattern for connecting to another device.

【0002】[0002]

【従来の技術】従来、合成樹脂の射出成形によって形成
した回路基板の表面に対して、導体パターンを形成する
方法には、合成樹脂製の回路基板の表面に、フォトレジ
ストを塗布し、マスクを用いて露光・現像することによ
りパターニングし、無電解メッキ法により導体パターン
を形成する方法(フォトアディティブ法)と、無電解メ
ッキ用触媒を配合しない合成樹脂にて回路基板を射出成
形し、次いで、この回路基板に対して、無電解メッキ用
触媒を配合した合成樹脂にて、所定の導体パターン通り
の形状を有する導体パターン形成部を射出成形し、この
無電解メッキ用触媒を配合した合成樹脂製の導体パター
ン形成部の表面に、無電解メッキにて所定の導体パター
ンを形成する方法(2回成形法)とがある。
2. Description of the Related Art Conventionally, a method of forming a conductor pattern on a surface of a circuit board formed by injection molding of synthetic resin is to apply a photoresist to the surface of the circuit board made of synthetic resin and apply a mask. Patterning by exposing and developing using, a method of forming a conductor pattern by electroless plating (photoadditive method), and injection molding of a circuit board with a synthetic resin that does not contain a catalyst for electroless plating, and then On this circuit board, a synthetic resin containing a catalyst for electroless plating is used to injection-mold a conductor pattern forming portion having a shape according to a predetermined conductor pattern. There is a method (double molding method) of forming a predetermined conductor pattern on the surface of the conductor pattern forming portion by electroless plating.

【0003】[0003]

【発明が解決しようとする課題】しかし、前者のフォト
アディティブ法は、マスクを用いて紫外線照射によりパ
ターニングするため、導体パターンをファイン化できる
利点を有するが、その反面、垂直な面に対して導体パタ
ーンを形成することができず、換言すると、導体パター
ンを立体化することができないと言う問題がある。
However, the former photoadditive method has the advantage that the conductor pattern can be made finer because it is patterned by UV irradiation using a mask. On the other hand, on the other hand, the conductor pattern is perpendicular to the conductor surface. There is a problem that the pattern cannot be formed, in other words, the conductor pattern cannot be three-dimensionalized.

【0004】これに対して、後者の2回成形法は、導体
パターンを、無電解メッキ用触媒を配合しない合成樹脂
にて形成した回路基板に対して、無電解メッキ用触媒を
配合した合成樹脂にて所定の導体パターン通りの形状を
有する導体パターン形成部を射出成形することによって
形成するものであるから、垂直な面に対しても導体パタ
ーンを形成することができ、換言すると、導体パターン
の立体化に適合できる利点を有するが、その反面、導体
パターンの幅寸法には、合成樹脂の射出成形のために或
る寸法以下にすることができないので、導体パターンを
ファイン化することができないと言う問題があった。
On the other hand, in the latter two-time molding method, a synthetic resin in which a catalyst for electroless plating is mixed with a circuit board in which a conductor pattern is formed of a synthetic resin not containing a catalyst for electroless plating Since it is formed by injection molding a conductor pattern forming portion having a shape according to a predetermined conductor pattern, it is possible to form a conductor pattern even on a vertical surface. Although it has the advantage of adapting to three-dimensionalization, on the other hand, the width dimension of the conductor pattern cannot be made smaller than a certain dimension due to injection molding of synthetic resin, so that the conductor pattern cannot be made fine. There was a problem to say.

【0005】本発明は、これら、フォトアディティブ法
及び2回成形法が有する問題を解消した回路パターンの
形成方法を提供することを技術的課題とするものであ
る。
It is a technical object of the present invention to provide a method for forming a circuit pattern which solves the problems of the photoadditive method and the double molding method.

【0006】[0006]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、トランジスター等の各種電子部品を搭
載する平面部と、当該平面部に対する立ち上がり部又は
垂れ下がり部とを備えた回路基板を合成樹脂の射出成形
によって形成し、該回路基板における平面部を、無電解
メッキ用触媒を配合した合成樹脂にて射出成形すると同
時に、前記回路基板における立ち上がり部又は垂れ下が
り部の表面に、無電解メッキ用触媒を配合した合成樹脂
製の端子電極パターン形成部を射出成形し、次いで、全
体に無電解メッキを施して、前記端子電極パターン部の
表面に、端子電極パターンを形成する一方、前記平面部
の表面に、フォトレジストを施し、マスクを用いて紫外
線照射によりパターニングして、回路パターンを形成す
ることにした。
In order to achieve this technical object, the present invention provides a circuit board having a plane portion on which various electronic components such as transistors are mounted and a rising portion or a hanging portion with respect to the plane portion. It is formed by injection molding of a synthetic resin, and the flat surface portion of the circuit board is injection-molded with a synthetic resin mixed with an electroless plating catalyst, and at the same time, the surface of the rising portion or the hanging portion of the circuit board is electroless plated. A synthetic resin terminal electrode pattern forming portion containing a catalyst for injection is injection-molded, and then electroless plating is performed on the entire surface to form a terminal electrode pattern on the surface of the terminal electrode pattern portion, while the flat surface portion is formed. It was decided to form a circuit pattern by applying a photoresist to the surface of and then patterning it by UV irradiation using a mask.

【0007】[0007]

【作 用】このようにすると、回路基板のうち平面部
に対する立ち上がり部又は垂れ下がり部の表面には、前
記従来の2回成形法によって、端子電極パターンを立体
的に形成することができる一方、前記回路基板のうちト
ランジスター等の各種電子部品を搭載する平面部には、
マスクのパターニングによって、回路パターンを、ファ
イン化して形成することができるのである。
[Operation] By doing so, the terminal electrode pattern can be three-dimensionally formed on the surface of the rising portion or the hanging portion with respect to the flat portion of the circuit board by the conventional double molding method. On the plane part where various electronic parts such as transistors are mounted on the circuit board,
By patterning the mask, a fine circuit pattern can be formed.

【0008】[0008]

【発明の効果】従って、本発明によると、回路基板のう
ち各種電子部品を搭載する平面部に、回路パターンをフ
ァイン化して形成することと、前記回路基板のうち前記
平面部に対する立ち上がり部又は垂れ下がり部の表面
に、外部への接続用の端子電極パターンを、立体的に形
成することとを同時に達成できる効果を有する。
As described above, according to the present invention, a circuit pattern is finely formed on a plane portion of a circuit board on which various electronic components are mounted, and a rising portion or a sag of the circuit board with respect to the plane portion is formed. This has the effect of simultaneously forming a terminal electrode pattern for connection to the outside in three dimensions on the surface of the portion.

【0009】[0009]

【実施例】以下、本発明の実施例を、図1及び図2に示
すように、ハイブリッド集積回路装置用の回路基板に対
して導体パターンを形成する場合について説明する。す
なわち、前記図1及び図2に示すハイブリッド集積回路
装置1は、合成樹脂の射出成形によって形成した回路基
板2の下面に、左右一対の脚部3を一体的に造形し、前
記回路基板1における平面部4の上面及び下面に、回路
パターン5,6を各々形成したのち、各種の電子部品
7,8を搭載する一方、前記両脚部3の表面に、外部へ
の接続用の端子電極パターン9を複数本ずつ形成したも
のである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to a case where a conductor pattern is formed on a circuit board for a hybrid integrated circuit device as shown in FIGS. That is, in the hybrid integrated circuit device 1 shown in FIGS. 1 and 2, a pair of left and right leg portions 3 are integrally formed on the lower surface of the circuit board 2 formed by injection molding of synthetic resin. After the circuit patterns 5 and 6 are formed on the upper and lower surfaces of the flat portion 4, various electronic components 7 and 8 are mounted, and on the surfaces of the leg portions 3, terminal electrode patterns 9 for external connection are formed. It is formed by a plurality of each.

【0010】前記回路基板1における左右一対の両脚部
3を、図3に示すように、無電解メッキ用触媒を配合し
ない合成樹脂の射出成形によって形成する。このとき、
両脚部3の表面うち前記端子電極パターン9に該当する
部分には、凹み溝10を形成する。次いで、前記両脚部
3の間の部分に、図4〜図7に示すように、前記回路基
板2における平面部4を、無電解メッキ用触媒を配合し
た合成樹脂の射出成形によって形成する。このとき同時
に、無電解メッキ用触媒を配合した合成樹脂を、前記両
脚部3における各凹み溝10内に充填することによっ
て、各凹み溝10内に、無電解メッキ用触媒を配合した
合成樹脂製の端子電極パターン形成部11を形成する。
The pair of left and right legs 3 of the circuit board 1 are formed by injection molding of a synthetic resin containing no electroless plating catalyst, as shown in FIG. At this time,
A recessed groove 10 is formed in a portion of the surface of both legs 3 corresponding to the terminal electrode pattern 9. Next, as shown in FIGS. 4 to 7, a flat surface portion 4 of the circuit board 2 is formed in a portion between the leg portions 3 by injection molding of a synthetic resin containing a catalyst for electroless plating. At this time, at the same time, a synthetic resin containing a catalyst for electroless plating is filled in each recessed groove 10 in each of the leg portions 3 to make a synthetic resin containing a catalyst for electroless plating in each recessed groove 10. The terminal electrode pattern forming portion 11 is formed.

【0011】次に、前記回路基板2の全体に対して銅の
無電解メッキを施することにより、当該回路基板2のう
ち無電解メッキ用触媒を配合した合成樹脂製の部分の表
面に対して銅のメッキ層を形成する。そして、前記回路
基板2における平面部4の上面及び下面に、図8に示す
ように、フォトレジスト用のドライフィルム12,13
を貼付けし、次いで、このフォトレジスト用のドライフ
ィルム12,13に対して、前記回路パターン5,6と
同じ形状に打ち抜いたマスクを使用して露光・現像する
ことにより、図9に示すように、前記ドライフィルム1
2,13に、前記回路パターン5,6の形状通りの抜き
窓14を形成する。なお、ここにおけるフォトレジスト
は半田メッキレジストを言う。
Next, electroless plating of copper is performed on the entire circuit board 2 so that the surface of the portion of the circuit board 2 made of a synthetic resin containing an electroless plating catalyst is mixed. Form a copper plating layer. Then, as shown in FIG. 8, dry films 12 and 13 for photoresist are formed on the upper surface and the lower surface of the flat portion 4 of the circuit board 2.
9 is applied, and then the dry films 12 and 13 for photoresist are exposed and developed using a mask punched out in the same shape as the circuit patterns 5 and 6, as shown in FIG. , The dry film 1
Formed in windows 2 and 13 are windows 14 having the same shapes as the circuit patterns 5 and 6. The photoresist here is a solder plating resist.

【0012】これが終わると、前記回路基板2は半田メ
ッキを施すのであり、この半田メッキにより、前記各端
子電極パターン形成部11の表面、及び前記平面部4の
うち前記抜き窓14内の部分には、銅メッキ層を介して
半田メッキ層が付着する。そこで、前記フォトレジスト
用のドライフィルム12,13を除去したのち、銅を溶
かすエッチング液に浸漬することによって、平面部4に
おける余分な銅メッキ層を除去することにより、図10
に示すように、回路基板2における両脚部3の各々に、
端子電極パターン9を形成することができると共に、平
面部4の上下両面に、回路パターン5,6を形成するこ
とができるのである。
When this is finished, the circuit board 2 is subjected to solder plating, and this solder plating causes the surface of each terminal electrode pattern forming portion 11 and the portion of the plane portion 4 inside the opening 14 to be formed. The solder plating layer is attached via the copper plating layer. Therefore, after removing the photoresist dry films 12 and 13, the excess copper plating layer on the flat portion 4 is removed by immersing in the etching solution that dissolves copper.
As shown in, each of the both leg portions 3 of the circuit board 2,
The terminal electrode pattern 9 can be formed, and the circuit patterns 5 and 6 can be formed on both upper and lower surfaces of the flat portion 4.

【0013】なお、前記実施例は、回路基板2における
平面部4の全体を、無電解メッキ用触媒を配合した合成
樹脂製にした場合を示したが、本発明は、これに限ら
ず、前記平面部4における表面のみを、無電解メッキ用
触媒を配合した合成樹脂製にしても良いのである。ま
た、前記回路基板2は、以下に述べるようにすることに
より、多量生産することができる。
In the above-described embodiment, the case where the entire flat portion 4 of the circuit board 2 is made of synthetic resin mixed with the electroless plating catalyst is shown, but the present invention is not limited to this. Only the surface of the flat portion 4 may be made of synthetic resin mixed with a catalyst for electroless plating. The circuit board 2 can be mass-produced by the following method.

【0014】すなわち、前記の構造を有する回路基板2
の複数個を、図11に示すように、互いに一体的に連結
した状態で、無電解メッキ用触媒を配合しない合成樹脂
による射出成形と、無電解メッキ用触媒を配合した合成
樹脂による射出成形との2回成形によって形成し、その
全体に銅の無電解メッキを施したのち、上下両面に、フ
ォトレジスト用のドライフィルム12,13を、各回路
基板2について連続して貼着し、次いで、前記ドライフ
ィルム12,13に、回路パターン5,6と同じ形状の
抜き窓14を露光・現像によって形成し、全体に半田メ
ッキを施し、前記ドライフィルム12,13を除去した
のち、銅を除くエッチングを施すことによって、前記各
回路基板2の各々に、回路パターン5,6と、端子電極
パターン9を形成する。
That is, the circuit board 2 having the above structure
As shown in FIG. 11, in a state where they are integrally connected to each other, injection molding with a synthetic resin containing no electroless plating catalyst and injection molding with a synthetic resin containing an electroless plating catalyst are performed. After the electroless plating of copper is applied to the whole, the dry films 12 and 13 for photoresist are continuously attached to each of the circuit boards 2 on both upper and lower surfaces, and then, An opening 14 having the same shape as the circuit patterns 5 and 6 is formed on the dry films 12 and 13 by exposure and development, solder plating is applied to the entire surface, the dry films 12 and 13 are removed, and then etching for removing copper is performed. Then, the circuit patterns 5 and 6 and the terminal electrode pattern 9 are formed on each of the circuit boards 2.

【0015】そして、各絶縁基板2の各々に、各種の電
子部品7,8を搭載したのち、各回路基板2の間に刻設
したV溝型の筋目線15,16に沿って、各回路基板2
ごとにブレイクするものである。なお、前記実施例は、
回路基板2における下面に左右両側に脚部3を一体的に
造形して、この両脚部3に、端子電極パターン9を形成
したいわゆるデュアル型のハイブリッド集積回路装置1
に適用した場合を示したが、本発明は、これに限らず、
図12に示すように、回路基板2における下面の周囲に
脚部3を一体的に造形し、この各脚部3の各々に端子電
極パターン9を形成したいわゆるクワッド型のハイブリ
ッド集積回路装置1aに対しても同様にして適用できる
のである。
After mounting various electronic components 7 and 8 on each insulating substrate 2, each circuit is provided along the V-groove type crease lines 15 and 16 engraved between the circuit substrates 2. Board 2
It breaks every time. In addition, in the above embodiment,
A so-called dual-type hybrid integrated circuit device 1 in which leg portions 3 are integrally formed on the lower surface of the circuit board 2 on both left and right sides, and terminal electrode patterns 9 are formed on the both leg portions 3.
However, the present invention is not limited to this,
As shown in FIG. 12, a so-called quad-type hybrid integrated circuit device 1a in which the leg portions 3 are integrally formed around the lower surface of the circuit board 2 and the terminal electrode patterns 9 are formed on each of the leg portions 3 is formed. The same applies to the same.

【0016】そして、このクワッド型ハイブリッド集積
回路装置1aにおいても、前記と同様に、回路基板2の
複数個を、図13及び図14に示すように、互いに一体
的に連結した状態で、無電解メッキ用触媒を配合しない
合成樹脂による射出成形と、無電解メッキ用触媒を配合
した合成樹脂による射出成形との2回成形によって形成
し、その全体に銅の無電解メッキを施したのち、上下両
面に、フォトレジスト用のドライフィルム12,13
を、各回路基板2について連続して貼着し、次いで、前
記ドライフィルム12,13に、回路パターン5,6と
同じ形状の抜き窓14を露光・現像によって形成し、全
体に半田メッキを施し、前記ドライフィルム12,13
を除去したのち、銅を除くエッチングを施すことによっ
て、前記各回路基板2の各々に、回路パターン5,6
と、端子電極パターン9を形成し、次いで、各絶縁基板
2の各々に、各種の電子部品7,8を搭載したのち、各
回路基板2の間に刻設したV溝型の筋目線15,16に
沿って、各回路基板2ごとにブレイクすることにより、
多量生産できるのである。
Also in this quad hybrid integrated circuit device 1a, similarly to the above, a plurality of circuit boards 2 are electrolessly connected to each other as shown in FIGS. 13 and 14. It is formed by injection molding with a synthetic resin that does not contain a plating catalyst and injection molding with a synthetic resin that contains an electroless plating catalyst. After the entire surface is electrolessly plated with copper, both upper and lower surfaces are formed. And dry film 12, 13 for photoresist
Is continuously attached to each circuit board 2, and then, the dry film 12, 13 is formed with a window 14 having the same shape as the circuit patterns 5, 6 by exposure and development, and the whole is plated with solder. , The dry film 12, 13
By removing the copper and then performing etching except copper, the circuit patterns 5, 6 are formed on each of the circuit boards 2.
Then, after forming the terminal electrode pattern 9 and mounting various electronic components 7 and 8 on each of the insulating substrates 2, a V-groove type score line 15 formed between the circuit substrates 2 is formed. By breaking each circuit board 2 along 16,
It can be mass produced.

【図面の簡単な説明】[Brief description of drawings]

【図1】デュアル型ハイブリッド集積回路装置を上面か
ら見たときの斜視図である。
FIG. 1 is a perspective view of a dual type hybrid integrated circuit device when viewed from above.

【図2】デュアル型ハイブリッド集積回路装置を上面か
ら見たときの斜視図である。
FIG. 2 is a perspective view of the dual-type hybrid integrated circuit device as viewed from above.

【図3】回路基板における脚部を射出成形したときの斜
視図である。
FIG. 3 is a perspective view when the legs of the circuit board are injection molded.

【図4】回路基板における平面部を射出成形したときの
斜視図である。
FIG. 4 is a perspective view when a flat surface portion of a circuit board is injection molded.

【図5】図4のV−V視断面図である。5 is a cross-sectional view taken along line VV of FIG.

【図6】図4のVI−VI視断面図である。6 is a sectional view taken along line VI-VI of FIG.

【図7】図4のVII −VII 視断面図である。7 is a sectional view taken along line VII-VII of FIG.

【図8】回路基板における平面部にフォトレジスト用の
ドライフィルムを貼着したときの斜視図である。
FIG. 8 is a perspective view when a dry film for photoresist is attached to a flat surface portion of a circuit board.

【図9】前記フォトレジスト用のドライフィルムに回路
パターン用の抜き窓を形成したときの斜視図である。
FIG. 9 is a perspective view of a dry film for a photoresist, in which an opening for a circuit pattern is formed.

【図10】回路基板に回路パターンと端子電極パターン
とを形成した状態の斜視図である。
FIG. 10 is a perspective view showing a state where a circuit pattern and a terminal electrode pattern are formed on a circuit board.

【図11】デュアル型ハイブリッド集積回路装置に使用
する回路基板を一体的に形成した状態の斜視図である。
FIG. 11 is a perspective view showing a state in which a circuit board used for the dual type hybrid integrated circuit device is integrally formed.

【図12】クワッド型ハイブリッド集積回路装置を下面
から見たときの斜視図である。
FIG. 12 is a perspective view of the quad hybrid integrated circuit device when viewed from the bottom surface.

【図13】クワッド型ハイブリッド集積回路装置に使用
する回路基板を一体的に形成した状態の斜視図である。
FIG. 13 is a perspective view showing a state where a circuit board used in the quad hybrid integrated circuit device is integrally formed.

【図14】図13のXIV −XIV 視拡大断面図である。14 is an enlarged sectional view taken along line XIV-XIV of FIG.

【符号の説明】[Explanation of symbols]

1,1a ハイブリッド集積回路装置 2 回路基板 3 脚部 4 回路基板の平面部 5,6 回路パターン 7,8 電子部品 9 端子電極パターン 10 凹み溝 11 端子電極パターン形成部 12,13 フォトレジスト用ドライフィルム 14 回路パターン用抜き窓 15,16 ブレイク用のV溝型筋目線 1, 1a Hybrid integrated circuit device 2 Circuit board 3 Leg part 4 Plane part of circuit board 5,6 Circuit pattern 7,8 Electronic component 9 Terminal electrode pattern 10 Recessed groove 11 Terminal electrode pattern forming part 12, 13 Dry film for photoresist 14 Window for circuit pattern 15, 16 V-groove line for break

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】トランジスター等の各種電子部品を搭載す
る平面部と、当該平面部に対する立ち上がり部又は垂れ
下がり部とを備えた回路基板を合成樹脂の射出成形によ
って形成し、該回路基板における平面部を、無電解メッ
キ用触媒を配合した合成樹脂にて射出成形すると同時
に、前記回路基板における立ち上がり部又は垂れ下がり
部の表面に、無電解メッキ用触媒を配合した合成樹脂製
の端子電極パターン形成部を射出成形し、次いで、全体
に無電解メッキを施して、前記端子電極パターン形成部
の表面に、端子電極パターンを形成する一方、前記平面
部の表面に、フォトレジストを施し、マスクを用いて紫
外線照射によりパターニングして、回路パターンを形成
することを特徴とする合成樹脂製回路基板における導体
パターンの形成方法。
1. A circuit board having a flat portion on which various electronic components such as transistors are mounted and a rising portion or a hanging portion with respect to the flat portion is formed by injection molding of synthetic resin, and the flat portion on the circuit board is formed. , Injection molding with a synthetic resin containing a catalyst for electroless plating, and at the same time injection of a synthetic resin terminal electrode pattern forming part containing a catalyst for electroless plating on the surface of the rising portion or the hanging portion of the circuit board. Molded, then electroless plated on the entire surface to form a terminal electrode pattern on the surface of the terminal electrode pattern forming portion, while applying photoresist to the surface of the flat surface portion and irradiating ultraviolet rays using a mask A method for forming a conductor pattern in a synthetic resin circuit board, characterized by forming a circuit pattern by patterning with
JP3252528A 1991-09-30 1991-09-30 Method of forming conductive pattern on circuit board made of synthetic resin Expired - Fee Related JP3016922B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3252528A JP3016922B2 (en) 1991-09-30 1991-09-30 Method of forming conductive pattern on circuit board made of synthetic resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3252528A JP3016922B2 (en) 1991-09-30 1991-09-30 Method of forming conductive pattern on circuit board made of synthetic resin

Publications (2)

Publication Number Publication Date
JPH0590733A true JPH0590733A (en) 1993-04-09
JP3016922B2 JP3016922B2 (en) 2000-03-06

Family

ID=17238626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3252528A Expired - Fee Related JP3016922B2 (en) 1991-09-30 1991-09-30 Method of forming conductive pattern on circuit board made of synthetic resin

Country Status (1)

Country Link
JP (1) JP3016922B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111090A2 (en) 1999-12-21 2001-06-27 Ryoh Itoh Method for partially plating on a base
JP2002324819A (en) * 2001-04-24 2002-11-08 Matsushita Electric Works Ltd Ic mounting board and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111090A2 (en) 1999-12-21 2001-06-27 Ryoh Itoh Method for partially plating on a base
JP2002324819A (en) * 2001-04-24 2002-11-08 Matsushita Electric Works Ltd Ic mounting board and method for manufacturing the same
JP4604387B2 (en) * 2001-04-24 2011-01-05 パナソニック電工株式会社 IC mounting board

Also Published As

Publication number Publication date
JP3016922B2 (en) 2000-03-06

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