JPH0590284A - Hetero-junction bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a horizontal type bipolar transistor structure which is high in direct current amplification factor and operation speed by a method wherein an emitter is al 1 covered with an insulating film except its face which confronts a collector layer, and the center of a base layer is narrower than its peripheral part in band gap. CONSTITUTION:A first conductivity type emitter layer 27, a second conductivity type base layer 25, and a first conductivity type collector layer 28 are arranged in a single crystal semiconductor on an insulating film 12 buried in the semiconductor substrate 11 in a direction parallel with the surface of the semiconductor substrate 11. The first conductivity type emitter layer 27 is all covered with an insulating film excluding its surface which confronts the collector layer 27. Furthermore, the second conductivity type base layer 25 is formed of semiconductor material whose band gap is smaller than those of the first conductivity type emitter layer 27 and the collector layer 28, and center of the second conductivity type base layer 25 is set, narrower than its peripheral part in band gap.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device composed of an ultra-small lateral bipolar transistor and a heterojunction bipolar transistor, which has a high speed operation and a high performance in a wide current range.

[0002]

2. Description of the Related Art In recent years, with the rapid development of semiconductor technology, there is an increasing demand for higher integration and higher speed of semiconductor elements. In response to such a demand for high speed, a demand for high integration can be realized at the same time, so that the mainstream is to respond by miniaturization of elements.

At the same time, in MOS transistors, the technical miniaturization limit and operable limit of bulk type semiconductor devices are considered to be around 0.1 μm in channel length, and in the future, liquid nitrogen will be used. Temperature (77K)
There is an urgent need to lower the operating temperature, such as operation, or to apply a new element structure.

As one method for overcoming this limitation of the bulk type semiconductor device, thin film SOI (Silicon-On-Insul)
ator) MOS transistors are drawing attention. With this structure, there are advantages such as high mobility, high latch-up resistance, and high drain breakdown voltage, and experimental results have been reported that a device having a channel length of 0.1 μm level can operate with high performance even at normal temperature operation. From such a background, even in a BiCMOS element in which a bipolar transistor and a MOS transistor are mixedly mounted, a method of forming an element on a thin film SOI substrate is being studied. Thin film SOI
As an example of forming a bipolar transistor on the substrate,
Figure 6 (1991 Symp.VLSI Tech.Digest of Tech
nical Papers, p.53, N.Higaki, et al.).

However, as can be seen from the plan view shown in FIG. 7, the device shown in FIG. 6 has a structure in which the high-concentration n-type layer in the emitter region and the high-concentration p-type layer in the external base region are in contact with each other. Therefore, most of the electrons injected from the emitter region are recombined with the holes supplied from the high-concentration p-type region, so that the direct current amplification factor is about 15 as shown in FIG. There was a big problem that it became a very small value.

[0006]

As described above, the conventional technique has a serious problem that a sufficient value cannot be obtained for the direct current amplification factor of the lateral bipolar transistor.

The present invention has been made in view of this point, and an object of the present invention is to provide a lateral bipolar transistor structure capable of obtaining a high DC current amplification factor and a high speed operation characteristic.

[0008]

The present invention has a structure in which a high-concentration n-type emitter layer and a high-concentration p-type external base layer are separated by an insulating film or the like, and at least one of an emitter and a collector junction is heterogeneous. The junction is characterized in that the central portion of the internal base layer has a smaller bandgap than the peripheral portion near the external base layer. For example, in a heterojunction bipolar transistor that forms a base layer using a strained epitaxial layer SiGe alloy,
An internal base layer is used in which the germanium concentration distribution is set so that the band gap in the central part is narrower than that in the outer peripheral part.

[0009]

According to the present invention, the number of electrons injected from the peripheral portion of the emitter layer into the high-concentration base region is reduced, and Si
The electric field in the Ge alloy makes it possible to increase the number of electrons that reach the collector layer. As a result, it becomes possible to obtain a remarkably higher DC current amplification factor than in the past. Further, by controlling the Ge content in Si in the base layer so that the band gap in the central portion of the base layer is narrow, it is possible to increase the impurity concentration in the central portion of the base layer, At the same time as the base resistance can be reduced, it is possible to suppress the occurrence of the current concentration effect even in the high collector current region and achieve the improvement in high-speed performance.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a heterojunction bipolar transistor structure according to one embodiment of the present invention (FIG. 1).
FIG. 2A is a cross-sectional view (FIG. 1B) taken along the line LL ′ in the plan view.

In FIG. 1, n ^{− −} ions are formed by ion implantation of silicon atoms and subsequent thermal oxidation or a wafer attachment technique. A silicon oxide film layer 12 is embedded in the type silicon layer 11, and a single crystal silicon layer is formed thereon. Further, by patterning for element isolation, a silicon oxide film is formed around the element region. Next, the low concentration n-type layer 20 is formed by ion implantation of phosphorus. Then, a high-concentration p-type layer to be an external base layer and a base electrode lead-out portion is formed by ion implantation, and then a patterned CVD silicon oxide film, and
Germanium ion implantation is performed using the silicon nitride film left on the sidewalls as a mask, and the SiGe alloy layer 25 serving as the intrinsic base region has a Ge concentration in the SiGe from the center of the intrinsic base region toward the external base. It is formed so as to decrease. Further, a high-concentration n-type emitter region 27 and a collector region 28 are simultaneously formed by arsenic ion implantation using the resist as a mask. At this time, the intrinsic base-side metallurgical junction end of the high-concentration n-type emitter region is formed so as not to contact the SiGe alloy layer 25. Then, after depositing a CVD silicon oxide film, contacts for the emitter, base and collector are opened, and finally an emitter electrode 30, a base electrode 31 and a collector electrode 32 made of a metal such as Al are formed.

Next, one manufacturing method of the above structure will be described with reference to sectional views of manufacturing steps. 2 to 4 (a) to (g)
Shows a specific manufacturing process of the structure of FIG. First, n
^- The silicon substrate 11 is oxidized by ion implantation of silicon, or using a wafer attachment technique,
A silicon oxide film 12 is embedded in a silicon substrate 11.
Then, a 1000 A (A is angstrom, the same applies hereinafter) silicon thermal oxide film (not shown) is formed and peeled off, and then a 500 A thermal oxide film 13 is formed. 100 more
A 0A polysilicon film 14, a 1500A silicon nitride film 15, and a 4000A polysilicon film 16 are deposited (FIG. 2A).

Next, after the polysilicon film 16 is etched by the reactive ion etching method using a photoresist mask (not shown), it is 40 at 1000.degree.
It is exposed to a water vapor atmosphere for 0 minutes to form a silicon oxide film 17 of 11000A. Furthermore, silicon oxide film 1
The silicon nitride film 15 is patterned by the reactive ion etching method using 7 as a mask (FIG. 2).
(B)).

Next, the silicon oxide film 17 is removed by a wet etching method, and then exposed to an oxygen atmosphere diluted with nitrogen at 1000 ° C. for 60 minutes, and the silicon nitride film 15 is used as a mask to form the silicon oxide film 18 of 6000 A.
Are formed (FIG. 2C).

Further, after removing the silicon nitride film 15 by the CDE method, 25 is newly formed on the entire surface of the silicon substrate.
A CVD silicon oxide film 19 of 00A is deposited, and the CVD silicon oxide film 19 is patterned by a reactive ion etching method using a photoresist mask (not shown). Next, acceleration voltage 100 KeV, dose 1
Under the condition of × 10 ¹² cm ^-2 , phosphorus is ion-implanted on the entire surface to form the low concentration n-type layer 20 (FIG. 3).
(D)). In addition, in FIG. 3D and subsequent figures, only the main part of the element is enlarged and shown. A plan view of FIG. 3 (d) is shown in FIG. 5 (a). Note that FIG. 3D is a cross-sectional view taken along the line AA ′ in FIG.

Next, after depositing a silicon nitride film 21 having a film thickness of 1000 A on the entire surface, it is etched back by using the reactive ion etching method to leave only on the side wall of the CVD silicon oxide film 19. Further, under the conditions of an accelerating voltage of 15 keV and a dose of 1 × 10 ¹⁴ cm ⁻² , boron ion implantation is performed on the entire surface to form a p-type layer 22 (FIG. 3E).

Further, the silicon nitride film 21 and the CVD
After peeling off the silicon oxide film 19, again CVD is performed on the entire surface.
A silicon oxide film 23 and a silicon nitride film 24 are deposited,
Etch back using the reactive ion etching method,
The silicon nitride film 24 is left only on the side wall of the CVD silicon oxide film 23. Next, germanium ion implantation is performed on the entire surface to form a P-type layer 25 containing germanium (FIG. 3F). Here, B- in FIG.
A cross-sectional view of a plane perpendicular to the plane of the paper in the B'direction is shown in FIG.

Next, the CVD silicon oxide film 23 and the silicon nitride film 24 are peeled off, a photoresist 26 is applied and patterned, and then the entire surface is ^{exposed under} the conditions of an accelerating voltage of 60 keV and a dose amount of 1 × 10 ¹⁶ cm ^-2. By implanting arsenic ions, a high concentration n-type emitter layer 27 and collector layer 2 are formed.
8 are formed simultaneously (FIG. 4 (g)).

Then, after removing the resist 26, finally, a 2000 A CVD silicon film 29 is deposited, and after opening a contact, metal electrodes 30, 31, 32 of the emitter, base, and collector are formed, respectively. The heterojunction bipolar transistor shown in Fig. 1 is completed (Fig. 4
(H)). The above is one embodiment for realizing the structure of the present invention.

[0021]

As described above in detail, according to the present invention, the number of electrons directly injected from the high-concentration emitter layer into the high-concentration external base region is reduced, and the electric field in the SiGe alloy is reduced. Thereby, the number of electrons reaching the collector layer can be increased, the emitter injection efficiency can be improved, and the direct current amplification factor can be expected to be significantly improved. Further, the S in the intrinsic base layer is formed only by a simple step of ion implantation using the nitride film left on the sidewall of the CVD silicon oxide film deposited on the SOI layer as a mask.
The Ge content in i can be controlled. This makes it possible to increase the impurity concentration in the central portion of the base layer by reducing the band gap in the central portion of the base layer and reduce the base resistance. It is possible to suppress the occurrence of the concentration effect and achieve improvement in high-speed performance, and it is possible to realize an ultra-small and high-performance heterojunction bipolar transistor.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a structure of a bipolar transistor according to an embodiment of the present invention.

2A to 2D are process cross-sectional views showing a method of manufacturing the bipolar transistor shown in FIG.

FIG. 3 is a process cross-sectional view showing a process following that of FIG. 2;

FIG. 4 is a process cross-sectional view showing a process following that of FIG. 3;

5 is a structural plan view including the cross section of FIG. 3D and a cross sectional view in a direction perpendicular to the cross section of FIG.

FIG. 6 is a structural cross-sectional view showing a conventional SOI lateral bipolar transistor.

FIG. 7 is a structural plan view showing a conventional SOI lateral bipolar transistor.

FIG. 8 shows collector current dependence of DC amplification factor in a conventional SOI lateral bipolar transistor.

[Explanation of symbols]

11 n ^- Silicon substrate 12, 13, 17, 18 Silicon thermal oxide film 14, 16 Polysilicon film 15, 21, 24 Silicon nitride film 19, 23, 29 CVD silicon oxide film 20 Low concentration n-type layer 22 p-type layer 25 p-type Silicon-germanium alloy layer 26 Resist 27 High-concentration n-type emitter layer 28 High-concentration n-type collector layer 30 Emitter metal electrode 31 Base metal electrode 32 Collector metal electrode

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type emitter layer, a second conductivity type base layer and a first conductivity type collector layer in a single crystal semiconductor layer on an insulating film embedded in the semiconductor substrate. The emitter layer of the first conductivity type is arranged in a direction parallel to the surface and is covered with an insulating film except for the surface facing the collector layer of the first conductivity type. The two-conductivity-type base layer is formed by using a semiconductor material having a bandgap narrower than those of the first-conductivity-type emitter layer and the collector layer, and the second-conductivity-type base layer has a central bandgap at an outer peripheral portion. A heterojunction bipolar transistor characterized by having a structure narrower than that.