JPH0590249A - Method of forming surface protective film of semiconductor device - Google Patents
Method of forming surface protective film of semiconductor deviceInfo
- Publication number
- JPH0590249A JPH0590249A JP3250781A JP25078191A JPH0590249A JP H0590249 A JPH0590249 A JP H0590249A JP 3250781 A JP3250781 A JP 3250781A JP 25078191 A JP25078191 A JP 25078191A JP H0590249 A JPH0590249 A JP H0590249A
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- Prior art keywords
- film
- temperature
- silicon oxide
- protective film
- dried
- Prior art date
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- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、表面保護膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a surface protective film.
【０００２】[0002]
【従来の技術】従来、半導体装置の表面保護膜は、以下
の方法によって形成されていた。すなわち、図５に示す
ように、Ｐ型シリコンなどの半導体基板２０１に、Ｎ+
型のソース２０２，ドレイン２０３，フィールド絶縁膜
（ＳｉＯ2 ）２０４，多結晶Ｓｉゲート２０５，多結晶
Ｓｉから成る蓄積容量電極２０６，ＰＳＧ膜２０７，ア
ルミニウム電極配線２０８ａ，２０８ｂが形成されたＭ
ＯＳ型トランジスタメモリセル上に、モノシラン（Ｓｉ
Ｈ4 ）及び、亜酸化窒素（Ｎ2 Ｏ）を用いてプラズマＣ
ＶＤ法により第１層目の酸化シリコン膜２０９を３００
〜４００℃程度の温度で厚さ約１００ｎｍ程度成長させ
る。次いで、モノシラン（ＳｉＨ4 ）及びアンモニア
（ＮＨ3 ）を用いて、プラズマＣＶＤ法により第２層目
の窒化シリコン膜２１０を３００〜４００℃程度の温度
で厚さ約５００ｎｍ程度成長させていた。2. Description of the Related Art Conventionally, the surface protective film of a semiconductor device has been formed by the following method. That is, as shown in FIG. 5, N + is formed on a semiconductor substrate 201 such as P-type silicon.
Type source 202, drain 203, field insulating film (SiO 2 ) 204, polycrystalline Si gate 205, storage capacitor electrode 206 made of polycrystalline Si, PSG film 207, and aluminum electrode wirings 208a and 208b.
On the OS-type transistor memory cell, monosilane (Si
H 4 ) and nitrous oxide (N 2 O) for plasma C
The silicon oxide film 209 of the first layer is formed to 300 by the VD method.
The thickness is grown to about 100 nm at a temperature of about 400 ° C. Next, using monosilane (SiH 4 ) and ammonia (NH 3 ), the second layer silicon nitride film 210 was grown at a temperature of about 300 to 400 ° C. by a plasma CVD method to a thickness of about 500 nm.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
表面保護膜の形成方法は、以下の問題点があった。すな
わち、アルミニウム電極配線の微細化に伴なって、図６
に概略的に示すように、複数本のアルミニウム電極配線
３０８が近接して配置されている部分では、ＣＶＤ法に
より保護膜３１１（酸化シリコン膜２０９，窒化シリコ
ン膜２１０を総称していう）を形成するときの基板表面
の凹凸が激しいので、保護膜３１１はオーバハング形状
を呈するため、半導体チップを樹脂封止した場合、封止
樹脂の熱応力によるアルミニウム電極配線の断線あるい
は保護膜に亀裂が生じてしまうという問題がある。However, the conventional method for forming a surface protective film has the following problems. That is, as the aluminum electrode wiring is miniaturized, as shown in FIG.
As schematically shown in FIG. 3, a protective film 311 (generically referred to as a silicon oxide film 209 and a silicon nitride film 210) is formed by a CVD method in a portion where a plurality of aluminum electrode wirings 308 are arranged close to each other. At this time, since the unevenness of the substrate surface is severe, the protective film 311 has an overhang shape. Therefore, when the semiconductor chip is resin-sealed, the aluminum electrode wiring is broken or the protective film is cracked due to thermal stress of the sealing resin. There is a problem.
【０００４】さらに３００℃以上の温度でアルミニウム
電極配線上に保護膜を形成するので、アルミニウム電極
配線表面にヒロックとよばれる突起が発生し、半導体装
置の製造歩留り，信頼性を著しく低下させてしまうとい
う問題も有している。Further, since the protective film is formed on the aluminum electrode wiring at a temperature of 300 ° C. or higher, protrusions called hillocks are generated on the surface of the aluminum electrode wiring, and the manufacturing yield and reliability of the semiconductor device are significantly reduced. I also have the problem.
【０００５】また、高温環境での連続動作を行う場合に
は、保護膜の熱応力によって、アルミニウム電極配線の
断線が加速され、あるいは、保護膜に生じた亀裂からの
水分の浸入によるアルミニウム電極配線の腐食が発生
し、著しく信頼性が低下してしまい実用に供し得ないも
のとなってきている。When performing continuous operation in a high temperature environment, the thermal stress of the protective film accelerates the disconnection of the aluminum electrode wiring, or the aluminum electrode wiring is caused by the infiltration of water from the cracks formed in the protective film. Corrosion occurs and the reliability is remarkably deteriorated, and it cannot be put to practical use.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置の表
面保護膜の形成方法は、最上層配線層が形成された半導
体チップ上に、第１の酸化シリコン膜を高高２５０℃の
温度で形成する工程と、化学式Ｓｉ（ＯＨ）4 ，Ｓｉ
（ＯＲ）4 ，又はＲn −Ｓｉ（ＯＲ）4-n （Ｒ：アルキ
ル基，ｎ：１〜３の整数）のうち少くとも１つから形成
したアルコール溶液、すなわちＳＯＧ用塗布液を塗布し
たのち高高２００℃の温度の熱処理により乾燥し、アル
コキシフルオロシラン（化学式Ｆm −Ｓｉ（Ｏ
Ｒ）4-m ，Ｒ：アルキル基，ｍ：１〜３の整数）を主成
分とする蒸気にさらしたのち、高高２５０℃の温度で熱
処理して酸化シリコン系のガラス膜を形成する工程と、
続いて、プラズマ化学気相成長法により、高高２５０℃
の温度で絶縁膜を形成する工程とを有するというもので
ある。According to a method of forming a surface protective film of a semiconductor device of the present invention, a first silicon oxide film is formed on a semiconductor chip having an uppermost wiring layer formed thereon at a high temperature of 250 ° C. Forming process and chemical formula Si (OH) 4 , Si
An alcohol solution formed from at least one of (OR) 4 or R n —Si (OR) 4-n (R: alkyl group, n: an integer of 1 to 3), that is, an SOG coating liquid was applied. After that, it is dried by heat treatment at a high temperature of 200 ° C. to obtain an alkoxyfluorosilane (chemical formula F m —Si (O
R) 4-m , R: alkyl group, m: an integer of 1 to 3) exposed to vapor, and then heat-treated at a temperature of 250 ° C. to form a silicon oxide glass film. When,
Subsequently, the plasma chemical vapor deposition method was used to increase the high temperature to 250 ° C.
And a step of forming an insulating film at the temperature.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００８】図１（ａ）〜（ｄ）は、本発明の一実施例
である表面保護膜の形成方法の説明に使用する工程順断
面図である。1A to 1D are cross-sectional views in order of steps, which are used for explaining a method for forming a surface protective film which is an embodiment of the present invention.
【０００９】まず図１（ａ）に示すように、図示しない
トランジスタなどの素子が形成された半導体基板１０１
上に厚さ約０．８μｍのＰＳＧ膜１０２を形成する。こ
のような半導体チップ上に厚さ約０．８μｍのアルミニ
ウム電極配線１０３を形成する。次に、図１（ｂ）に示
すようにプラズマ化学気相成長法により、厚さ約０．４
μｍの酸化シリコン膜１０４を２５０℃の温度で形成す
る。Ｓｉ（ＯＨ）4 を１０重量％含むエチルアルコール
を４０００ｒｐｍの回転速度でスピン塗布した後、１０
０℃の温度に保たれたホットプレート上で６０秒間ベー
クを行ない塗布膜を形成する。次に図１（ｃ）に示すよ
うに、トリエトキシフルオロシラン（化学式Ｆ−Ｓｉ
（ＯＣ2 Ｈ5 ）3）の蒸気（大気圧）に室温（２５℃）
で３０分間曝らした後、２５０℃で６０分間熱処理を行
い厚さ約０．４μｍのフッ素含有酸化シリコン膜１１２
を形成する。First, as shown in FIG. 1A, a semiconductor substrate 101 on which elements such as transistors (not shown) are formed.
A PSG film 102 having a thickness of about 0.8 μm is formed on top. An aluminum electrode wiring 103 having a thickness of about 0.8 μm is formed on such a semiconductor chip. Next, as shown in FIG. 1B, a thickness of about 0.4 is formed by plasma enhanced chemical vapor deposition.
A silicon oxide film 104 of μm is formed at a temperature of 250 ° C. Ethyl alcohol containing 10% by weight of Si (OH) 4 was spin-coated at a rotation speed of 4000 rpm, and then 10
A coating film is formed by baking for 60 seconds on a hot plate kept at a temperature of 0 ° C. Next, as shown in FIG. 1C, triethoxyfluorosilane (chemical formula F-Si
Room temperature (25 ° C) in (OC 2 H 5 ) 3 ) vapor (atmospheric pressure)
Exposed for 30 minutes, and then heat-treated at 250 ° C. for 60 minutes to give a fluorine-containing silicon oxide film 112 having a thickness of about 0.4 μm.
To form.
【００１０】このようにして形成したフッ素含有酸化シ
リコン膜１１２のＦＴ−ＩＲスペクトルを図２に曲線Ａ
として示す。曲線Ｂはトリエトキシフルオロシラン蒸気
処理を施さないＳＯＧ膜のスペクトルである。波数約３
４００ｃｍ-1付近のＯＨ基に起因する吸収ピークはほぼ
完全に消失し、含有水分量の少ない良質な酸化シリコン
系の絶縁膜が得られることが判る。The FT-IR spectrum of the fluorine-containing silicon oxide film 112 thus formed is shown in FIG.
Show as. Curve B is the spectrum of the SOG film without the triethoxyfluorosilane vapor treatment. Wave number about 3
It can be seen that the absorption peak due to the OH group near 400 cm -1 disappeared almost completely, and a high-quality silicon oxide-based insulating film having a small water content was obtained.
【００１１】この後、図１（ｄ）に示すようにプラズマ
化学気相成長法によって、厚さ約０．５μｍの窒化シリ
コン膜１０６を２５０℃の温度で形成する。最後に、公
知のフォトエッチング技術を用いて、図示しないアルミ
ニウムパッド上に開孔を形成する。Thereafter, as shown in FIG. 1D, a silicon nitride film 106 having a thickness of about 0.5 μm is formed at a temperature of 250 ° C. by plasma chemical vapor deposition. Finally, a well-known photo-etching technique is used to form an opening on the aluminum pad (not shown).
【００１２】以上の方形で形成した表面保護膜は、亀裂
の発生は全くなく、かつ、表面の平坦性は充分なもので
あった。The surface protective film formed in the above-mentioned rectangular shape had no cracks at all and had a sufficient surface flatness.
【００１３】さらに以上の方法で形成した表面保護膜の
信頼性を調べるために、樹脂封止型のパッケージ中に組
込んで、飽和蒸気圧が２．１気圧で１２５℃の温度での
耐湿性試験、また、１２５℃〜２５℃〜−６５℃の温度
サイクル試験を行ったところ、それぞれ５００時間，３
００サイクル後に、不良の発生は全くないものであっ
た。Further, in order to investigate the reliability of the surface protective film formed by the above method, the surface protective film was incorporated in a resin-sealed package, and the humidity resistance at a saturated vapor pressure of 2.1 atm and a temperature of 125 ° C. When a test and a temperature cycle test of 125 ° C. to 25 ° C. to −65 ° C. were performed, 500 hours and 3 hours, respectively.
After 00 cycles, no defects were generated.
【００１４】また、アルミニウム電極配線形成後に、２
５０℃以上の温度を経ることはないのでヒロックの発生
はない。After the aluminum electrode wiring is formed, 2
No hillocks are generated because the temperature does not exceed 50 ° C.
【００１５】以上、Ｓｉ（ＯＨ）4 から形成したＳＯＧ
用塗布液と、トリエトキシフルオロシランとを用いた例
について説明した。Above, SOG formed from Si (OH) 4
An example using the coating liquid for tributary and triethoxyfluorosilane has been described.
【００１６】ＳＯＧ用塗布液としては、その外にＳｉ
（ＯＲ）4 ，（Ｒはアルキル基）やＲn −Ｓｉ（ＯＲ）
4-n （Ｒはアルキル基、ｎは１，２または３）などのア
ルコキシシラン化合物を使用してもほぼ同様の結果を得
ることができる。図３にＣＨ3 −Ｓｉ（ＯＣ2 Ｈ5 ）3
を用い、２５℃で３０分間トリエトキシフルオロシラン
の蒸気に曝したのち２５０℃，３０分の熱処理をしたも
ののＦＴ−ＩＲスペクトル（曲線Ａ）を、トリエトキシ
フルオロシランの蒸気に曝すことなく熱処理をしたもの
（曲線Ｂ）と比較して示す。やはり、含有水分量の少な
い良質の酸化シリコン系の絶縁膜が得られることが判
る。As the SOG coating liquid, Si
(OR) 4 , (R is an alkyl group) and R n —Si (OR)
Almost the same result can be obtained by using an alkoxysilane compound such as 4-n (R is an alkyl group, n is 1, 2 or 3). In FIG. 3, CH 3 —Si (OC 2 H 5 ) 3
FT-IR spectrum (curve A) of the product after being exposed to the vapor of triethoxyfluorosilane for 30 minutes at 25 ° C. and then subjected to the heat treatment at 250 ° C. for 30 minutes without being exposed to the vapor of triethoxyfluorosilane. It shows in comparison with what was done (curve B). Again, it can be seen that a high-quality silicon oxide-based insulating film having a low water content can be obtained.
【００１７】また、図４にその他のアルコキシフルオロ
シランを用いたものについてＦＴ−ＩＲスペクトルを示
す。曲線Ａ，Ｂ，Ｃはそれぞれトリメトキシフルオロシ
ラン（Ｆ−Ｓｉ（ＯＣＨ3 ）3 ）、トリノルマルブトキ
シフルオロシラン（Ｆ−Ｓｉ（ｎ−ＯＣ3 Ｈ7 ）3 ）、
トリイソブトキシフルオロシラン（Ｆ−Ｓｉ（ｉ−ＯＣ
3 Ｈ7 ）3 ）を用いたもののＦＴ−ＩＲスペクトルであ
る。これらは前述した一実施例において、アルコキシフ
ルオロシランの種類を変えたもので、他の条件は同じで
ある。一般に、Ｆ−Ｓｉ（ＯＲ）3 ，Ｆ2 −Ｓｉ（Ｏ
Ｒ）2 ，Ｆ3 −Ｓｉ（ＯＲ）などを用いることができ
る。In addition, FIG. 4 shows an FT-IR spectrum of the one using other alkoxyfluorosilane. Curve A, B, C, respectively trimethoxy fluorosilane (F-Si (OCH 3) 3), tri-n-butoxy-fluoro silane (F-Si (n-OC 3 H 7) 3),
Triisobutoxyfluorosilane (F-Si (i-OC
3 H 7) 3) is a FT-IR spectrum but was used. These are obtained by changing the kind of the alkoxyfluorosilane in the above-mentioned embodiment, and the other conditions are the same. In general, F-Si (OR) 3 , F 2 -Si (O
R) 2, F 3, etc. -Si (OR) can be used.
【００１８】すなわち、前述したＳＯＧ用塗布液を塗布
し、乾燥し、室温においてアルコキシフルオロシランの
蒸気に曝すことによって縮合反応が起きて、一部Ｆを含
む酸化シリコン系ガラス膜が形成できる。従って従来の
ＳＯＧ膜形成のように、２５０℃以上の高温焼成は不要
となる。That is, the above SOG coating liquid is applied, dried, and exposed to the vapor of alkoxyfluorosilane at room temperature to cause a condensation reaction, whereby a silicon oxide glass film containing a part of F can be formed. Therefore, unlike the conventional SOG film formation, high temperature firing at 250 ° C. or higher is not necessary.
【００１９】なお、以上の説明において、絶縁膜の厚
さ，配線材料，成膜条件等は、任意に選択することがで
きるものである。さらに、本発明に基づいて形成した表
面保護膜上に、ポリイド膜等の樹脂膜を形成することも
可能である。In the above description, the thickness of the insulating film, the wiring material, the film forming conditions, etc. can be arbitrarily selected. Further, it is possible to form a resin film such as a polyidic film on the surface protective film formed according to the present invention.
【００２０】[0020]
【発明の効果】以上説明したように、本発明は、ＳＯＧ
膜形成用の塗布溶液を塗布して乾燥したのち、トリエト
キシフルオロシランの蒸気に曝らし、２５０℃以下の温
度で熱処理することによってシリコン系のガラス膜を形
成するので、ＳＯＧ膜の低温形成が可能となると同時
に、表面の平坦化を行っていることから、保護膜に亀裂
が生じたり、アルミニウム電極配線が断線したりするこ
とはない。As described above, according to the present invention, the SOG
After applying a coating solution for forming a film and drying it, it is exposed to vapor of triethoxyfluorosilane and heat-treated at a temperature of 250 ° C. or less to form a silicon-based glass film, so that the SOG film can be formed at low temperature. At the same time, since the surface is flattened, the protective film is not cracked or the aluminum electrode wiring is not broken.
【００２１】また、アルミニウム電極配線形成後に、２
５０℃以下の温度で保護膜を形成するので、アルミニウ
ム電極配線にヒロックが形成されることはないため、製
造歩留り、信頼性の高い半導体装置の製造が可能とな
る。After forming the aluminum electrode wiring, 2
Since the protective film is formed at a temperature of 50 ° C. or lower, hillocks are not formed on the aluminum electrode wiring, and therefore a semiconductor device with high manufacturing yield and high reliability can be manufactured.
【００２２】さらに、封止樹脂の熱応力に対しても、亀
裂の発生あるいは、アルミニウム電極配線の断線が全く
ない良好な表面保護膜が２５０℃以下の低温で簡便に得
られるという効果がある。Further, even with respect to the thermal stress of the sealing resin, there is an effect that a good surface protective film having no cracks or no breakage of aluminum electrode wiring can be easily obtained at a low temperature of 250 ° C. or lower.
【図１】本発明の一実施例を説明するため（ａ）〜
（ｄ）に分図して示す工程順断面図である。FIG. 1A is a view for explaining an embodiment of the present invention.
It is a process order sectional view divided and shown in (d).
【図２】本発明の一実施例の説明に使用する特性図であ
る。FIG. 2 is a characteristic diagram used to describe one embodiment of the present invention.
【図３】本発明の一実施例の説明に使用する特性図であ
る。FIG. 3 is a characteristic diagram used to describe one embodiment of the present invention.
【図４】本発明の一実施例の説明に使用する特性図であ
る。FIG. 4 is a characteristic diagram used to describe one embodiment of the present invention.
【図５】従来の技術の説明に使用するＭＯＳ型トランジ
スタセルの断面図である。FIG. 5 is a cross-sectional view of a MOS type transistor cell used for explaining a conventional technique.
【図６】従来の技術の説明に使用する半導体チップの断
面図である。FIG. 6 is a cross-sectional view of a semiconductor chip used for explaining a conventional technique.
１０１，２０１，３０１ 半導体基板 ２０２ ソース ２０３ ドレイン ２０４ フィールド絶縁膜 ２０５ 多結晶シリコンゲート ２０６ 多結晶シリコン蓄積電極 １０７，２０７，３０７ ＰＳＧ膜 １０８，２０８ａ，２０８ｂ，３０８ アルミニウム
電極配線 １０９，２０９ 酸化シリコン膜 １１０，２１０ 窒化シリコン膜 ３１１ ＣＶＤ法による保護膜 １１２ フッ素含有酸化シリコン膜101, 201, 301 Semiconductor substrate 202 Source 203 Drain 204 Field insulating film 205 Polycrystalline silicon gate 206 Polycrystalline silicon storage electrode 107, 207, 307 PSG film 108, 208a, 208b, 308 Aluminum electrode wiring 109, 209 Silicon oxide film 110 , 210 silicon nitride film 311 protective film by CVD method 112 fluorine-containing silicon oxide film
Claims (2)
上に、第１の酸化シリコン膜を高高２５０℃の温度で形
成する工程と、化学式Ｓｉ（ＯＨ）4 ，Ｓｉ（Ｏ
Ｒ）4 ，又はＲn −Ｓｉ（ＯＲ）4-n （Ｒ：アルキル
基，ｎ：１〜３の整数）のうち少くとも１つから形成し
たアルコール溶液、すなわちＳＯＧ用塗布液を塗布した
のち高高２００℃の温度の熱処理により乾燥し、アルコ
キシフルオロシラン（化学式Ｆm −Ｓｉ（ＯＲ）4-m ，
Ｒ：アルキル基，ｍ：１〜３の整数）を主成分とする蒸
気にさらしたのち、高高２５０℃の温度で熱処理して酸
化シリコン系のガラス膜を形成する工程と、続いて、プ
ラズマ化学気相成長法により、高高２５０℃の温度で絶
縁膜を形成する工程とを有することを特徴とする半導体
装置の表面保護膜の形成方法。1. A step of forming a first silicon oxide film at a high and high temperature of 250 ° C. on a semiconductor chip on which an uppermost wiring layer is formed, and chemical formulas Si (OH) 4 , Si (O).
R) 4, or R n -Si (OR) 4- n (R: alkyl group, n: an alcohol solution formed from one at least of the integer of 1 to 3), i.e. after the application of the SOG coating solution It is dried by heat treatment at a high temperature of 200 ° C. to give an alkoxyfluorosilane (chemical formula F m —Si (OR) 4-m ,
R: an alkyl group, m: an integer of 1 to 3) as a main component, and then heat-treating at a high and high temperature of 250 ° C. to form a silicon oxide glass film, followed by plasma. And a step of forming an insulating film at a high temperature of 250 ° C. by a chemical vapor deposition method.
シフルオロシランである請求項１記載の半導体装置の表
面保護膜の形成方法。2. The method for forming a surface protective film of a semiconductor device according to claim 1, wherein the alkoxyfluorosilane is triethoxyfluorosilane.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25078191A JP2737478B2 (en) | 1991-09-30 | 1991-09-30 | Method for forming surface protection film of semiconductor device |
| KR1019920016642A KR960006961B1 (en) | 1991-09-13 | 1992-09-09 | Method for forming interconnect structure, insulating films and surface protective films of semiconductor device |
| US07/943,069 US5405805A (en) | 1991-09-13 | 1992-09-10 | Method for forming interconnect structure, insulating films and surface protective films of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25078191A JP2737478B2 (en) | 1991-09-30 | 1991-09-30 | Method for forming surface protection film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0590249A true JPH0590249A (en) | 1993-04-09 |
| JP2737478B2 JP2737478B2 (en) | 1998-04-08 |
Family
ID=17212954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25078191A Expired - Lifetime JP2737478B2 (en) | 1991-09-13 | 1991-09-30 | Method for forming surface protection film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737478B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274779A (en) * | 1988-09-10 | 1990-03-14 | Toyo Sash Co Ltd | Door with curtain |
| EP0599730A2 (en) * | 1992-11-24 | 1994-06-01 | Sumitomo Chemical Company, Limited | Semiconductor device and method of producing the same |
| US5444023A (en) * | 1993-01-11 | 1995-08-22 | Nec Corporation | Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas |
| US5753564A (en) * | 1992-11-24 | 1998-05-19 | Sumitomo Metal Industries, Ltd. | Method for forming a thin film of a silicon oxide on a silicon substrate, by BCR plasma |
| US6287956B2 (en) * | 1997-04-25 | 2001-09-11 | Nec Corporation | Multilevel interconnecting structure in semiconductor device and method of forming the same |
| JP2001267315A (en) * | 1999-12-23 | 2001-09-28 | Applied Materials Inc | In situ deposition and integration of silicon nitride in high density plasm reactor |
| KR100345663B1 (en) * | 1995-04-11 | 2002-10-30 | 주식회사 하이닉스반도체 | A method for inter-dielectric planarization of film in semiconductor device |
| JP2002329720A (en) * | 2001-04-27 | 2002-11-15 | Samco International Inc | Protective film for device and its manufacturing method |
| US6514884B2 (en) | 1998-02-06 | 2003-02-04 | Semiconductor Process Laboratory Co., Ltd. | Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same |
| KR100312377B1 (en) * | 1995-06-28 | 2003-08-06 | 주식회사 하이닉스반도체 | Method for manufacturing passivation layer of semiconductor device |
-
1991
- 1991-09-30 JP JP25078191A patent/JP2737478B2/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274779A (en) * | 1988-09-10 | 1990-03-14 | Toyo Sash Co Ltd | Door with curtain |
| EP0599730A2 (en) * | 1992-11-24 | 1994-06-01 | Sumitomo Chemical Company, Limited | Semiconductor device and method of producing the same |
| EP0599730A3 (en) * | 1992-11-24 | 1995-02-15 | Sumitomo Metal Ind | Semiconductor device and method of producing the same. |
| US5753564A (en) * | 1992-11-24 | 1998-05-19 | Sumitomo Metal Industries, Ltd. | Method for forming a thin film of a silicon oxide on a silicon substrate, by BCR plasma |
| US5444023A (en) * | 1993-01-11 | 1995-08-22 | Nec Corporation | Method of fabricating a semiconductor device having a multilayer wiring structure and using a fluorine compound-containing gas |
| KR100345663B1 (en) * | 1995-04-11 | 2002-10-30 | 주식회사 하이닉스반도체 | A method for inter-dielectric planarization of film in semiconductor device |
| KR100312377B1 (en) * | 1995-06-28 | 2003-08-06 | 주식회사 하이닉스반도체 | Method for manufacturing passivation layer of semiconductor device |
| US6287956B2 (en) * | 1997-04-25 | 2001-09-11 | Nec Corporation | Multilevel interconnecting structure in semiconductor device and method of forming the same |
| US6514884B2 (en) | 1998-02-06 | 2003-02-04 | Semiconductor Process Laboratory Co., Ltd. | Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same |
| JP2001267315A (en) * | 1999-12-23 | 2001-09-28 | Applied Materials Inc | In situ deposition and integration of silicon nitride in high density plasm reactor |
| JP2002329720A (en) * | 2001-04-27 | 2002-11-15 | Samco International Inc | Protective film for device and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| JP2737478B2 (en) | 1998-04-08 |
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