JPH0589034A - Bus control circuit - Google Patents

Abstract

PURPOSE:To provide the bus control circuit which can keep the number of times for acquiring the right of bus use for each bus master at a fixed rate in the state of always accepting a bus use request signal without limiting the accepting of the signal. CONSTITUTION:According to a value stored in an initial counter value storage circuit 61, a fixed gradient is applied to the frequency of acquiring a bus use permit signal of each bus master, the values of respective bus priority registers 11-15 are controlled according to the number of times for applying the bus use permit signal, and the priority for the right of bus use is increased/decreased so as to apply the bus use permit signal to each bus master in the state of always accepting the bus use request signal while keeping the fixed rate. Thus, the number of times for acquiring the right of bus use for each bus master can be kept at the fixed rate while always accepting the bus use request signal without limiting the accepting of the signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit for a system in which a plurality of bus masters share a set of buses, and more particularly, to use a bus for a specific bus master in response to a bus use request from a plurality of bus masters. The present invention relates to a bus control circuit that manages a bus use right that gives permission.

[0002]

2. Description of the Related Art Conventionally, in this type of bus control circuit, the priority of obtaining the bus use right for each bus master is determined by hardware, and the bus use right is given to a bus master having a low priority. If multiple bus use request signals are received each time, the bus use right is kept waiting until the next bus use request signal is given to all the received bus use request signals. I was allocating. In addition, since the acquisition priority is determined by hardware, when multiple bus masters simultaneously make bus use requests, the bus use permission signal is always output to the bus master with a higher priority. It was like this. Furthermore, if there is a bus master that wants to obtain the bus use permission signal with special priority several times during a group of bus use request processing, a counter that counts the number of times the bus use permission signal is given is provided, and the counter is a hardware The bus use request signal is accepted only when the number of times is within the predetermined number.

[0003]

In the above-mentioned conventional bus control circuit, the priority of the bus use right for each bus master is determined by hardware, and a bus use request signal is simultaneously input from a plurality of bus masters. In this case, the bus use permission signal is always output to the high-priority bus master determined by hardware. Therefore, if the bus use request signal is accepted indefinitely, the priority order The bus use permission signals to the bus masters with high priority increase, and the bus use permission is not given to the bus masters with lower priority. Therefore, when the bus use request signals are received from multiple bus masters, all the received bus use requests are accepted. However, there is a problem in that the bus use permission signal must be given to the . If there is a bus master that wants to obtain the bus use permission signal several times during a group of bus use request processing and a counter that holds the number of times the bus use permission signal is obtained is provided, the group of bus use request processing is in progress. Since the number of times the bus use permission signal is accepted is fixed, the frequency of bus acquisition is uneven, and the frequency of bus acquisition is determined by hardware, allocation of the optimum bus usage right for the program to be executed There was a problem that I could not.

The present invention has been made in view of the above problems, and does not limit the acceptance of a bus use request signal, and always keeps the acceptance state of each bus master at a constant ratio. It is an object of the present invention to provide a bus control circuit capable of performing the above operation.

[0005]

In order to achieve the above object, the bus control circuit of the present invention has a bus control circuit in which a plurality of bus masters share a set of buses and transfers data. When the bus priority register that exists and indicates the priority of each bus master and the bus priority indicated by the bus priority register of the bus master is high, the value is updated when the bus usage right is assigned to the own bus master. If the bus priority is low, the priority control counter that updates the value when the bus mastership is assigned to a bus master other than itself and the bus mastership is assigned to the bus master other than itself with a high bus priority. A bus usage right waiting counter whose value is updated when the priority is given, and a priority value counter and an initial value to be set in the bus usage right waiting counter are stored in advance. The initial value storage circuit, the priority register control circuit for controlling the bus priority register according to the contents of the priority control counter, and the number of times the bus usage right could not be acquired depending on the contents of the bus usage right waiting counter. When the value exceeds the value, the bus use right wait judgment circuit for giving priority to the bus use right to other bus masters, the bus priority register and the bus use right wait judgment circuit, and the bus use request signal from each bus master A bus use request arbitration circuit that determines a bus master that gives a bus use permission signal, and a counter control circuit that controls updating of a priority control counter and a bus use right wait counter by the bus use permission signal are provided. The value stored in the value storage circuit gives a certain slope to the acquisition frequency of the bus use permission signal of each bus master. By controlling the value of each bus priority register according to the given number of bus use permission signals and raising or lowering the priority of the bus use right, the bus use request signal is always accepted to each bus master. The bus use permission signal is given while maintaining a constant ratio, and preferably the counter initial value storage circuit is made accessible by the processor so that the contents of the initial value storage circuit are set by the execution program so that the execution program The configuration is such that the frequency of bus right acquisition can be changed.

[0006]

With the value stored in advance in the counter initial value circuit, the bus mastership acquisition frequency of each bus master is inclined, and the priority of the bus mastership right is set according to the number of bus mastership acquisition times of each bus master. Move it up and down. As a result, the number of times the bus mastership is acquired by each bus master is maintained at a constant ratio without limiting the acceptance of the bus use request signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a bus control circuit according to an embodiment of the present invention. The bus control circuit includes bus priority registers 11 to 15, priority control counters 21 to 25, subtraction circuits 31 to 35, bus usage right waiting counters 41 to 45, subtraction circuits 51 to 55, and a counter initial counter. It is composed of a value storage circuit 61, a priority register control circuit 62, a bus use right wait judgment circuit 63, a bus use request arbitration circuit 64, and a counter control circuit 65.

The bus priority registers 11 to 15 are 1-bit registers that exist for each bus master and indicate the priority of the bus master. The priority control counters 21 to 25 are decremented when the bus master registers of the bus priority registers 11 to 15 have high priority, and are subtracted when the bus master receives the bus use permission signal S2. In this case, when the bus master other than itself obtains the bus use permission signal S2, it is subtracted. The subtraction circuits 31 to 35 are circuits for subtracting the priority control counters 21 to 25. Bus right-of-use waiting counter 41
To 45, when one of the bus priority registers 11 to 15 of its own bus master has high priority,
It is subtracted when a bus master other than itself receives the bus use permission signal S2. The subtraction circuits 51 to 55 subtract the bus usage right waiting counters 41 to 45.

The counter initial value storage circuit 61 has a priority control counter 21 when the contents of the bus priority registers 11 to 15 are changed, or when its own bus master receives the bus use permission signal S2 in the case of low priority. ~ 25
And initial values set in the bus use right waiting counters 41 to 45 are stored in advance. Priority register control circuit 62
Performs control to change the contents of the bus priority registers 11 to 15 when the contents of the priority control counters 21 to 25 become 0. The bus use right wait determination circuit 63 determines that the contents of the bus use right wait counters 41 to 45 have become "0", and gives the bus use permission signal S2 in preference to other bus masters.

The bus use request arbitration circuit 64 currently uses the contents of the bus priority registers 11 to 15 of each bus master and the information from the bus use right wait judgment circuit 63 in response to the bus use request signal S1 input from each bus master. Control is performed to give the bus use permission signal S2 to the bus master having the highest priority. The counter control circuit 65 controls subtraction of the priority control counters 21 to 25 and the bus use right waiting counters 41 to 45 from the bus use permission signal S2 output from the bus use request arbitration circuit 64. Further, in the bus control circuit of this embodiment, the counter initial value storage circuit 61 is made readable and writable, and is connected to the address bus 71 and the data bus 72 so that it can be accessed by the main CPU.

Next, the operation of the bus control circuit configured as described above will be described. Now, the counter initial value storage circuit 61
The initial values of the priority control counters 21 to 25 and the bus use right waiting counters 41 to 45 stored in advance in FIG.
It is assumed that the value is shown in. That is, the initial values of the priority control counters 21 to 25 at the time of high priority are “4”, “2”, “1”, “2”, “,” respectively.
2 ", the initial values at low priority are"
2 "," 4 "," 3 "," 5 "," 4 ",
The initial values of the bus usage right waiting counters 41 to 45 are "2", "3", "4", "6", and "5", respectively.

The bus master A corresponds to the bus priority register 11, the priority control counter 21, and the bus right-of-use waiting counter 41. The bus master B corresponds to the bus priority register 12 and the priority. The bus priority register 13, the priority control counter 23, and the bus usage right waiting counter 43, which correspond to the bus master C.
The bus priority register 1 corresponds to the bus master D.
4, a priority control counter 24, and a bus right-of-use waiting counter 44. Corresponding to the bus master N below are the bus priority register 15, the priority control counter 25, and the bus right-of-use waiting counter 45. The bus acquisition priority with the same priority is bus master A> bus master B> bus master C.
> Bus master D >>...> Bus master N

First, the bus priority registers 11 to 15 are set to the high priority state, and the priority control counters 21 to 21 are set.
The initial value at the time of high priority is transferred from the counter initial value storage circuit 61 to 25. Bus right-of-use waiting counter 4
The initial values for the bus use right waiting counters 41 to 45 are transferred to the counters 1 to 45 from the counter initial value storage circuit 61. At this time, the bus use request signal S1 is output from the bus masters B, D, and N (FIG. 3). The outputs of the bus priority registers 11 to 15 all indicate high priority. All the values of the bus usage right waiting counters 41 to 45 are also "
Since it is not 0 ", the bus use right wait judgment circuit 63 indicates that there is no bus master to which the bus use permission signal S2 is assigned with the highest priority.

At this time, the bus use request arbitration circuit 64 outputs 1
The bus use permission signal S2 is output to the bus master B having the highest priority order of the number bus acquisition. The counter control circuit 65 recognizes that the bus use permission signal S2 is given to the bus master B, inputs the value of the priority control counter 22 corresponding to the bus master B to the subtraction circuit 32, and sets the value of the priority control counter 22 to " Change from 2 "to" 1 ". Further, the counter control circuit 65 outputs the bus use request signal S1 but cannot acquire the bus use permission signal S2.
The values of the bus usage right waiting counters 44 and 45 corresponding to the above are input to the subtraction circuits 54 and 55, and the bus usage right waiting counter 4
The value of 4 is changed from "6" to "5", and the value of the bus use right waiting counter 45 is changed from "5" to "4" (FIG. 4).

Assuming that the next bus use request signal S1 is output from the bus masters C, D, N, the values of the bus priority registers 11 to 15 and the output of the bus use right wait judgment circuit 63 (the bus use right wait counters 41 to 41). Since all 45 are not "0", there is no bus master which gives the bus use permission signal S2 with the highest priority), and outputs the bus use permission signal S2 to the bus master C. The counter control circuit 65 recognizes that the bus use permission signal S2 is given to the bus master C, inputs the value of the priority control counter 23 corresponding to the bus master C to the subtraction circuit 33, and sets the value of the priority control counter 23 to "1". Try to change from "0" to "0". Here, the priority register control circuit 62 recognizes that the value of the priority control counter 23 becomes "0", and changes the contents of the bus priority register 13 corresponding to the bus master C from high priority to low priority. Further, the priority control counter 23 stores the initial value of the priority control counter 23 at the time of low priority from the counter initial value storage circuit 61.
3 "is transferred. Also, the values of the bus mastership wait counters 44 and 45 corresponding to the bus masters D and N that could not acquire the bus mastership enable signal S2 are input to the subtraction circuits 54 and 55, and the bus mastership wait counter is input. The values of 44 and 45 are changed (FIG. 5).

Next, assuming that the bus use request signal S1 is output from the bus masters B, C, D and N, the bus use request arbitration circuit 64 causes the bus priority registers 11 to 15 and the bus use right wait judgment circuit 63 to make the bus master. The bus use permission signal S2 is output to B. Counter control circuit 65
Tries to change the value of the priority control counter 22 corresponding to the bus master B that has acquired the bus use permission signal S2 into the subtraction circuit 32 and change it from "1" to "0". Therefore, the priority register control circuit 62 changes the contents of the bus priority register 12 corresponding to the bus master B from high priority to low priority, and the priority control counter 22
The initial value “4” of the priority control counter 22 at the time of low priority is transferred from the counter initial value storage circuit 61. Further, since the bus master C did not allocate the bus use permission signal S2 to itself at low priority, the counter control circuit 65 inputs the value of the priority control counter 23 to the subtraction circuit 33 and changes it from "3" to "2". change. The bus masters D and N, which cannot acquire the bus use permission signal S2 with high priority, change the value of the bus use right wait counter 44 from "4" to "3" and the value of the bus use right wait counter 45 from "3", respectively. Change to "2" (Fig. 6).

Next, when the bus use request signal S1 is output from the bus masters C, D, and N, the bus use request arbitration circuit 64 is the first among the ones showing high priority according to the contents of the bus priority registers 11 to 15. The bus use permission signal S2 is output to the bus master D having a high bus acquisition priority. The counter control circuit 65 inputs the value of the priority control counter 24 corresponding to the bus master D, which has acquired the bus use permission signal S2, to the subtraction circuit 34 to input "2" to "1".
Change to. Further, the value of the bus use right waiting counter 44 corresponding to the bus master D is the counter initial value storage circuit 61 because the bus master D has acquired the bus use permission signal S2.
"6" as the initial value of the bus usage right waiting counter 44
To transfer. Since the bus master C could not acquire the bus use permission signal S2 with low priority, the value of the priority control counter 23 is subtracted from "2" to "1" by the subtraction circuit 33.
Change to. Since the bus master N could not acquire the bus use permission signal S2 with high priority, the value of the bus use right wait counter 45 is subtracted from "2" by the subtraction circuit 55.
Change to 1 "(Fig. 7).

Next, it is assumed that the bus master A, B, C, N outputs the bus use permission signal S2. The bus use request arbitration circuit 64 outputs the bus use permission signal S2 to the bus master A having the highest bus acquisition rank among the bus masters having high priority. The counter control circuit 65 inputs the value of the priority control counter 21 corresponding to the bus master A that has acquired the bus use permission signal S2 to the subtraction circuit 31 and changes it from "4" to "3". The values of the priority control counters 22 and 23 corresponding to the bus masters B and C showing the low priority in the bus priority registers 11 to 15 and unable to acquire the bus use permission signal S2 are input to the subtraction circuits 32 and 33, respectively. , Priority control counter 22
Value is changed from "4" to "3", and the value of the priority control counter 23 is changed from "1" to "0". Here, the priority register control circuit 62 recognizes that the content of the priority control counter 23 is about to be changed to "0", and changes the content of the bus priority register 13 from low priority to high priority. However, the counter control circuit 65 outputs the priority control counter 2 at the time of high priority.
The initial value "1" of 3 is transferred. Further, the value of the bus usage right waiting counter 45 is input to the value subtraction circuit 55 of the bus usage right waiting counter 45 corresponding to the bus master N which has not acquired the bus usage right signal S2 with high priority.
Change from 1 "to" 0 "(Fig. 8).

Next, it is assumed that the bus use request signal S1 is output from the bus masters A, B, C, D and N. Since the value of the bus usage right waiting counter 45 is now “0”, the bus usage right waiting determination circuit 63 recognizes the value of the bus usage right waiting counter 45 and informs the bus usage request arbitration circuit 64 of the bus master. N has the highest priority and requests acquisition of the bus use right. When the bus use request arbitration circuit 64 receives the highest priority request from the bus use right wait determination circuit 63, the bus use request arbitration circuit 64 uses the bus even if there is another bus master with a high priority for acquiring the bus use right. A bus use permission signal S2 is issued to the bus master N requested by the right waiting determination circuit 63.
Is output. The value of the priority control counter 25 corresponding to the bus master N that has acquired the bus use permission signal S2 is input to the subtraction circuit 35 and changed from "2" to "1". Since the bus master N has acquired the bus use permission signal S2, the bus use right wait counter 45 has a counter initial value storage circuit 61.
The initial value "5" of the bus use right waiting counter 45 is transferred to the bus use right waiting counter 45. Further, the bus masters A, C, and D, which have not been able to acquire the bus use permission signal S2 with high priority, subtract the values of the corresponding bus use right waiting counters 41, 43, 44 from the subtraction circuits 51, 53, respectively. 54, the value of the bus usage right waiting counter 41 is changed from "2" to "1", the value of the bus usage right waiting counter 43 is changed from "4" to "3", and the value of the bus usage right waiting counter 44 is changed. Change from "6" to "5". Further, the value of the priority control counter 22 corresponding to the bus master B which could not acquire the bus use permission signal S2 at low priority is input to the subtraction circuit 32.
Change from 3 "to" 2 "(Fig. 9).

Further, as shown in FIG. 10, when the contents of the bus priority registers 11, 14, and 15 corresponding to the bus master which outputs the bus use request signal S1 all indicate low priority, the bus use request arbitration circuit 64. Is a bus master A with a low priority and the highest priority for bus acquisition
To the bus use permission signal S2. The initial value "2" of the priority control counter 21 at the time of low priority of the counter initial value storage circuit 61 is transferred to the priority control counter 21 corresponding to the bus master A which has acquired the bus use permission signal S2. The values of the priority control counters 24 and 25 corresponding to the bus masters D and N that cannot acquire the bus use permission signal S2 are input to the subtraction circuits 34 and 35, respectively, and the value of the priority control counter 24 is from "4" to "4". 3 "
Then, the value of the priority control counter 25 is changed from "3" to "2" (FIG. 11).

In the bus control circuit according to this embodiment,
Since the counter initial value storage circuit 61 is a readable / writable storage device and is connected to the address bus 71 and the data bus 72 that can be accessed by the execution program, the current execution program uses the counter initial value as shown in FIG. Even if it has a value, if you want to execute another program, at the beginning of the new program the main CPU
Therefore, new data can be injected into the counter initial value storage circuit 61 through the address bus 71 and the data bus 72.
As described above, since the content of the counter initial value storage circuit 61 can be changed by the execution program, the frequency of bus right acquisition can be set to an expected ratio by the executed program. that's all,
Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above embodiments.

[0022]

As described above, in the bus control circuit of the present invention, the value stored in the counter initial value circuit in advance gives a gradient to the bus mastership acquisition frequency of each bus master, and the bus mastership of each bus master has a gradient. By raising or lowering the priority of the bus use right according to the number of times the bus use right is acquired, the number of times the bus mastership is acquired by each bus master is kept constant without limiting the acceptance of the bus use request signal. You will be able to keep the ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bus control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing stored contents in a counter initial value storage circuit of this embodiment.

FIG. 3 is a diagram showing a first state of a bus priority register, a priority control counter, and a bus usage right waiting counter according to the present embodiment.

FIG. 4 is a diagram showing a second state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 5 is a diagram showing a third state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 6 is a diagram showing a fourth state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 7 is a diagram showing a fifth state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 8 is a diagram showing a sixth state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 9 is a diagram showing a seventh state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 10 is a diagram showing an eighth state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

FIG. 11 is a diagram showing a ninth state of a bus priority register, a priority control counter, and a bus usage right waiting counter.

[Explanation of symbols]

 11-15 ... Bus priority register 21-25 ... Priority control counter 31-35 ... Subtraction circuit 41-45 ... Bus usage right waiting counter 51-55 ... Subtraction circuit 61 ... Counter initial value storage circuit 62 ... Priority register control Circuit 63 ... Bus usage right wait judgment circuit 64 ... Bus usage request arbitration circuit 65 ... Counter control circuit

Claims (2)

[Claims] 1. A bus control circuit which shares a set of buses with a plurality of bus masters and transfers data, and a bus priority register which exists for each bus master and indicates the priority level of each bus master, and the bus master. When the bus priority indicated by the bus priority register is high, the value is updated when the bus usage right is assigned to the own bus master, and when the bus priority is low, the bus usage right is given to other bus masters. A priority control counter that updates the assigned value, a bus usage right wait counter that updates the value when the bus usage right is assigned to a bus master other than itself with a high bus priority, and the priority control A counter and a counter initial value storage circuit that stores in advance initial values to be set in the bus usage right waiting counter; The priority register control circuit for controlling the priority register and the number of times that the bus usage right cannot be acquired due to the contents of the bus usage right waiting counter exceeds a certain value, the bus usage right is given priority over other bus masters. A bus use right wait determination circuit for giving a bus use right arbitration circuit, and a bus use request arbitration circuit for determining a bus master to which a bus use permission signal is given according to a bus use request signal from each of the bus priority register and the bus use right wait determination circuit. , A counter control circuit for controlling the update of the priority control counter and the bus usage right waiting counter by the bus usage permission signal, and the bus usage permission of each bus master according to the value stored in the counter initial value storage circuit. A certain slope is given to the frequency of signal acquisition, and the bus priority level is determined according to the number of times the bus use permission signal is given. By controlling the value of the bus and raising or lowering the priority of the bus use right, the bus use request signal is always accepted and given to each bus master while maintaining a fixed ratio. And a bus control circuit. 2. The counter initial value storage circuit is made accessible to the processor, whereby the content of the initial value storage circuit is set by the execution program, and thereby the execution program can change the frequency of bus usage right acquisition. The bus control circuit according to claim 1, wherein: