JPH0588916A - Interrupt controller - Google Patents

Abstract

PURPOSE:To shorten the interrupt handling time of an interrupt controller and to fractionalize the priority level on demand. CONSTITUTION:When at least one interrupt source signal from plural interrupt sources is inputted, an interrupt signal processing device 6 outputs the interrupt request signal encoded in accordance with its priority level to a CPU 2. Since this encoded signal indicates not only the priority level but also the interrupt source, the CPU 2 immediately executes proper interrupt handling. The interrupt signal processing device 6 discriminates which of the rise and the fall of the interrupt source signal is true in accordance with the interrupt level signal from the CPU 2. The interrupt source signal is encoded, and thereby, the priority level is fractionalized to process interrupt source signals whose number is larger than the number of interrupt inputs peculiar to the CPU 2. The interrupt handling time is shortened by these functions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control device which, when an interrupt source signal is input, carries out interrupt processing in accordance with its priority.

[0002]

2. Description of the Related Art A one-board or one-chip microcomputer is used for process control or sequence control in electronic devices such as industrial equipment, office automation equipment, and household electric appliances. In order to reduce the cost of equipment, a low-cost microcomputer is selected as much as possible within the range of satisfying the original performance, and peripheral devices and circuits are desired to be simple and low-cost.

An interrupt signal (interrupt source signal) is output when an interrupt is required, for example, when a certain work is started or ended, when a minor accident or malfunction occurs, or when a serious accident such as a power failure occurs. When the device (hereinafter also referred to as “CPU”) detects the interrupt signal, the device stops the work currently in progress and responds to the corresponding process according to its priority (the latter is higher in the above example). Do.

This interrupt signal has a polarity matching positive or negative logic of the CPU, that is, a positive logic when it changes from a low level to a high level (hereinafter referred to as "rising"), and a negative logic, a high level to a low level. When it changes to (hereinafter referred to as "fall"), it must be true (active). Therefore, the interrupt signal is input to an interrupt processing LSI for that purpose, and a trigger level setting register in the LSI is used to set whether the rising edge or the falling edge of the interrupt signal is true or a knot circuit. The polarities were matched by passing through.

Therefore, when there is a signal which is always high and goes low only while the work is being continued, and when an interrupt is required at the start and end of the work, that is, at both the falling edge and the rising edge, one of them is set to the above. In this way, two independent interrupt signals are produced by the above process, or the contents of the trigger level setting register of the interrupt processing LSI are changed in the middle of the sequence.

Further, since the number of interrupts required is generally larger than the number of inputs that can be processed by the CPU, interrupts of the same priority are collected together and the OR (logical sum) is taken to determine the interrupt terminal of the CPU. I was connected to one.

[0007]

However, setting or changing the contents of the trigger level setting register of the interrupt processing LSI involves a relatively large number of instruction steps of the program, so if the contents are repeatedly changed in the middle of the sequence. The whole sequence control might be delayed. On the other hand, if the knot circuit is passed or the contents of the register are not changed, the number of interrupts will increase accordingly.

When an OR interrupt is input,
Since the CPU needs to determine from which interrupt source it was issued to service the interrupt, it polls the status of all interrupted interrupt sources via the I / O port. There is a problem in that the larger the number, the longer the interrupt processing time.

Further, as the number of interrupts increases, the priority of the interrupts tends to be subdivided. However, even if the number problem is solved by collecting ORs for each priority, the priority exceeds the number of inputs peculiar to the CPU. It was impossible to subdivide the degree.

The present invention has been made in view of the above points, and it is a first object of the present invention to shorten the interrupt processing time, and further, it is possible to subdivide the priority as necessary. Is the second purpose.

[0011]

In order to achieve the above object, the present invention provides an interrupt control device having a central processing unit having an interrupt processing function and performing system control, inputting from the central processing unit. A change in the interrupt source signal is detected in response to the interrupt level signal that indicates when the interrupt source signal is high level or low level, and the interrupt source signal changes from high level to low level. Means for determining an interrupt caused by any one of the interrupt source signals as true when the level is changed to low level or high level, and an interrupt request signal to the central processing unit when the means determines that the interrupt is true And an interrupt request output means for outputting.

Further, in an interrupt control device having a central processing unit having an interrupt processing function and performing system control, a plurality of interrupt source signals to be input are grouped into a plurality of blocks, and each block is divided into blocks. Block determining means for determining whether to output the interrupt request signal is provided.

In these interrupt control devices, it is preferable to provide source instruction output means for outputting a source instruction signal for instructing the interrupt source that has output the interrupt source signal.

[0014]

In the interrupt control device according to the present invention, the judging means detects the change of the interrupt source signal according to the interrupt level signal inputted from the central processing unit, and the interrupt source signal changes from the high level to the low level. Alternatively, when the low level changes to the high level, the interrupt by any one of the interrupt source signals is determined to be true, and the interrupt request output means centrally processes the interrupt request signal when any of the interrupts is determined to be true. Since the signal is output to the device, the signal processing when an interrupt occurs becomes easy and the interrupt processing time is shortened.

Further, a plurality of interrupt source signals input by the block determining means are grouped into a plurality of blocks, and whether or not to output the interrupt request signal is determined for each block. It is possible to set a larger number of interrupt inputs than the number of interrupt inputs. Along with that, the number of interrupts that must be combined and taken OR decreases.
The frequency of polling is reduced, and the number of interrupts forming a set of ORs is reduced, so that the time required for polling is reduced and the interrupt processing time is shortened.

Furthermore, by setting priorities for each block in advance, the number of priorities limited by the number of interrupt inputs of the central processing unit can be increased and subdivided.

Further, since the source instruction output means indicates the interrupt source by the source instruction output means, the central processing unit can easily identify the interrupt source, and the interrupt processing time can be shortened accordingly. become.

[0018]

1 is a block diagram showing the configuration of an interrupt control device according to an embodiment of the present invention. The interrupt control device 1 includes a CPU (central processing unit) 2 which has an interrupt processing function and performs arithmetic operations and system control, a ROM 3 in which programs and constant data are stored, and a RAM 4 which is a work memory of the CPU 2. , I / O connected to peripheral devices and external devices and equipped with communication and data input / output interface functions
It comprises a port 5 and an interrupt signal processing device 6 for processing an interrupt source signal input directly or via the I / O port 5 and outputting a coded interrupt request signal to the CPU 2. To the bus line 7.

In the interrupt device 1 thus configured, the CPU 2 executes system control including sequence control and process control of the main body device according to the program of the main routine stored in the ROM 3, When each of the constituent devices notifies the start or end of the work, or when an abnormality or an accident is detected and an interrupt source signal is output (interrupt occurrence), the interrupt signal processing device 6 outputs the interrupt source signal. An input is made, processing is performed in accordance with a preset priority, and an interrupt request signal obtained by coding the priority or the interrupt source is output to the CPU 2 via the dedicated line 8.

When the CPU 2 receives the interrupt request signal, it temporarily suspends the routine currently being processed in accordance with the priority of the interrupt request signal,
After the instruction and data are saved in the register, the program of the interrupt processing routine corresponding to the interrupt source is stored in the ROM 3
To execute the necessary processing, and when the processing is completed, the instruction and data saved in the register are returned to return to the previous routine.

Even if the interrupt processing routine is being executed, if an interrupt with a higher priority occurs, the previous interrupt processing is suspended and the subsequent interrupt processing is prioritized. In this way, interrupts may be processed in multiple layers, and in this case, the plurality of instructions and data saved in the register are processed first after being saved.

Even if an interrupt having a lower priority than the interrupt processing routine being executed occurs, the CPU 2 waits (masks) without accepting it and accepts it after the process being executed is completed. If there is an interrupt process during evacuation, the priority is compared and it is decided whether to accept or continue waiting. The priority and the masking by the priority are performed by the interrupt signal processing device 6 outputting a coded interrupt request signal according to a preset procedure, and the CPU 2 judging it.

FIG. 2 is a block diagram showing a first embodiment of the interrupt signal processing device 6, which is a single custom IC P.
It is composed of an LD (Programmable Logic Device) 10. The PLD 10 includes a logic array 11 including a large number of logic elements (not shown) and one amplifier A each, such as 16R4 on the market.
And a knot circuit N, and eight polarity-inverted control amplifiers C
And four D-FF (flip-flop) circuits D, by converting each logic element of the logic array 11 into an AND element, an OR element, and a knot element in accordance with a user's request, An IC that satisfies the desired logical expression.

The PLD 10 is provided with 20 pins indicated by pin numbers, and the 20th pin is connected to the + 5V power source (Vcc) and the 10th pin is connected to the ground (GND). Pins 1 to 9 and 11 are for each input, Pins 14 to 17 are for output, 12, 13, 1
Pins 8 and 19 are terminals for both input and output.

Hereinafter, for example, "/" added before the signal name "S0" or "WR" such as "/ S0" or "/ WR"
The signals S0 and WR indicate negative logic, that is, the low level is true and the high level is false, and the signal without "/" indicates that the signal conveys different information depending on the positive logic or polarity. Also, as a general rule, the signals input / output to / from the PLD 10 (appearing outside) should be named with capital letters,
Signals used for internal logical operations have names with lowercase letters.

A system clock (hereinafter simply referred to as "clock") CLK which is a reference for synchronization output from the CPU 2 is input to the 1st pin, and passes through a buffer amplifier A and four D-FF circuits D. It is connected to each clock terminal.

Signals / S0 to / S3, which are interrupt source signals, are input to pins 2 to 5, and signals ITLV, / ITEN, / WR, and / RD are input to pins 6 to 9, respectively. Input to the logic array 11 via the respective pins.

The signal input to the 11th pin is a knot circuit N.
The four control amplifiers C for controlling the signals output to the 14th to 17th pins are controlled via the. In this embodiment, since the pin 12 is externally connected, the output signal / iten of the pin 12 is immediately fed back to the inside. Therefore, the signals output from the 14th to 17th pins are simultaneously controlled according to the polarity of the signal / iten.

Whether or not each signal output from the pins 12, 13, 18, and 19 which also serve as input / output is output to the outside because each control amplifier C is controlled by the internal signal from the logic array 11. Are determined independently. On the other hand, when a signal is input to each pin, each input signal is directly input to the logic array 11 because each control amplifier C is in the open state (cutoff state).

Signal / SEL is input to pin 13 and 1
Signals / INTR0, / INTR1 forming coded interrupt request signals are output from the pins 4 and 15 to the pulled-up line, and pins 16 and 17 are
In this embodiment, the external connection is NC (no connection).
However, the same signal as the signal / laiten appears at the 17th pin when the interrupt request signal is internally output. 1
Signals / MASINT and / L are provided on pins 8 and 19, respectively.
MATCH is output, but in this first embodiment, 1
8th pin is NC, 19th pin is D0 of data bus
Connected to the line.

The signals input to and output from the PLD 10 will be collectively described below. First, regarding the input signal group,
Signals / S0, / S2, / S3 are negative logic interrupt source signals respectively input from the respective interrupt sources. For example, signal / S0 is from a timer, signal / S2 is for transmitting / receiving data, S3 is each interrupt signal indicating the end of the work or processing.

The signal / S1 is an interrupt (source) signal which is at a low level during the work or the processing is continued, but it is C at the start and end points thereof, that is, at both the falling edge and the rising edge.
It is necessary to output an interrupt request signal to PU2. Signal IT
LV is a signal input from the CPU 2. Depending on the level of "H" or "L", the interrupt request signal becomes true (output) at the rising edge of the interrupt signal such as the signal / S1 or at the falling edge. Indicate whether to be true.

The signal / ITEN is a negative logic signal input from the CPU 2 via the D0 line of the data bus. When both of the following signals / WR and / SEL are true (L), the PLD 10
It is latched by the rising edge of the clock CLK. The signals / WR and / RD are also negative logic signals input from the CPU 2 and instruct to write or read data to or from each device or element (here, the PLD 10). Signal / SE
L is obtained by decoding the chip select signal output from the CPU 2 via the address bus, and the signal / ITE
It becomes true (L) at the time of latching N and reading the following signal / LMATCH.

Next, regarding the output signal group, the signal INT
R0 and INTR1 form an interrupt request signal with a set of 2 bits, and also serve as a source instruction signal for instructing the priority and the interrupt source corresponding to the priority. The signal / LMATCH is a signal indicating whether or not the levels of the signal / S1 and the signal ITLV match, and in this embodiment, when the signals / RD and / SEL are both true (L), the signal / LMATCH The state (level) is output to the D0 line of the data bus. The details of the signal group for internal processing will be described later.

Table 1 shows the interrupt (source) signals / S0 through //
When S3 becomes true, that is, when any interrupt occurs and no interrupt occurs (NONE), the encode value of the encode interrupt request signal and the priority of each interrupt (also referred to as "priority order") It is a table showing an example.

[0036]

[Table 1]

As is clear from Table 1, the signals / INTR0 and 1 are both false (H) at all times, that is, when the interrupt is not generated, but when the signal / S0 becomes true (L), the signal / INTR0,1. 1 becomes true (L), the signal / INTR1 becomes true (L) when the signal / S2 becomes true, and the signal / INTR0 becomes true (L) when the signal / S1 or / S3 becomes true. The priority becomes lower in the later order.

As described above, the priority level is determined according to the input of the interrupt signals / S0 to / S3, and the encoded value P is output.
The operation of the LD 10 will be described based on the logical formula for determining the operation and the drawings.

In the logical expressions shown in the equations (1) and (2), "/" used on the right side is the low level of the signal, and "/" used on the left side is the logical expression on the right side. Indicates that the signal becomes low level.
As for the operation symbols that perform logical operations on true and false, “*” indicates a logical product (and), “+” indicates a logical sum (or), and “±” indicates an exclusive logical sum (exclusive or). , ": =" Indicates that the logical result on the right side does not immediately appear on the left side (in the case of "="), but the logical result is latched at the rising edge of the clock CLK and the latched result appears on the left side. ..

[0040]

(1) pr1 = / S0 (2) pr2 = / S2 * / pr1 (3) lmatch = S1 ± ITLV (4) pr3 = (/ lmatch + / S3) * / pr2 * / pr1 (5) / laiten: = (/ SEL * / WR * / ITEN) +
(WR * / laiten) (6) / iten = / laiten

[0041]

(2) / LMATCH = / SEL * / RD * / lmatch (2) / INTR0 = / iten * (pr1 + pr3) (3) / INTR1 = / iten * (pr1 + pr2) (4) / MASINT = pr1 + pr2 + pr3

[Mathematical formula-see original document] The above equation 1 shows the signal processed inside the PLD 10, and the equation 2 shows the logical expression of the output signal. The signal / iten shown in (6) of the equation 1 is once output from the 12th pin. Although it is output to the outside, it is handled as an internal signal because it is input from pin 11 immediately by an external connection.

FIG. 3 shows the input clock CLK and each signal / SEL, / ITEN, / WR, / RD, and FIG. 4 shows the input interrupt (source) signals / S1, / S3 and signal / IT.
LV and internal signals / laiten, / lmat respectively
ch and output interrupt request signal / INTR0, / INT
It is a time chart which shows an example of a relation with R1.

The signal names shown on the left side of each waveform are shown without the "/" in order to represent the level of each signal as it is, and the broken line showing each timing is for convenience of comparison with the description of the text. The alphabet is attached. Also, in FIG. 3, a part of the waveform of ITEN is shown by a one-dot chain line,
High level or low level (hereinafter “high”,
It is a part that can be both depending on the case.

First, the interrupt signal / S0 according to (1) of the equation 1
While is true, the signal pr1 (priority 1) indicating the priority becomes high. When the interrupt signal / S2 becomes true by (2), pr2 (priority 2) becomes high when pr1 is low, but pr2 is low when pr1 is high. That is, / S0 has a higher priority, and / S0
While / is true, / S2 is not accepted and masks and ends.

(3) of the equation (1) is the level of the signal lmatch indicating the level match / mismatch by taking the exclusive OR of the interrupt signal S1 and the input signal ITLV at which the interrupt is generated at the falling edge and the rising edge. Is determined, and as shown in the portions between timings A, B, C, D, and E in FIG. 4, when the levels of S1 and ITLV do not match, lmat
ch goes high and goes low on a match. Therefore, when ITLV is low, the level of S1 remains lm
The level of S1 is reached, and when high, the level of S1 is inverted and appears in lmatch.

According to the equation (4), pr3 (priority 3) becomes high when lmatch becomes low or the interrupt signal / S3 becomes true (low), but either pr1 or pr2 becomes high, that is, / S0. Or, if the / S2 interrupt is generated, the masking ends. That is, when interrupts occur simultaneously or while one interrupt is being processed and the other interrupt occurs, the priority indicating which is prioritized is pr1 (/ S
0) is the highest, pr2 (/ S2) is next, pr
3 (/ S1 and / S3 are at the same level) is the lowest.

The equation (5) of the equation 1 will be described with reference to FIG. As shown in FIG. 3, when the signals SEL, ITEN, and WR respectively input from the CPU 2 become true (low), the first term on the right side of the logical expression shown in (5) becomes true, and the second The term becomes false due to WR in it,
The logical sum of the first and second terms is taken, the right side becomes true, and the result of being latched at the rising edge A of the clock CLK causes the internal signal laiten (latched interrupt enable) to go low, and at the same time, SEL and ITEN. WR returns to high.

At the next rising edge B of the clock, WR returns to high, so that the first side on the right side of the logical expression (5) of equation 1 is used.
The term becomes false, but since WR and / laiten are both high, the second term is true and laiten remains low. The signal iten, which is fed back to the inside through the 12th and 11th pins and controls the output of the 14th to 17th pins, is the same as the laiten according to the equation (6). When SEL and WR are true (low) again and ITEN is high, the first term and the second term on the right side of (5) of Formula 1 are both false and the laiten and iten rise and the clock CLK rises. It locks at E (Fig. 3) and returns to high.

Equation 2 shows the logical expression of the output signal. According to (1), when the input signals / SEL and / RD are both true (low) (falling C and rising D of the clock CLK in FIG. 3).
During the period), the level of the internal signal lmatch is output as it is from the 19th pin as the external signal LMATCH. Otherwise, LMATCH is high. Number 2
(2) and (3) are signals / INTRO and / I which constitute the interrupt request signal output from the PLD 10 to the CPU 2.
The logical formula of NTR1 is shown, and the equations (1), (2),
It is determined by combining pr1, pr2 and pr3 such that the plurality determined in (4) do not become high at the same time.

/ INTR0 is pr according to (2) of equation 2.
1 or pr3 is high and / iten is true (low), true (low), / INTR1 is (3)
Goes true (low) when pr1 or pr2 is high and / iten is true.

Output signal / MASI shown in (4) of equation 2
NT becomes true (low) by the logical sum of pr1, pr2, and pr3 when any of the interrupts / S0 to / S3 occurs. This signal is not used in this embodiment because it is output to the externally unconnected pin 18, but it works effectively in the second embodiment of the interrupt signal processing device 6 described later.

From the above description, as shown in Table 1, since all pr1 to pr3 are low unless there is an interrupt, / INTR0 and 1 are both false (high). When an interrupt occurs at the source of S0, pr1 of priority (rank) 1 becomes high. / INTR1, / IN
TR0 goes high together. When an interrupt occurs at the source of S2, pr2 of rank 2 goes high unless there is an interrupt by S0, so / INTR1 goes low and / INTR0 goes high.

An interrupt occurs at the source of S3 or / I
If the interrupt is determined to be true (lmatch is high) at the rising or falling of the signal S1 according to the level of TLV, and if there is no interrupt by S0 or S2, pr3 of rank 3 becomes high, / INTR1 becomes high, / INTRO goes low.

The CPU 2 determines that there is no interrupt if both the interrupt request signals / INTR0, 1 input via the dedicated line 8 (FIG. 1) are high. If any one of them is true (L), it is determined that an interrupt has occurred, and the process proceeds to the interrupt process. At this time, the interrupt request signal is coded and serves as the source instruction signal as well as the priority. Therefore, it is possible to decode the code and perform the interrupt processing according to the interrupt source.

As shown in Table 1, INTR1, INT
If R0 is [L, L], priority is 1 and interrupt source is S0
That is, it is an interrupt from a timer, and if it is [L, H], it is S2 with a priority of 2, that is, an interrupt of data transmission / reception.

However, if it is [H, L], it is obvious that the priority is 3, but the interrupt sources are S1 and S.
Since it does not know which of the three, the CPU2 polls through the I / O port 5 to indicate S3, that is, the end of a certain work or process, or the start or end of the work outputting S1. The processing program is selected by checking the interrupt source level. If S1
If so, it is determined whether the work is started or ended according to the level of the signal ITLV output by the CPU 2 itself.

In this way, the interrupt signal processing device 6
Since the interrupt request signal coded to U2 is output, CP
U2 is a 2-bit input and can handle interrupts with three levels of priority or four interrupt sources. An example of processing a further subdivided priority or a large number of interrupts is shown below.

FIG. 5 is a block diagram showing a second embodiment of the interrupt signal processing device 6, which is composed of two PLDs, that is, a main PLD 15 and a sub PLD 16. Since the main PLD 15 has the same logical configuration as the PLD 10 of the first embodiment, the description of the overlapping parts will be omitted. The sub PLD 16 has a slightly different logical configuration,
The power supply (Vcc), GND, input, output, and input / output terminals are arranged in exactly the same manner.

That is, the clock CLK and the input signal /
ITEN, / WR, / RD, / SEL are PLD15, 1
Inputs are made in parallel to pins 1, 7, 8, 9, and 13 of 6, respectively, and pins 11 and 12 are externally connected. Pins 2 to 5 of PLDs 15 and 16 are
The interrupt source signals / S0-3 and / S4-7 are input, respectively.

The difference between the input signals is that the signal ITLV is input to the 6th pin of the PLD 15 as in the first embodiment, whereas the 6th pin of the PLD 16 is / S0 of the PLD 15.
When any of the interrupts 3 to 3 is input, the signal / MASINT output from the 18th pin is input.

Interrupt request signals / INTR0 and / INT output from pins 14 and 15 of PLDs 15 and 16, respectively.
The R1s are connected in parallel with each other and output to the pulled-up lines. PLD15 18,1
Signals / MASINT and / LMA from pin 9 respectively
TCH is output. The 16th and 17th bins of PLD 15 and the 16th to 19th pins of PLD 16 are NC.

Table 2 shows that when the interrupt (source) signals / S4 to / S7 and the signal / MASINT input to pins 2 to 6 of the sub PLD 16 become true, that is, when any interrupt occurs. 9 is a table showing an example of the encode value of the encode interrupt request signal and the priority of each interrupt when an interrupt has not occurred (NONE).

As is apparent from Table 2, the signals / INTR0 and 1 are both false (H) at all times, that is, when the interrupt is not generated, but when the signal / MASINT becomes true (L), the signal / INTR0,1. 1 becomes true (L), signal / INT4 becomes true (L) when signal / S4 or / S5 becomes true, and signal / IN becomes true when signal / S6 or / S7 becomes true.
TR0 becomes true (L). The priority becomes lower in the later order.

[0065]

[Table 2]

In the second embodiment, of the two PLDs each of which inputs four interrupt signals as a block, the main PLD 15 has a higher priority than the sub PLD 16, and the respective PLDs 15 and 16 are provided. Since priority is set for each interrupt source in /, the priority of each interrupt signal is / S0, / S2, (/ S1 or / S3), (/ S4 or / S5), ( / S6 or / S
7).

The operation of the sub PLD 16 will be described based on the logical expressions shown in equations (3) and (4). The mathematical expressions 3 and 4 are divided into the logical expressions for the internal signal and the external output signal, as in the expressions 1 and 2, respectively.

[0068]

[Equation 3] (1) pr1 = / MASINT (2) pr2 = (/ S4 + / S5) * / pr1 (3) pr3 = (/ S6 + / S7) * / pr2 * / pr1 (4) / laiten: = ( / SEL * / WR * ITEN) +
(WR + / laiten) (5) / iten = / laiten

[0069]

(4) (1) / INTR0 = / iten * (pr1 + pr3) (2) / INTR1 = / iten * (pr1 + pr2)

Here, the signal / M input from the PLD 15
ASINT becomes true (L) according to the result of the logical sum of pr1 to pr3, as shown in (4) of Equation 2. Therefore, the interrupt signal / S0 of the PLD 15 is calculated by the equation (1) in Equation 3.
If an interrupt occurs on any of / S3, pr1 (priority 1) goes high.

According to the equation (2), either of the interrupt signals / S4 and / S5 of the PLD 16 becomes true, and if pr1 is low, pr2 (priority 2) becomes high. Similarly, by (3), if either of the interrupt signals / S6, / S7 becomes true and both pr1 and pr2 are low, pr3
Becomes high. Therefore, the priority order from / S0 to (/ S6 or / S7) is determined. Since the expression (5) and the expression (1) and (2) of the expression 4 are the same as the expression (6) and the expression (2) and (3) of the expression 2, respectively, the description thereof will be omitted.

Equation (4) is similar to Equation (5), but in the first term on the right side of the logical expression, the logical product (AND)
The signal ITEN which is one of the elements is the former ITEN and the latter / ITE. Therefore, if the signal ITEN input from the CPU 2 is high, the signal / laiten of the PLD 16, that is, / iten becomes active, and as shown in (1) and (2) of Equation 4, the PLD 16
Is enabled.

Conversely, if the signal ITEN is low, then P
The signals / laiten and / iten of the LD15 become active, and as shown in (2) and (3) of the equation 2, the PL
D15 is enabled. Therefore, PLD15,
16 are never enabled or disabled at the same time, always one enabled and the other disabled. Since the outputs of the disabled PLD pins 14 and 15 are open (cut off), there is no problem even if each line of the interrupt request signals INTR0 and INTR1 is common.

As shown in the above description and Table 2, PL
D16 has a signal / MASINT with a priority of 1, and an interrupt signal /
S4 or / S5 is next, and interrupt signal / S6 or / S
Priority 3 of 7 is the lowest. / S4 and / S5, / S6 and /
The priorities of S7 are the same level.

In the second embodiment, C is normally used.
Since the PU2 outputs the signal / ITEN with the high level, the sub PLD 16 is enabled, and if there is no interrupt (NONE), both INTR0 and INTR1 are high.

When an interrupt occurs in any of the interrupt sources S4 to S7, the interrupt request signal IN output from the PLD 16
When either TR0 or 1 becomes low, the CPU 2 detects the occurrence of the interrupt, analyzes the code, and if INTR0 is low, determines that the priority level is 3 and interrupt sources S6 and S7.
If INTR1 is low, it is determined as priority 2 and the interrupt sources S4 and S5 are respectively polled to specify the interrupt source and execute the interrupt processing program corresponding to each.

Main PL having higher priority than PLD 16
When an interrupt occurs on the interrupt source S0 to S3 of D15,
Since the PLD 15 detects this and sets the signal / MASINT to true (L), the PLD 16 sets the interrupt sources S4 to S7.
Irrespective of the presence or absence of an interrupt from, both INTR0 and INTR1 are set to low and an interrupt request signal of priority 1 (of PLD 16) is output.

When the CPU 2 detects the interrupt request signal of priority 1 from the PLD 16 and knows that the main PLD 15 is interrupted, it immediately switches the level of / ITEN to low, so that the PLD 16 is disabled. PL
D15 is enabled. Next, CPU2 is PLD1
The interrupt request signal output by the signal 5 is input and decoded, and the interrupt processing program corresponding to the source where the interrupt occurs is executed. If the processing ends and no other interrupt is generated in the PLD 15, the level of the signal / ITEN is returned to high and the interrupt request signal from the PLD 16 is waited.

As described above, the sub PLD 16 is normally enabled, but when the main PLD 15 is interrupted, it is switched to the PLD 15 immediately. Therefore, the PLD 15 has a higher priority and is set in advance in each PLD. Since the interrupt processing is performed according to the priority, the priority is subdivided into substantially five levels in this second embodiment, and the number of interrupt sources is increased to eight.

To further subdivide the priority and increase the number of interrupt sources, a second sub PLD is provided, and the 6th pin thereof is provided with a signal / MASI from the 18th pin of the PLD 16.
It suffices to output a signal corresponding to NT. At this time, the signal /
A signal corresponding to ITEN may be sent via another line of the data bus.

If the priority is subdivided and the number of interrupt sources that can be processed is increased in this way, the number of OR interrupt sets decreases and the polling frequency decreases, and the interrupt sources in one set also decrease. Since the number of polls also decreases, the time required for one polling becomes faster. Therefore, the identification of the interrupt source is simplified and the interrupt processing time is shortened.

[0082]

As described above, the interrupt control device according to the present invention can shorten the interrupt processing time.
Further, the priority can be subdivided as necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an interrupt control device according to the present invention.

FIG. 2 is a block diagram showing a first embodiment of the interrupt signal processing device shown in FIG.

FIG. 3 is a time chart showing an example of signals of respective parts of the interrupt signal processing device shown in FIG.

FIG. 4 is a time chart showing an example of signals of other portions of the interrupt signal processing device shown in FIG.

5 is a block diagram showing a second embodiment of the interrupt signal processing device shown in FIG.

[Explanation of symbols]

1 Interrupt control device 2 CPU
(Central processing unit) 6 Interrupt signal processing device (means for determining an interrupt to be true, interrupt request output means, block determination means, source instruction output means) 10, 15, 16 PLD (programmable logic device) 11 logic Array S0 to S7 Interrupt source signal ITLV Interrupt level signal

Claims (3)

[Claims] 1. An interrupt control device having a central processing unit having an interrupt processing function and performing system control, when an interrupt source signal input from said central processing unit is at a high level or a low level. A change in the interrupt source signal is detected in response to an interrupt level signal indicating whether to make an interrupt true, and when the interrupt source signal changes from a high level to a low level or from a low level to a high level. An interrupt request output means for outputting an interrupt request signal to the central processing unit when the interrupt is determined to be true by the interrupt source signal is provided. An interrupt control device characterized in that 2. An interrupt control device having a central processing unit for controlling the system having an interrupt processing function, wherein a plurality of interrupt source signals to be inputted are grouped into a plurality of blocks, and each block is divided into blocks. An interrupt control device comprising block determining means for determining whether to output an interrupt request signal. 3. The interrupt control device according to claim 1 or 2, further comprising source instruction output means for outputting a source instruction signal for instructing an interrupt source that has output the interrupt source signal. Interrupt control device.