JPH0588851A - Testing device for digital adder circuit - Google Patents

Abstract

PURPOSE:To provide a testing device capable of correctly monitoring the condition of a digital adder circuit concerning the tester to test whether or not an adder circuit for adding the digital data is normal, for example, in a digital communication network. CONSTITUTION:By a data bus detecting means 13, use buses 111-11n are detected, and to the use buses 111-11n, a digital signal for testing is supplied from a digital signal generating means 14 for testing, the testing signal is added by the action of a carry processing prohibiting means 15 in the condition to ignore the carry by using a digital added circuit 12, an odd and even number discriminating means 16 discriminates whether the number of use buses is the odd number of the even number, and based on the discriminated result, it is discriminated whether or not the added result of the digital adder circuit 12 shows the true value, and thus, the condition of the digital adder circuit 12 is discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for monitoring whether or not an adder circuit for adding digital data is normal in a digital communication network.

Generally, in a digital communication network having a function of multiplexing and separating digital signals, an increasing number of digital signals are dealt with by adding digital signals supplied from a plurality of communication systems prior to multiplexing of digital signals. It is supposed to do.

In such a digital communication network, the digital adder circuit as well as the multiplexer / demultiplexer circuit,
It is necessary to constantly monitor whether or not the communication is normal and improve the reliability of the communication network.

[0004]

2. Description of the Related Art In order to meet this demand, conventionally, a parity check is used to monitor whether or not the digital data addition circuit is normal.

However, in such a configuration, since the addition result of the digital addition circuit is only indirectly inspected, there is a problem that the state of the digital addition circuit cannot be accurately monitored.

[0006]

As described above, conventionally, since the state of the digital data adder circuit is only monitored by the parity check, there is a problem that it cannot be accurately monitored. ..

Therefore, an object of the present invention is to provide a test apparatus capable of accurately monitoring the state of a digital adder circuit.

[0008]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

In the figure, numeral 12 is a digital adder circuit which is judged by the test apparatus of the present invention to be normal or not.

This digital adder circuit 12 has n (n is 2
It is configured to add a maximum of n digital signals supplied from the data buses 11 _{1 to} 11 _n (n is a positive integer of 2 or more).

In the test apparatus for testing the digital adder circuit 12, a reference numeral 13 denotes a data bus 11 _m to which the digital signal supplied to the addition process of the digital adder circuit 12 is supplied.
It is a data bus detecting means for detecting (m = 1 to n).

Reference numeral 14 is a test digital signal generating means for supplying a test digital signal having a predetermined bit pattern to the data bus detected by the data bus detecting means 13.

Numeral 15 is a carry processing inhibiting means for inhibiting the carry processing of the digital adding circuit 12 when the digital adding circuit 12 adds the test digital signals.

Reference numeral 16 is an odd / even determination means for determining whether the number of the data buses 11 _m detected by the data bus detection means 13 is an odd number or an even number.

The reference numeral 17 determines whether or not the addition result of the test digital signal by the digital addition circuit 12 is a true value based on the determination result of the odd-even determination means 16.
It is a state determination means for determining whether or not the digital addition circuit 12 is normal.

[0016]

In the above structure, if the digital adder circuit 12 is normal, the bit pattern of the addition result of the test digital signal is the test digital signal when the number of data buses detected by the data bus detection means 13 is odd. It has the same bit pattern as the signal.

On the other hand, when the number of detected data buses is an even number, the bit pattern of the addition result is a pattern in which all the bits are "0".

Therefore, if the addition result of the test digital signal is monitored based on the determination result of the odd / even determination means 16, it can be determined whether or not the digital addition circuit 12 is normal.

According to such a configuration, since the addition result of the digital adder circuit 12 can be directly monitored, the state of the digital adder circuit 12 can be accurately monitored as compared with the conventional case.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 also shows the configuration of the addition unit for digital signals (hereinafter referred to as "main signals") transmitted through the communication network, in addition to the test apparatus which is a feature of the present invention.

Therefore, first, before describing the configuration of the test apparatus, which is a feature of the present invention, the configuration of the main signal adding section will be described.

In the figure, the multiplex signal sent through the transmission path 21 on the low-order group side is separated by the separation circuit 22 into the main signal of each communication system before multiplexing.

The main signals separated by the separation circuit 22 are synchronized with each other in the corresponding data bus 23 ₁
It is passed through the ~ 23 _8.

The main signals passed through the data buses 23 ₁ to 23 ₈ are added by the digital adder circuit 24 for each corresponding bit.

This addition output is time-division-multiplexed with the addition outputs of the other addition systems by the multiplexing circuit 25, and then passed through the transmission path 26 on the high-order group side.

The multiplexed signal sent through the low-order group transmission line 21 is, for example, a time-division multiplexed main signal for a maximum of eight systems. Each main signal is, for example, an 8-bit digital signal.

Further, as shown in FIG. 3, the separation circuit 22 is adapted to repeatedly output the main signal of each communication system at regular time intervals.

The above is the configuration of the addition unit of the main signal. Next, the configuration of the test apparatus which is a feature of the present invention will be described.

In the figure, 27 is a period determination circuit for determining the transmission period and non-transmission period (empty time slot in FIG. 3) of the main signal output from the separation circuit 22.

The period determination circuit 27 is adapted to perform the period determination based on the operation of the separation circuit 22.

Reference numeral 28 detects a data bus 23 _m (m = 1 to n) that gives the main signal used for the addition processing by the digital addition circuit 24, that is, a used bus from the data buses 23 ₁ to 23 _8. It is a used bus detection circuit.

[0034] The use bus detection circuit 28, when it is determined that the transmission period by the period determination circuit 27, by observing the signal transmission state of the data bus 23 _{1-23 8,} so as to perform the detection ing.

29 is a digital adder circuit 24 for the used bus 23 _m detected by the used bus detection circuit 28.
Digital signal for testing whether or not the
It is a test signal generation circuit for supplying a "test signal").

The test signal generating circuit 29 is adapted to generate a test signal when the period judging circuit 27 judges that the period is a non-transmission period.

The test signal is, for example, an 8-bit signal, and each bit is set to "1".

Reference numeral 30 is a carry inhibition circuit capable of inhibiting the carry processing in the addition processing of the digital addition circuit 24.

The carry inhibit circuit 30 inhibits the carry process of the digital adder circuit 24 when the period determining circuit 27 determines that the period is a non-transmission period.

The carry-inhibit process is performed by, for example, inserting a switch in the carry path of the digital adder circuit 24,
This switch is realized by setting the switch to the ON state during the transmission period and to the OFF state during the non-transmission period.

When the period determination circuit 27 determines that the transmission period is 31, the odd-even determination circuit 31 determines whether the number of the used buses 23 _m is an odd number or an even number based on the detection result of the used bus detection circuit 28. Is.

Reference numeral 32 is a true value signal generating circuit for generating a true value signal indicating the true value of the addition result of the test signals when the digital adding circuit 24 is normal.

When the odd / even determination circuit 31 determines that the number of used buses 23 _m is an odd number, the true value signal generation circuit 32 generates an 8-bit signal in which all bits are "1" as a true value signal. To do.

On the other hand, if it is determined that the number is an even number, an 8-bit signal in which all the bit values are "0" is output.

The value of the true value signal is registered in advance in a memory provided inside the true value signal generating circuit 32, for example.

Further, the true value signal is supplied to the period judging circuit 27.
If it is determined to be a non-transmission period by, it is generated.

When the period determination circuit 27 determines that the signal is not in the transmission period 33, whether the addition result of the digital addition circuit 24 and the value of the true value signal output from the true value signal generation circuit 32 match. Is a coincidence determination circuit for determining.

The coincidence determination circuit 33 outputs an alarm signal ALM for notifying that the digital addition circuit 24 is abnormal when both inputs do not coincide.

The operation of the above configuration will be described.

During the transmission period of the main signal, the used bus detection circuit 28 actually outputs the main signal to the digital addition circuit 2.
The data bus (used bus) 23 _m given to the No. 4 is detected.

From this state, the period determination circuit 27
When it is determined to be the non-transmission period (empty time slot), the test signal is supplied to the data bus determined to be the used bus 23 _m by the used bus detection circuit 28.

For example, the data buses 23 ₁ , 23 ₂ , 23
If it is determined that ₃ is the used bus, this data bus 2
A test signal is supplied to 3 ₁ , 23 ₂ , and 23 ₃ .

As a result, during this non-transmission period,
The digital adder circuit 24 adds the test signals on the used bus 23 _m .

However, in this addition, the carry inhibit circuit 30 inhibits the carry process of the digital adder circuit 24.

As a result, if the digital adder circuit 24 is normal and the number of used buses 23 _m is odd, the adder circuit 24 outputs a signal in which the lower 8 bits are all "1". That is, a signal having the same bit pattern as the test signal is output.

On the other hand, if the digital adder circuit 24 is normal and the number of the used buses 23 _m is even, the digital adder circuit 24 outputs a signal in which the lower 8 bits are all "0". It

At the same time, during the non-transmission period of the main signal, the odd / even determination circuit 31 determines whether the number of the used buses 23 _m is an odd number or an even number based on the detection result of the used bus detection circuit 28.

When it is determined to be an odd number by this determination processing, the true value signal generation circuit 32 outputs a true value signal in which all 8 bits are "1". That is, a signal having the same bit pattern as the test signal is output.

On the other hand, when it is determined that the number is even, a true value signal in which all 8 bits are "0" is output.

The true value signal output from the true value signal generation circuit 32 is supplied to the coincidence determination circuit 33, and it is determined for each bit whether or not it coincides with the addition result of the digital addition circuit 24.

When it is determined by this determination process that the two do not match, the match determination circuit 33 outputs an alarm signal ALM.
Is output.

As a result, if the digital addition circuit 24 is abnormal and the addition result does not show a true value, the coincidence determination circuit 3
The alarm signal ALM is output from 3.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, since the digital addition circuit 24 is configured to determine whether the digital addition circuit 24 is normal by directly determining the addition result of the digital addition circuit 24, the reliability is higher than that of the configuration that is determined by the parity check. You can improve your sex.

(2) Further, since the carry process of the digital adder circuit 24 is prohibited so that the addition is performed, only two signals corresponding to the odd-even number of the used buses are prepared as the true value signals. Good.

As a result, the true value signal generating circuit 32 can be simplified and the capacity of the internal memory can be reduced.

(3) Since the values of all the bits of the test signal are the same, the structure of the test signal generating circuit 29 can be simplified.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to such an embodiment.

(1) For example, in the above embodiment, the case where a signal having a bit pattern in which all bits are "1" is used as the test signal has been described.

However, in the present invention, a signal having a bit pattern in which "1" and "0" are arbitrarily combined may be used.

Also in this case, if the number of buses used is odd,
The bit pattern of the true value of the addition result is the same as the bit pattern of the test signal, and if it is an even number, it is a pattern in which all bits are "0".

(2) In the above embodiment, the case where all two true value signals are registered in the internal memory has been described.

However, in the present invention, the test signal generated from the test signal generating circuit 29 may be used as the true value signal when the number of buses used is odd.

(3) In the above embodiment, the case where a signal having the same number of bits as the number of bits of the main signal is used as the test signal has been described, but a signal having a different number of bits is used instead. May be.

(4) Further, in the above embodiment, the case where the test is carried out by utilizing the empty time slot of the main signal has been described.

However, in the present invention, the test may be performed during a period specially prepared for the test.

(5) Further, in the above embodiment, the case where the present invention is applied to the adder circuit for digital signals repeatedly supplied at a predetermined cycle has been described.

However, the present invention can also be applied to the test of an adder circuit for digital signals that are supplied one-off.

(6) In addition to this, it is needless to say that the present invention can be variously modified without departing from the scope of the invention.

[0080]

As described in detail above, according to the present invention,
It is possible to provide a test device capable of determining whether or not the digital addition circuit is normal with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a diagram for explaining a supply form of a main signal.

[Explanation of symbols]

11 _{1 to} 11 _n Data Bus 12 Digital Adder Circuit 13 Data Bus Detection Means 14 Test Digital Signal Generating Means 15 Carry Process Inhibiting Means 16 Odd-Even Judgment Means 17 State Judgment Means

Claims (2)

[Claims] 1. n (n is an integer of 2 or more) data buses
In a test device for monitoring whether or not a digital adder circuit (12) for adding a maximum of n digital signals given by (11 _{1 to} 11 _n ) is normal, said n data buses (11 _{1 to} 11) from among _n), said data bus detecting means for detecting a data bus that supplied the test digital signal to the addition processing of the digital adding circuit _{(12) (11 m) (} m = 1~n) and (13), Test digital signal generating means (14) for supplying a test digital signal having a predetermined bit pattern to the data bus (11 _m ) detected by the data bus detecting means (13), and the digital addition During the addition of the test digital signal by the circuit (12), a carry process inhibiting means (15) for inhibiting the carry process of the digital adding circuit (12) and the data bus detecting means (13) are detected. It said data bus (11 _m) number is determine whether even or odd, Based on the odd / even determination means (16) and the determination result of the odd / even determination means (16), it is determined whether or not the addition result of the test digital signal by the digital addition circuit (12) shows a true value. Thus, the digital adder circuit test apparatus is provided with a state determination means (17) for determining whether or not the digital adder circuit (12) is normal. 2. The digital signal is a repetitive signal repeatedly supplied at a predetermined repetitive cycle, and the test digital signal is added by utilizing an empty time slot of the repetitive signal. Item 1. A digital adder circuit test apparatus according to Item 1.