JPH0588763B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a signal pulse photocurrent extraction circuit used in a distance detection circuit using a semiconductor position detection device (PSD). (Conventional technology) A light source irradiates the object with infrared rays in the form of pulsed light, and the reflected light is sent to the semiconductor position detection element PSD.
(Position Sensitive Detector).
2. Description of the Related Art Distance detection devices that measure the distance to an object using the principle of triangulation are known. FIG. 2 is a schematic diagram showing the optical system of a distance detection device using a PSD. The pulsed light emitted from the light projection LED is projected onto the object to be measured Ob in front by the light projection lens _L1 .
The reflected light enters the PSD via the light receiving lens _L2 . PSD separates background light or extraneous light and pulsed light.
It converts into a current that includes information on the level of background light or extraneous light and the incident position of pulsed light, and outputs it. Therefore, it is necessary to extract only the necessary pulse signal current superimposed on the current caused by the background light or extraneous light (hereinafter referred to as extraneous photocurrent) from the PSD and execute distance calculation. FIG. 3 is a block diagram of the signal processing circuit of the distance detecting device. The output terminals of the PSD are each connected to a pulse signal extraction circuit with the same configuration. The pulse signal extraction circuit logarithmically compresses the pulsed photocurrent and extracts it, and the differential circuit extracts the distance information. FIG. 4 is a circuit diagram showing a conventional signal pulse photocurrent sampling circuit. The conventional circuit uses an NPN transistor 31 to extract the background photocurrent. For this reason, the collector of the NPN transistor 31 and the base of the NPN transistor 35 are connected, and a current is caused to flow from the current source 41 to the base. This is set to operate even when the photocurrent of the photodiode 30 (PSD equivalent circuit) is 0. Also, the emitter of NPN transistor 35 is NPN
Since it is connected to the base of transistor 31, part of the collector current of 35 flows to the base of NPN transistor 31 and part flows to transistor 36. This current of NPN transistor 35 is
Three stages of diodes 48, 4 are connected through a mirror circuit connected by PNP transistors 38, 46, 39.
9, 50 and NPN transistor 47. As for the output level, when there is no signal light, the voltage determined by the two-stage diodes 53 and 54 from the current source 52 enters the - terminal 56 of the comparator 55, and the voltage between this and +
Terminal 57 is compared, this output controls PNP transistor 59, and NPN transistors 61 and 36
It was set by controlling the base voltage of the NPN transistor 31 using a mirror circuit. (Problems to be Solved by the Invention) The circuit shown in FIG. 4 has a drawback that its characteristics vary greatly depending on the design of the transistor 36. The purpose of setting the transistor 36 is to stabilize the emitter potential of the transistor 35. When a constant current including an external light current flows through the transistor 31, the current flowing through the transistor 38 is given by the following equation. I38=(1+Δ38)·(I36+Io/β) Δ38 indicates the error rate of the current I38 when the current of the transistor 36 is set to 1. The current flowing through I39 is given by the following formula. I39=(1+Δ38)·(1+Δ39)·(I36+Io/β) Δ39 indicates the error rate of the current I39 when the current of the transistor 36 is set to 1. The comparator 55 is set in a region where the external light current is small, and the current of the transistor 47 is set by the current source 60, so it is constant. Therefore, Δ(I39−I47) = (1+Δ38)・(1+Δ39)・(Io/Io′)/β However, Io: Collector current of transistor 31 (with external light current) Io′: Collector current of transistor 31 (with no external light current) This is the amount of current imbalance in the amplifier. This current causes the circuit shown in FIG. 4 to oscillate. In the circuit shown in FIG. 4, no consideration is given to increasing the current value of the transistor 36, and the condition is to suppress the external light current to 1 μA or less. SUMMARY OF THE INVENTION An object of the present invention is to provide a photocurrent sampling circuit in which a signal current is added to a carrier current in order to prevent the Early effect, and in which oscillation does not occur. (Means for Solving the Problems) In order to achieve the above object, the signal pulse photocurrent extraction circuit according to the present invention has a collector with a constant current and
The emitter of the NPN transistor for steady current extraction to which the current from the PSD is connected is grounded via a resistor, and the base of the NPN transistor for signal amplification is connected to the collector of the NPN transistor for steady current extraction. and this
A mirror circuit is connected to the collector of the NPN transistor, a signal current is passed from the mirror circuit to the two-stage diode and a current source for setting the carrier current, and the collector of the third NPN transistor connected to the mirror circuit and the memory capacitor are connected to the collector of the third NPN transistor connected to the mirror circuit. Connect the base of the NPN transistor for steady current extraction,
A common source of a differential circuit consisting of a pair of FETs is connected to the mirror circuit, the voltage of the two stages of diodes is connected to the gate of one FET via a voltage follower and a sampling capacitor, and the voltage of the two stages of diodes is connected to the gate of one FET, and A reference voltage is connected to the gate of the FET, the drain of the one FET is grounded via a diode, and the connection point thereof is connected to the base of the third transistor. (Example) The present invention will be described in more detail below with reference to the drawings and the like. FIG. 1 is a circuit diagram showing an embodiment of a signal photocurrent sampling circuit according to the present invention. The constant current source 118 and the PSD are connected to the collector of the NPN transistor 101 for steady current extraction via a voltage follower. The emitter of NPN transistor 101 is grounded via resistor 119. NPN transistor 10 for steady current extraction
The base of an NPN transistor 102 for signal amplification is connected to the collector of 1, and the emitter is grounded. The collector of this NPN transistor 102 is
It is connected to a mirror circuit constituted by a group of PNP transistors 103, 104-107. The collector of the transistor 107 of the mirror circuit is connected to two stages of diodes 113 and 114 and a current source 115 for setting a carrier current. The collector of the third NPN transistor 111 connected to the transistor 105 of the mirror circuit and the memory capacitor 116 are used for the steady current extraction.
Connected to the base of NPN transistor 101. A common source of the differential circuit consisting of a pair of FETs 108 and 109 is connected to the transistor 106 of the mirror circuit. The voltages of the two stages of diodes 113 and 114 are connected to the gate of one FET 109 via a voltage follower 112 and a sample-hold capacitor 117. Reference voltage Vref is applied to the gate of the other FET108.
is connected. The drain of the one FET 109 is grounded via a diode-connected transistor 110, and its connection point is connected to the third transistor 11.
Connected to 1. In the above configuration, a constant current source 11 is connected to the connection point between the base of the transistor 102 and the transistor 101.
When the steady current and signal current from 8 and SPD enter, the steady current is extracted by NPN transistor 101 and resistor 119. The collector of the transistor 105 is connected to the collector of the transistor 111, and further connected to the memory capacitor 116 and the base of the transistor 101. The role of current source 115 is to provide a carrier current. Transistor 106 is connected to the sources of FETs 108 and 109. FETs 108 and 109 form a comparator. This comparator compares the voltage of the sample-and-hold capacitor 117 with the reference voltage Vref, and transmits the current of 106 to the transistor 111 through the transistor 110. The transistor 107 is a two-stage diode 11
3, 114 and current source 115. The output of the diode is voltage follower 1
12 to determine the level of capacitor 117. This level is connected to transistor 109. In the steady state, the switch 120 is on, the voltage follower 112 is operated, and a negative feedback loop is formed. When a signal current comes in, the switch 120 is turned off, and the potential of the memory capacitor 116 is maintained by the voltage of the sample hold capacitor 117. Therefore, the signal current flows through the diode 113,1
14 will output logarithmically compressed output. Regarding the balance of the current provided by the constant current source 115, consider the balance in which the current of the transistor 104 is set to 1. The current _I107 flowing through the transistor 107 is the current of the constant current source 115 as Ica, and the current of the diode as IB.
Then, I ₁₀₇ = (Ica + IB) [1 + Δ (107)] and similarly I ₁₀₅ = (Ica + IB) [1 + Δ (105)] + Io/β. Δ(107) and Δ(105) indicate the percentage of error current caused by mismatching between the transistor 104 and the transistors 105 and 107, respectively;
The steady current is Io, and the gain of the transistor 101 is β. Therefore, a necessary condition for preventing oscillation is that this current difference ΔI=(Ica+IB)[1+Δ(107)−Δ(105)]−Io/β be absorbed in the circuit. The circuit that absorbs this current is the transistor 10
6, 108, 109, and 110, the current is absorbed by the difference between the voltage of the capacitor 117 and the voltage of Vref. Another cause of oscillation is an increase in the base current of the transistor 101 as the signal current is generated. When a signal current Is enters, this current flows as βIs. In FIG. 4, this current flows approximately to memory capacitor 37. In FIG. At this time, the current is drawn out by the transistor 31, and the current flowing to the transistor 35 is restricted. Especially when the external light becomes large, the effect becomes remarkable and leads to oscillation. In the circuit according to the present invention, current is supplied from the transistor 106 to the differential amplification in consideration of this point. With this circuit, the increased current βIs enters from the transistor 105 and flows out to the transistor 111. At this time, since the delay time is determined by transistors 105 and 106, no current delay occurs. Since the circuit is stabilized in this way, it is resistant to oscillation and can use a large carrier current. Therefore, the rise in the base voltage of the transistor 102 when the signal current Is is input can be suppressed to a small level, and the occurrence of the Early effect of the transistor 101 can be suppressed. The reduction in signal current due to the Early effect is given by ΔIa=[Io·VTln{(βIs+Ica)/Ica}]/Va...(1). In other words, this equation shows that when the carrier current Ica is increased, the external light current, early voltage,
Even if ΔIa is determined by the current gain, the absolute value of ΔIa becomes small because the inside of { } of ln approaches 1. It is calculated from the above formula as shown in Table 1 below.

[Table] From the above table, Ica should be set so that ΔIa≪ΔIs is satisfied. [Effects of the Invention] As explained in detail above, the signal pulse photocurrent sampling circuit according to the present invention has a constant current and a collector.
The emitter of the NPN transistor for steady current extraction to which the current from the PSD is connected is grounded via a resistor, and the collector of the NPN transistor for steady current extraction is connected to the base of the NPN transistor for signal amplification, and the emitter is connected to the base of the NPN transistor for signal amplification. ground and this
A mirror circuit is connected to the collector of the NPN transistor, a signal current is passed from the mirror circuit to the two-stage diode and a current source for setting the carrier current, and the collector of the third NPN transistor connected to the mirror circuit and the memory capacitor are connected to the memory capacitor. Connect the base of the NPN transistor for steady current extraction,
A common source of a differential circuit consisting of a pair of FETs is connected to the mirror circuit, the voltage of the two stages of diodes is connected to the gate of one FET via a voltage follower and a sample-hold capacitor, and the other A reference voltage is connected to the gate of the FET, the drain of the one FET is grounded via a diode, and the connection point thereof is connected to the third transistor. When the carrier current is increased with the above configuration,
This has the advantage that the early effect can be reduced. When dealing with a signal component superimposed on a steady current, the Early effect cannot be ignored if the signal component is small compared to the steady current. When Ica is used as a parameter, it becomes as shown in Table 1 shown at the end of (Examples) of the detailed description of the invention. For example, if you set the carrier current to 10μA,
The early effect is about 1.0 to 2.7%, which means that a sufficient level of distance measurement accuracy can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a signal pulse photocurrent extraction circuit according to the present invention. Figure 2 shows
1 is a schematic diagram for explaining the principle of a distance measuring device using a PSD. FIG. 3 is a block diagram showing an example of a circuit of a distance measuring device using a conventional PSD. FIG. 4 is a circuit diagram showing an embodiment of a conventional signal pulse photocurrent extraction circuit. PSD...Semiconductor position detection element, 101, 102,
110, 111,...NPN transistor, 103,
104, 105, 106, 107... PNP transistor, 108, 109... FET, 112... Voltage follower, 113, 114... Diode, 115... Constant current source for carrier current setting, 11
7...Sample hold capacitor, 118...constant current source, 120...switch.

Claims (1)

[Claims] 1. In a signal pulse photocurrent extraction circuit, the emitter of an NPN transistor for steady current extraction, whose collector is connected to a constant current and a current from a PSD, is grounded via a resistor, and the steady current extraction for
The collector of the NPN transistor is used for signal amplification.
The base of the NPN transistor is connected and its emitter is grounded, a mirror circuit is connected to the collector of this NPN transistor, a signal current flows from the mirror circuit to the two-stage diode and a current source for setting the carrier current, and the signal current is connected to the mirror circuit. The third
The collector of the NPN transistor and the memory capacitor are connected to the base of the NPN transistor for steady current extraction, the common source of the differential circuit consisting of a pair of FETs is connected to the mirror circuit, and the gate of one FET is connected to the base of the NPN transistor for drawing the steady current. The voltages of the two stages of diodes are connected through the portage follower and sample hold capacitor, the reference voltage is connected to the gate of the other FET, and the drain of the one FET is grounded through the diode, and the connection point is A signal pulse photocurrent sampling circuit, characterized in that the signal pulse photocurrent extraction circuit is configured by connecting to the base of the third transistor. 2 In the above circuit, the relationship between the carrier current of the NPN transistor for signal amplification, the signal current, the early voltage of the NPN transistor for steady current extraction, and the steady current is as follows: ΔIa=[Io・VTln{(βIs+Ica)/Ica}] /Va Io: Steady current VT=kT/q k: Boltzmann constant q: Electronic charge T: Absolute temperature Is: Signal current Ica: Carrier current Va: Early voltage ΔIa: Early current Claims that satisfy ΔIa≪Is The signal pulse photocurrent sampling circuit according to item 1.