JPH0588603A - Centralized controller - Google Patents

Abstract

PURPOSE:To lighten the load of the communication of the control means of a main controller at the time of communication between the main controller and a terminal equipment. CONSTITUTION:When data are sent from the control means 12 of the main controller 11 to plural terminal equipments 7 at the time of data transmission between the main controller 11 and terminal equipments 7, the data are temporarily written in a transmitting memory 13 and the written data are read out under the control of a transmission timing controller 14 and sent out to the terminal equipments 7. When data are received from the terminal equipments 7, on the other hand, the data are temporarily written in a receiving memory 15 and then the written data are read out of the receiving memory 15 under the control of a reception timing controller 16 and inputted to the control means 12 of the main controller 11. Consequently, the load of the communication with the terminal equipments 7 on the control means 12 becomes relatively light.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for application to a learning device such as a so-called LL (Language Laboratory) system, which is a collective language learning system composed of one master and a plurality of slaves. Central control device.

[0002]

2. Description of the Related Art In a conventional LL system, teaching material duplication tapes for the number of students are reproduced at a pace of each person by an LL tape recorder arranged for each student so that a language practice such as English conversation can be performed. Was becoming. However, in such an LL system, there is a problem in that LL tape recorders for the number of students are required, and the cost increases in proportion to the increase in the size of the LL system.

Further, the recording / reproducing operation by the tape recorder is basically a so-called sequential operation which is carried out in accordance with a magnetic tape, and when the student arbitrarily selects a specific portion of the teaching material and tries to practice it, There is also a problem that it takes time for rewinding and fast-forwarding for the beginning of the tape, resulting in wasted time other than learning.

In order to solve these problems, the present applicant has proposed a technique disclosed in Japanese Patent Laid-Open No. 59-129889.

In this technology, the LL system is divided into a master unit and a slave unit, a random access memory for storing teaching materials is arranged in the master unit, and the slave unit has a D / A converter and this D unit. Headphones and PLAY connected to the A / A converter,
Operation buttons such as repeat and STOP are arranged. Further, the master unit and the slave unit are connected by a communication line. At the time of use, the audio information as the teaching material stored in the random access memory is read out by the time division multiplexing technique according to the operation of the operation button of the child device of each student,
The read voice information is converted into voice through the D / A converter and headphones of the slave unit.

According to this technique, not only each student can immediately practice language learning at his / her own pace, but also all students can simultaneously practice. Also, since it is not necessary to use a tape recorder, L
Even if the size of the L system is expanded, the cost does not increase proportionally.

[0007]

By the way, in a centralized control device applied to an LL system or the like in which a master unit and a slave unit are connected by a communication line in this way, as shown in FIG. The main control unit 1 is provided with a CPU 2, a RAM 3, a serial interface (hereinafter referred to as SIO) 5 connected to the CPU 1 and the RAM 3 through a bus 4, and a switching circuit 6 connected to the SIO 5. ..
Then, the switching circuit 6 and each slave unit 7 as a terminal device are connected.

In the example of FIG. 4, the CPU of the main control unit 1
2 directly controls the SIO 5 to communicate with each child device 7. That is, the serial data representing the data request from each child device 7 is converted into parallel data through the switching circuit 6 and the SIO 5 and loaded into the RAM 3, while the parallel data corresponding to the data request is transferred to the RAM 3.
Is read out from and supplied to the SIO 5, the parallel data is converted into serial data by the SIO 5, and then sent to the slave unit 7 through the switching circuit 6.

However, in such a centralized control device according to the conventional technique, the CPU 2 directly controls the SIO 5 or the like to communicate with a large number of slaves 7, and thus the burden on the communication of the CPU 2 becomes excessive. However, there has been a problem that the communication time required to send and receive data to and from the child device 7 becomes relatively long.

The present invention has been made in view of the above problems, and the load on the control means for communication with the terminal device is relatively light, and the communication required for sending and receiving data to and from the terminal device. An object of the present invention is to provide a centralized control device in which time is relatively short.

[0011]

The centralized control device of the present invention comprises:
For example, as shown in FIG. 1, a plurality of terminal devices 7 and a main controller 11 that sends and receives data to and from the plurality of terminal devices 7.
In a centralized control device comprising:
Is a transmission memory 13, a transmission timing controller 14 for controlling the read / write timing of the transmission memory 13, a reception memory 15, and a reception timing controller for controlling the read / write timing of the reception memory 15. Timing controller 16 and transmission memory 1
3, a transmission timing controller 14, a reception memory 15, and a control means 12 connected to the reception timing controller 16 are provided, and data is transmitted and received between the main control device 11 and a plurality of terminal devices 7. At this time, when the data is transmitted from the control means 12 of the main control device 11 to the plurality of terminal devices 7, the data is once written in the transmission memory 13 and then read by the control of the transmission timing controller 14, and the terminal device is read. In the case of sending data to a plurality of terminal devices 7 and sending data to a plurality of terminal devices 7, the data is once written in the receiving memory 15 and then read by the control of the receiving timing controller 16 to read the data.
The control means 12 of No. 1 is incorporated.

[0012]

According to the centralized control device of the present invention, the main control device 11
When data is transmitted and received between the terminal device 7 and the plurality of terminal devices 7, when data is transmitted from the control means 12 of the main control device 11 to the plurality of terminal devices 7, the transmission memory 1
After the data is written in 3, the written data is read by the control of the transmission timing controller 14 and sent to the terminal device 7. On the other hand, when data is taken in from a plurality of terminal devices 7, the data is once written in the receiving memory 15 and then the data written in the receiving memory 15 is read out by the control of the receiving timing controller 16. It is adapted to be taken into the control means 12 of the control device 11. Therefore, the terminal device 7
The load on the control means 12 for communication with the device becomes relatively light.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the centralized control device of the present invention will be described below with reference to the drawings. In the drawings referred to below, the same components as those shown in FIG. 4 described above are designated by the same reference numerals.

Prior to the description of a specific embodiment, the basic structure and operation of the present invention will be described with reference to FIG.

The centralized control device shown in FIG. 1 comprises a plurality of terminal devices 7 and a main control device 11 for transmitting and receiving data to and from the plurality of terminal devices 7.

The main control unit 11 has a control means 12 having a CPU, a ROM, a RAM and the like.
Reference numeral 2 denotes a transmission memory 13, a transmission timing controller 14 that controls the timing of reading and writing of the transmission memory 13, a reception memory 15, and a reception of which controls the timing of reading and writing of the reception memory. Is connected to the timing controller 16.
The transmission memory 13 and the reception memory 15 are each connected to each terminal device 7.

Next, the operation of the example of FIG. 1 will be described.

When data is transmitted and received between the main control device 11 and a plurality of terminal devices 7, when data is transmitted from the control means 12 of the main control device 11 to the plurality of terminal devices 7, After writing the data to be transmitted to the transmission memory 13, the data is read out by the control of the transmission timing controller 14 and transmitted to each terminal device 7. On the other hand, in the case of fetching data from a plurality of terminal devices 7, the data is once written in the receiving memory 15 and then read by the control of the receiving timing controller 16 and fetched in the control means 12.

Thus, according to the example of FIG. 1, the control means 12
Becomes restricted only when the data to be transmitted is written in the transmission memory 13 and when the data is read from the reception memory 15, and is otherwise vacant. The effect of reducing the load on the control means 12 is obtained because the restraint time for the communication is relatively short. Therefore, the control means 12
Has the secondary effect of being able to perform other control actions as well.

Further, the transmitting memory 13 and the receiving memory 1
Data transmission and reception between the terminal 5 and each terminal device 7 are performed by the control of the transmission timing controller 14 and the reception timing controller 16 without moving the control means 12, so that the overall communication time is shortened. be able to.

Next, specific examples of the present invention will be described. 1 and 4 in the drawings shown below.
Components corresponding to those shown in are given the same reference numerals.

FIG. 2 shows an example of a configuration in which the centralized control device according to the present invention is applied to a learning device. This learning device has one console 21 as a master unit and 64 terminal devices as a master unit. The slave units S1 to S64 are provided.

The console 21 includes an operation section 22 having a key switch and a display section 23 having an LED display. The operation section 22 and the display section 23 are respectively an operation section interface 24 and a display section interface 25.
It is connected to the control unit 12 through. The control unit 12
It is connected to a transmission / reception transfer system circuit 26 described in detail later. Data TX output from the transmission / reception transfer circuit 26
1 to TX64 are sent to the slaves S1 to S64 having a key switch and a headset. On the other hand, slave units S1 to S
The data RX1 to RX64 output from 64 are sent to the transmission / reception transfer system circuit 26.

FIG. 3 shows detailed configurations of the control unit 12 and the transmission / reception transfer system circuit 26. 3, the control unit 12 shown in FIG. 2 is replaced by a CPU 12A, a ROM 12B and a RAM 12C.
Is drawn as. An address bus 31 and a data bus 32 (hatched) are connected to the CPU 12A, the ROM 12B, and the RAM 12C, respectively.

The address data output from the CPU 12 is sent to the RAM 3 for transmission through the address bus 31 and a tristate buffer (hereinafter referred to as a buffer) 33.
4 and the address input port A of the receiving RAM 36 through the buffer 35.

Address input port A of transmission RAM 34
Is supplied with address data from the transmission timing controller 39 through the address line 40 and the buffer 38. Address data is also supplied to the address input port A of the receiving RAM 36 from the receiving timing controller 41 through the address line 42 and the buffer 43.

Data input / output port D of the transmission RAM 34
Is supplied with data from the RAM 12C through the data bus 32 and the buffer 44. The data stored in the transmission RAM 34 is transferred to the latch 46 via the buffer 45.
Is supplied to. The data (parallel data) supplied to the latch 46 is converted from parallel data to serial data through the latch 46 and the shift register 47 and then supplied to the decoder 48.

The output signal of the decoder 48 is the decoder 49.
a through the decoder 49h, the data TX1 to TX64 are supplied to the slaves S1 to S64.

The data RX1 to RX64 which are serial data output from the slave units S1 to S64 are supplied to the start bit check circuit 53 as serial data through the multiplexers 51a to 51h and the multiplexer 52, and are also supplied to the shift register 54. It The output signal of the start bit check circuit 53 is supplied to the reception timing controller 41.

The serial data supplied to the shift register 54 is converted into parallel data through the shift register 54 and the latch 55. This parallel data is stored in the receiving RAM 36 through the buffer 56. The data stored in the receiving RAM 36 is taken into the RAM 12C through the buffer 57 and the data bus 32. It should be noted that the reception timing controller 41 is operated when the data is completely stored in the RAM 12C, in other words, when the transmission from the reception RAM 36 is completed.
A communication completion signal is output from the CPU, and the communication completion signal is output to the CPU through the flip-flop 59 and the data bus 32.
12A is supplied.

The transmission timing controller 39 controls the operations of the buffers 33, 38, 44, 45, the latch 46, the shift register 47 and the decoders 48, 49a to 49h. On the other hand, the reception timing controller 41
Are buffers 35, 43, 56, 57, a latch 55, a shift register 54 and multiplexers 52, 51a.
The operation of 51h is controlled.

Next, the operation of the configuration shown in FIGS. 2 and 3 will be described.

First, the operation when the console 21 side (teacher side) obtains the key input information on the slave units S1 to S64 side (student side) will be described.

In this case, usually, the slave units S1 to S6 are selected according to the learning progress of the students who use the slave units S1 to S64.
Since the key input information in 4 is different, the console 21
It is necessary to transmit command data (generally referred to as a status request signal) for reading key input information from the control unit 12 to all the slaves S1 to S64.

Therefore, the CPU 12 constituting the control unit 12
Under the control of A, the command data for reading the key input information is read from the RAM 12C and supplied to the input side of the buffer 44.

Under the control of the transmission timing controller 39, when the gate of the buffer 44 is opened, the gate of the buffer 33 is also opened and the transmission RAM 34 designated by the address signal supplied from the CPU 12A.
Address (in this case, 6 corresponding to slave units S1 to S64)
The command data for reading the key input information is written in four addresses). In this state, the buffer 38 and the buffer 45 are closed.

When the writing of the command data to the transmission RAM 34 is completed, the buffer 33 and the buffer 44 are controlled under the control of the transmission timing controller 39.
Gates are closed, while the gates of buffer 38 and buffer 45 are opened.

After the writing is completed, the buffer 33
And when the gate of the buffer 44 is closed, the CPU
Since 12A becomes unrelated to communication, it becomes a so-called idle time, and another process, for example, a correct answer rate when a test is previously performed on a student using the slaves S1 to S64, or a standard deviation is calculated. be able to. As shown in FIG. 2, the other processing is performed by the operation of the key switch of the operation unit 22 being taken into the control unit 12 through the operation unit interface 24. It may be set to be automatically performed by software. The calculation result can be sent from the control unit 12 to the display unit 23 through the display unit interface 25 and can be displayed on the display unit 23.

Further, during this idle time, it becomes possible to access a magneto-optical disk (not shown) on which voice data (for example, sentences in English) is recorded, and the voice data recorded on this magneto-optical disk can be accessed. It is also possible to control the data to be sent to the headsets of the respective slaves S1 to S64 through a communication line (not shown) through a D / A converter (not shown).

As described above, when the gate 38 and the gate 45 are opened after the writing of the command data for reading the key input information to the transmission RAM 34 is completed, the transmission timing controller 39 reads them through the buffer 38. A so-called address is designated, and the command data for reading the key input information written at the designated address is held in the latch 46.

The command data for reading the key input information, which is the parallel data held in the latch 46, is converted into serial data by the latch 46 and the shift register 47, and then the decoder 48 and the decoder 49a.
Through 49 h, the data is transmitted as transmission data TX1 to a slave device corresponding to the read address, for example, slave device S1.

The controller (not shown) of the slave unit S1 which has received the serial data which is the command data for reading the key input information, uses the key switch information (generally referred to as a state instruction signal) of its own console as the serial data RX1. It is sent to the transmission / reception transfer system circuit 26 on the 21st side. The serial data RX1 is acknowledge data output corresponding to the command data.

The serial data RX1 is supplied to the multiplexer 52 through the multiplexer 51a and is then supplied from the multiplexer 52 to the start bit check circuit 53 at the timing controlled by the reception timing controller 41.

The start bit check circuit 53 discriminates noise from start bits at a frequency that is an integral multiple of the communication clock. When the start bit is detected,
Data is supplied to the shift register 54, and the serial data RX1 is generated by the shift register 54 and the latch 55.
The key switch information represented by is converted into key switch information of parallel data.

Next, the buffer 43 and the buffer 56 are opened, and the parallel data as the acknowledge data representing the key switch information of the slave unit S1 is written to the address designated by the receiving timing controller 41 in the receiving RAM 36. Be done.

Similarly, the command data transmitted to the remaining slave units S2 to S64 are sequentially read from the transmission RAM 34 and supplied to the slave units S2 to S64. The acknowledge data of each of the slaves S2 to S64 is sequentially supplied to the receiving RAM 36. In this example, the command data is controlled to be transmitted to all the slaves S1 to S64, but the command data may be transmitted only to the necessary slaves to obtain the acknowledge data. ..

When the acknowledge data of all the slaves or required slaves are written in the receiving RAM 36, a communication completion signal is sent from the receiving timing controller 41 through the flip-flop 59 to the data bus 32.
Is supplied to. Further, the buffer 35 and the buffer 57 are opened under the control of the receiving controller 41. Then, the CPU 12A knows that the communication is completed by the communication completion signal, and writes the acknowledge data written in the receiving RAM 36 into the RAM 12C. RAM1
When acknowledge data is written to 2C, the gates of the buffer 35 and the buffer 57 are closed, and the CPU
12A and the receiving RAM 36 are in a non-connection state.

The CPU 12A supplies the corresponding audio data and the like described above to the specific slave units S1 to S64 based on the acknowledge data written in the RAM 12C.

Thus, according to the examples of FIGS. 2 and 3,
The load of software for communication of the CPU 12A is relatively reduced. After writing the command data to be transmitted to the slaves S1 to S64 in the transmission RAM 34, the hardware such as the transmission timing controller 39 automatically transmits to the slaves S1 to S64.
Further, the hardware such as the reception timing controller 41 automatically transmits the acknowledge data to the reception RA.
Since it is written in M36, when viewed from the CPU 12A,
During communication, the transmission memory 34 and the reception memory 3
This is because it is only necessary to perform the write and read operations with respect to 6.

Further, since the load on the software is lightened, the CPU 12A has an advantage that it can perform other control without being aware of communication with the slaves S1 to S64.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various configurations can be adopted without departing from the gist of the present invention.

[0052]

As described above, according to the centralized control device of the present invention, when data is transmitted and received between the main control device and a plurality of terminal devices, the control means of the main control device described above is used. In the case of transmitting data to a plurality of terminal devices, the data is once written in the transmission memory, then read by the control of the transmission timing controller and sent to the terminal device. Further, in the case of fetching data from the plurality of terminal devices, once the data is written in the receiving memory, the data written in the receiving memory is read out by the control of the receiving timing controller and the main control is performed. It is adapted to be incorporated in the control means of the apparatus. Therefore, the effect that the load of the control means for communication with the terminal device is relatively lightened can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a centralized control device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a learning device to which an embodiment of a centralized control device according to the present invention is applied.

FIG. 3 is a block diagram showing a detailed configuration example of a centralized control device of the learning device shown in FIG.

FIG. 4 is a block diagram showing a configuration of a centralized control device according to a conventional technique.

[Explanation of Codes] 7 Terminal Device 11 Main Controller 12 Control Means 13 Transmission Memory 14 Transmission Timing Controller 15 Reception Memory 16 Reception Timing Controller

Claims (1)

[Claims] 1. A centralized control device comprising a plurality of terminal devices and a main control device for transmitting and receiving data to and from the plurality of terminal devices, wherein the main control device comprises a transmission memory and a reading of the transmission memory. A transmission timing controller that controls the timing of the so-called writing, a reception memory, a reception timing controller that controls the timing of the reading and writing of the reception memory, the transmission memory, the transmission timing controller, and the reception Memory and a control means connected to the reception timing controller, and the control means of the main control device when transmitting and receiving data between the main control device and the plurality of terminal devices. When sending data from the above to the above multiple terminal devices, once write it in the sending memory, When the data is read from the plurality of terminal devices by being read out under the control of the reception timing controller, the data is once written in the reception memory, and then the reception timing controller A centralized control device characterized by being read out by control and incorporated into the control means of the main control device.