JPH0587883A - Test wave form generating device - Google Patents

Abstract

PURPOSE:To generate a high speed pattern with the inexpensive constitution, on the basis of a low speed LSI tester, without reducing the channel quantity, by generating the high speed pattern by the data of a pattern memory connected in each of a plurality of formatters and the timing signal allotted by an edge matrix. CONSTITUTION:When an LSI tester controller instructs about the operation, e.g. in four signal mode having 200MHz, timing generators 7a-7d starts two delay generators 12a and 12b at the same time. At this time, the using purpose of the edge is changed in each subcycle, and the delay time for eight edges is loaded 8, and timing-controlled. The edge signal is allotted to a plurality of formatters of a wave form generator 10 through an edge matrix 9 by a control signal 22, and the edge signal and the data of a pattern memory 11 are decoded and outputted 108. Since the read-out contents of the memory 11 can be changed in each formatter, each different wave form can be generated in each subcycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test waveform generator for an LSI tester, and in particular, based on a relatively low speed LSI tester, reduces the restrictions on pattern waveforms and timing conditions to generate a faster pattern. To obtain a test waveform generator.

[0002]

2. Description of the Related Art Conventionally, as a method for generating a high-speed pattern in a relatively low-speed LSI tester, a pin M is used.
There is a UX (multiplex) mode or a pattern sequence. The former is to combine two channels adjacent to each other and combine the output signals of the two channels outside or inside the LSI tester to generate a double speed test signal. In the latter, in one channel, the pattern data of the pattern memory is normally fetched in parallel to the decoder and decoded to obtain the test signal, the driver inhibit state signal, and the expected value signal of the test result. This is a method in which a high-speed signal is obtained by fetching it as a signal into a decoder and sequentially generating it.

[0003]

However, in the pin MUX mode, although the function of each channel, such as waveform generation and the number of edges, is not lost and there is no limitation in the degree of freedom of combination, the number of channels is substantially increased. Will decrease.
On the other hand, in a pattern sequence, the word width of the pattern memory is usually finite, so if a faster test signal is generated, the driver inhibit state signal and the expected value signal of the test result cannot be obtained, and the test signal is simply output. There is a drawback that it becomes only. Of course, if the entire apparatus is composed of high-speed devices, it is possible to generate the above-mentioned high-speed test signal, but of course the apparatus price becomes high and it becomes unacceptable to the user. Also, with the recent trend toward higher speeds and lower prices of devices, higher speed and lower cost LS
I tester is required. Therefore, an object of the present invention is to use a relatively low-speed LSI tester as a base, an inexpensive configuration, a reduction in the number of channels, a high-speed test mode without restrictions on the generation of patterns, and a format / format test. This is to realize an LSI tester that can generate a different waveform on-the-fly, that is, for each sub-cycle.

[0004]

In order to achieve such an object, according to the present invention, an LSI tester having a per-pin structure having a timing generator (delay generator) for each channel is provided in the timing generator. 2 delay generators capable of simultaneous or alternating operation and variable in delay time setting, a control circuit for controlling the delay generator, and a delay time connected to the delay generator and set in the delay generator And a programmable edge matrix for allocating the output of the timing generator,
A plurality of formatters and gate circuits that generate one waveform from the output to which the edge matrix is allocated and the format data; and a plurality of second storage elements that are respectively connected to the formatters and that store the format data. It is characterized by having.

[0005]

A plurality of formatters are provided for each sub-cycle in which the basic cycle is subdivided, and data of a plurality of relatively slow pattern memories connected to each formatter and timing signals assigned to the formatters by the edge matrix are used. Generate fast patterns. Also, format on the fly is possible because the formatter is divided for each sub-cycle.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.
FIG. 4 is a block diagram showing an embodiment of the LSI tester according to the present invention. In FIG. 4, the basic test cycle generator 1, the pattern address generator 2, and the LSI tester controller 3 are connected to each other by bus lines, and the output of the basic test cycle generator 1 is connected to the pattern address generator 2. The outputs of the basic test cycle generator 1, the pattern address generator 2 and the LSI tester controller 3 are connected to the _m channels 5 ₁ to 5 _m by the distributor 4. Here, the pattern address generator 2 uses an address for designating the contents of the pattern memory at a relatively low speed, for example, 50M.
It is generated at about Hz.

FIG. 1 is a block diagram showing a portion of one channel 5 in FIG. In FIG. 1, the timing generator control circuit 6 includes timing generators 7a, 7b and 7 respectively.
c, 7d, and timing generators 7a, 7b, 7
c and 7d are real-time, which constitutes the first memory element.
The timing control memory 8 is connected. The outputs of the timing generators 7a, 7b, 7c, 7d are connected to the edge matrix 9, and the output of the edge matrix 9 is connected to the waveform generator 10. In addition, the waveform generator 1
0 is the pattern memory 11 that constitutes the second memory element.
Are connected. The basic cycle signal 25 from the basic test cycle generator 1 is sent to the timing generator control circuit 6, part of the address signal 26 from the pattern address generator 2 is the real-time timing control memory 8, and the rest of the address signal 26 is The control signal 22 from the LSI tester controller 3 is connected to the pattern memory 11 to the timing generator control circuit 6 and the edge matrix 9, respectively.

The timing generator 7a includes a delay generator 12
a, 12b, and a control circuit 13 for controlling the activation of these delay generators.
b, 7c, and 7d have the same structure. Delay generation unit 12
a and 12b have their delay times specified by the data of the real-time timing control memory 8 output by the address signal 26 of the pattern address generator 2 in FIG. 4, and the basic cycle of the basic test cycle generator 1 in FIG. Two operations are performed when the signals 25 are alternately activated, or when the fundamental period signal 25 is simultaneously activated to specify different delay times to increase the apparent number of edges. The control circuit 13 controls activation of the delay generators 12a and 12b,
The mode signal indicates to the delay generators 12a and 12b whether the mode is normal or n times. In addition, the delay generating unit 12a,
It is possible for 12b to operate while one is operating and the other is overlapping. The delay generator 12a,
Other than 12b, it can be realized by a low speed LSI such as a CMOS LSI. The timing generator control circuit 6 controls edge generation by the basic cycle signal 25 of the basic test cycle generator 1 and the control signal 22 from the LSI tester controller 3 in FIG. 4, and alternately activates the delay generators 12a and 12b. Control either of the simultaneous activations.

In FIG. 2A, 9 is an edge matrix, 10 is a waveform generator, and 11 is a configuration diagram showing the pattern memory in more detail. 2B. The part B in FIG. 2A is composed of a logical product 20 and a logical sum 21 as shown in FIG. 2B, and the edge matrix 9 is a logical product 20 and a logical product shown in FIG. It is an 8 × 8 matrix structure of sum 21. LSI tester controller 3 in FIG.
Each edge signal by the control signal 22 from the waveform generator 1
Formatters 15a, 15b, 15c, 15d in 0
Assign to. Normally, edge signals 100, 101, and 1
02 and 103, 104 and 105, and 106 and 107 are controlled by the control signal 22 so as to operate in a logical sum.

The waveform generator 10 has four formatters 15.
a, 15b, 15c, 15d, logical sums 16a and 16b, and a flip-flop circuit 17, and generates an expected value signal 23 and a driver prohibition control signal 24 together with waveform generation. The waveform generator 10 uses a bipolar IC in order to obtain timing accuracy, and the maximum speed is determined by the number of formatters. The formatter 15a has a format decoder 18a and a logical product 1
The formatter 15 is composed of 9a and 19b.
b, 15c, and 15d have the same structure. The formatters 15a, 15b, 15c and 15d can respectively correspond to sub-cycles in which the basic periodic signal is subdivided, and the formatters 15a, 15b, 15c and 15d, respectively.
Pattern memory 1 for each format decoder of d
4a, 14b, 14c and 14d are respectively connected. For example, the format decoder determines the state by the data shown in the table of FIG. 3 and outputs the waveform according to this state. Here, L (Low Level), H (High Level)
l), P (Positive Pulse) and N (Negative Pulse)
You can select the type of waveform. In this case, it is 3 bits / sub cycle, and only the output state is shown. The data in the pattern memory is decoded and NRZ (Non Return Zero),
A format such as RZ (Return Zero) is selected, and a set / reset signal is created at the output of the edge matrix 9. Furthermore, the formatters 15a, 15b, 15c,
The output of 15d is set by the logical sum 16a and 16b, and the flip-flop circuit 17 is set as a reset signal.
Signal 108 is output. Therefore, the data content read out from the pattern memory can be changed for each formatter, and the respective signals can be ORed before the input to the flip-flop circuit 17, so that different waveforms can be generated for each sub-cycle.

The pattern memories 14a, 14b,
14c and 14d may have an access time of about a basic cycle. For example, when the basic cycle is 50 MHz, the access time may be 20 ns. The pattern memory is required for the number of sub-cycles, but the address bus may be common to all pattern memories, and it is not necessary to use a complicated method such as interleaving.

Pattern memories 14a, 14b, 14
Patterns generated in advance are downloaded to the c and 14d from the LSI tester controller 3 in FIG. Control circuit 13 in the general-purpose mode normally used
Alternately activates the delay generators 12a and 12b for each test cycle and sends the generated edge signal to one formatter of the waveform generator 10 by the edge matrix 9 to generate a waveform. Here, the edge is NR as shown in the table of FIG.
Three edges Z, RZL and RZT are used. In the general mode, phases 1 to 3 correspond to the test cycle, that is, the cycle of 20 ns in FIG. Here, in the table shown in FIG. 5, NZR is “L” or “” in the table shown in FIG.
Edge signal for generating H "waveform, for example, if pattern data is" L ", output as NZR edge signal 1
08 becomes low level. RZL and RZT are edge signals that generate a waveform of "P" or "N" in the table of FIG. 3. For example, if the pattern data is "P", the output 108 is the edge signal of RZL, which is high level, RZT.
The edge signal goes to low level.

In FIG. 1, the LSI tester controller 3 shown in FIG.
Timing generator 7 when instructed to operate at 0 MHz
Each of the four control circuits a, 7b, 7c, and 7d simultaneously activates two delay generators. At this time, the edge is shown in FIG.
The purpose of use is changed for each sub-cycle as shown in the table, and the delay time for eight edges is loaded from the real-time timing control memory 8. This allows real-time timing control. In the table shown in FIG. 5, phases 1 to 4 correspond to the subcycles in FIG. 1 to 1 of the edge signals 100 of the timing generators 7a, 7b, 7c and 7d in FIG.
07 is given to the edge matrix 9, and the formatters 15a, 15b, 15 in FIG.
NRZ, RZL, and RZT are assigned to c and 15d. Therefore, in FIG. 6, the edge signals 100, 102,
104 and 106 are NRZ1 and RZ1L and NRZ, respectively.
2 and RZ2L, NRZ3 and RZ3L, NRZ4 and RZ4
Used as L, while the edge signals 101, 103,
105 and 107 are RZ1T, RZ2T and RZ3, respectively.
Used as T, RZ4T. Here, in FIG. 6, the time a indicates a sub-cycle, and the symbol “·” indicates the activation of the delay generator that generates the edge signal. Also, NRZ1 and RZ
1L and RZ1T are NR in the first sub-cycle
The edge signals of Z, RZL, and RZT are shown.

Each edge signal and the pattern memory 14a,
Data 110, 111 from 14b, 14c, 14d,
112 and 113 are formatters 15a, 15b and 15
It is decoded by c and 15d, and is output as the output 108 through the logical sum 16a and 16b and the flip-flop circuit 17. In FIG. 6, 108 as three output examples.
a, 108b, 108c are shown. Here, as described above, since the data content read out from the pattern memory can be changed for each formatter, and different waveforms can be generated for each sub-cycle, the output 1 shown in FIG.
It is possible to switch and output any one of 08a, 108b, and 108c for each sub-cycle. In addition, FIG.
At pattern memories 14a, 14b, 14c, 1
Reading from 4d is not interleaved.

The formatters 15a, 15b, 15
It is also possible to reduce the pattern memory by fixing the functions of c and 15d in advance. Further, the edge signal is generated by activating the delay generating sections 12a and 12b alternately, instead of activating the delay generating sections 12a and 12b at the same time, and by giving an offset time to one of them, it is possible to apparently perform the same operation as the alternate operation. ..

[0016]

As is clear from the above description,
The present invention has the following effects. That is, even if the basic test cycle is 50 MHz, it is possible to generate test cycles that are 2 times, 3 times, and 4 times, and the pattern memory can be accessed simultaneously without interleaving the currently available memory with an access time of about 20 ns. It can be used. Also,
Without using a high-speed logic circuit as in the past,
Since a relatively low-speed logic circuit such as CMOS LSI is used in the front stage and a high-speed logic circuit such as ECL is used in the waveform generator 10 and the like in the rear stage, a very inexpensive system capable of switching the format and timing on the fly. Can be realized. Since the generation interval of the edge signal can be set relatively wide as shown in FIG. 6, the restart time of the timing generator does not become a problem even if the timing generator is relatively slow. Furthermore, since one cycle is divided, a resolution of 1 / n of the basic cycle can be obtained. For example, if the basic period is 1 ns, a resolution of 1 ns or less will be obtained, which is useful for a device limit test and the like.

[Brief description of drawings]

FIG. 1 is a detailed block diagram of a channel of an embodiment of a test waveform generator according to the present invention.

FIG. 2 is a detailed configuration diagram of an edge matrix, a waveform generator and a pattern memory of an embodiment of the test waveform generator according to the present invention.

FIG. 3 is a table showing the operation of the formatter of the embodiment of the test waveform generator according to the present invention.

FIG. 4 is a configuration diagram showing an embodiment of a test waveform generator according to the present invention.

FIG. 5 is a table showing an example of edge signal allocation in one embodiment of the test waveform generator according to the present invention.

FIG. 6 is a timing diagram showing the operation of an embodiment of the test waveform generator according to the present invention.

[Explanation of symbols]

1 Basic Test Cycle Generator 2 Pattern Address Generator 3 LSI Tester Controller 4 Distributor 5 Channel 6 Timing Generator Control Circuit 7 Timing Generator 8 Real Time Timing Control Memory 9 Edge Matrix 10 Waveform Generator 11, 14 Pattern memory 12 Delay generator 13 Control circuit 15 Formatter 16, 21 Logical sum 17 Flip-flop circuit 18 Format decoder 19, 20 Logical product 22 Control signal 23 Expected value 24 Driver inhibit control signal 25 Basic period signal 26 Address signal 100, 101, 102, 103, 104, 105, 1
06,107 Edge signal 108 output 110,111,112,113 Pattern memory output

Claims (1)

[Claims] 1. A per-pin structure LSI tester having a timing generator (delay generator) for each channel, wherein the delay generator is provided in the timing generator and is capable of simultaneous or alternating operation and variable in delay time setting. A control circuit for controlling the delay generator, a first memory element connected to the delay generator for storing a delay time set in the delay generator, and a programmable memory for allocating an output of the timing generator. An edge matrix, a plurality of formatters and gate circuits that generate one waveform from the output to which the edge matrix is allocated and format data, and a plurality of first formatters that are respectively connected to the formatters and that store the format data. An LSI tester having two storage elements.