JPH0587796B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a decorative clock in which a decorative body such as a doll operates in accordance with a musical piece at a predetermined time such as every hour. This invention relates to a device that integrates and controls a circuit that controls operations and a circuit that controls performance music.

(Prior Art) In a conventional clock of this kind, a driving device for a decorative object such as a doll and a sound device for generating musical pieces are controlled as independent devices.

For this reason, the synchronization between the performance music and the movement of the decorative body is
This was usually done by fine-tuning the movement of the decoration.

(Problem to be solved by the invention) In recent years, many decorative clocks of this type have been sold and installed, so there is a desire for something with more variety. It is conceivable that the program be configured to be selected and played.

However, in the above-mentioned conventional example, it was necessary to adjust the synchronization between the music to be performed and the movement of the decorative body for each music, so it was not possible to easily exchange the music to be performed.

An object of the present invention is to output a first timer signal and a second timer signal for operating circuits that control the decoration and the performance piece, respectively, based on a single reference signal, thereby controlling the decoration and the performance piece. To provide a decorative clock capable of easily switching the music to be played by synchronizing the music and independently controlling the music selection operation by operating separate functions according to each timer signal.

(Means for Solving the Problems) In the decorative clock of the present invention, a decorative object such as a doll operates at a predetermined time, and outputs a reference signal and also outputs a first timer signal based on the reference signal at the predetermined time. a master clock timer which also outputs a second timer signal based on the reference signal a certain period of time before the master clock timer, a decoration drive control circuit which operates the decoration in response to the first timer signal, and a decoration drive control circuit which responds to the second timer signal. A compact optical disk (hereinafter abbreviated as "CD") deck that selects a performance song from the performance songs stored on the compact optical disk and outputs a performance signal, and timing settings for music selection, operation start, and operation end that control the operation. a memory card that stores data such as values and song titles; a control signal generation circuit that reads the data stored in the memory card in response to the reference signal and the second timer signal and outputs a control signal to the CD deck in accordance with the data; It consists of a sound generation circuit that inputs performance signals from a CD deck and generates a performance song.

(Function) In the decorative clock of the present invention, the decoration drive control circuit, the CD deck, and the control signal generation circuit are respectively operated by the first and second timer signals output from the master clock timer.

Therefore, the CD deck and the control signal generation circuit are operated a certain period of time earlier than the decoration drive control circuit, and the music is selected by the predetermined time.

This music selection is performed by a control signal generation circuit reading data stored in the memory card and based on the data, after which a performance signal is output from the CD deck and a performance music is generated from the sound generation circuit.

Furthermore, the movement of the ornament and the music to be played are synchronized since the first and second timer signals output from the master clock timer are synchronized from the beginning of generation, and there is no need to adjust them for each music to be played.

(Embodiment) FIG. 1 is a block diagram showing the circuit configuration of a decorative timepiece according to an embodiment of the present invention.

2 is a master clock timer, which outputs the reference signal φ and also outputs the first timer signal T1 at a predetermined time such as on the hour, and outputs the second timer signal _T1 at a predetermined time before the reference signal φ.
It outputs T ₂ .

4 is a child clock, which inputs the reference signal from the master clock timer 2 and displays the time.

Reference numeral 6 denotes a decoration such as a doll or a stage, and in this embodiment, it also includes driving means such as a motor for driving the doll or the like.

Reference numeral 8 denotes a decoration drive control circuit, which is activated when the first timer signal _T1 is input, and applies a control signal to the decoration 6 to drive it and control its operation. In this embodiment, the decoration drive control circuit 8 is controlled by detecting the movement of the decoration 6, such as the rise and fall of the stage, and applying the detection signal from the decoration 6 to the decoration drive control circuit 8. The operation is stopped.

Reference numeral 10 denotes a CD deck, which is activated when the second timer signal _T2 is input, and has a replaceable built-in CD storing a plurality of performance pieces.

12 is a control signal generation circuit, which operates based on the reference signal φ when the second timer signal _T2 is input;
Song name signal A corresponding to each performance song on CD deck 10
, a music selection signal B for selecting a specified music, a start signal C for instructing the start of the performance, and an end signal D for instructing the end of the performance.

14 is a sound generation circuit, which includes an amplifier 16 that inputs and amplifies the performance signal from the CD deck 10, and a speaker 18 that inputs the output signal and generates sound.
It is composed of.

Next, the operation of the decorative clock having the above structure will be explained using the time chart shown in FIG.

At the predetermined time, the first clock from master clock timer 2
A pulse is generated in the timer signal _T1 , but a pulse is generated in the second timer signal _T2 a certain period of time prior to this.

When the pulse generated in the second timer signal _T2 is input, the CD deck 10 is turned on and activated.

Further, at the same time, the control signal generating circuit 12 which receives the pulse of the second timer signal _T2 also operates in response to this pulse, and first outputs the song title signal A and the song selection signal B.

The CD deck 10 to which these signals A and B are input,
Select the specified performance song from the CD.

Thereafter, at a predetermined time, a pulse is generated in the first timer signal _T1 from the master clock timer 2, and at the same time, a start signal C from the control signal generation circuit 12 is generated.
A pulse is also generated. This first timer signal T ₁
The pulse of C and the pulse of the start signal C are synchronized because they are both signals based on the reference signal φ.

Therefore, the decoration drive control circuit 8 and the CD deck 10, which respectively input these pulses, simultaneously apply signals to the decoration 6 and the sound generation circuit 14, respectively.

Therefore, the decoration body 6 begins to perform an action such as, for example, the stage extends and a doll appears, and at the same time, the selected musical piece is generated.

After that, when the decorative body 6 completes the predetermined operation,
In response to the detection signal from the decoration 6, the decoration drive control circuit 8 stops.

The CD deck 10 also includes a control signal generation circuit 1
When a pulse is generated in the end signal D from 2, it stops.

Next, the configuration and operation of the master clock timer 2 and the control signal generation circuit 12 shown in FIG. 1 will be explained in detail using FIGS. 3 and 4.

FIG. 3 is a diagram showing the circuit configuration of the master clock timer shown in FIG. 1.

20 is a reference signal generation circuit, and 22 is a counter that receives the reference signal φ from the reference signal generation circuit 20 and counts time. 24 is this counter 2
This is a display switching circuit which inputs a signal from 2 and a signal from a counter 36, which will be described later, and switches and outputs these input signals in accordance with an output signal from a setting switch 32, which will be described later. 26 is a decoder that converts the signal from the display configuration switching circuit 24 into a code signal, and 28 is a display that displays the time etc. based on the output signal.

30 is a monitor switch, and 32 is a setting switch for setting the operation start time.

Reference numeral 34 designates an AND gate which receives the signal from the setting switch 32 and the clock signal _φ1 , and 36 designates a counter which inputs its output signal to the clock input φ and counts it as an operation time.

38 is an inverter that inverts the output signal of the setting switch 32; 40 is a one-shot circuit that outputs a pulse in synchronization with the rise of the output signal; 4;
2 is a down counter which inputs the output pulse to the preset input PR and also inputs the count value of the counter 36.

44 is a fixed number pulse generating circuit which outputs a fixed number of pulses when the pulse from the one shot circuit 40 is input, and a delay circuit 46 which delays the pulse from the one shot circuit 40, and when its output signal is input to the set input S. flip flop 48
and an AND gate 50 which inputs the signal from its output Q and the clock signal φ ₂ and applies the output signal to the clock input φ of the down counter 42;
An inverter 52 inverts the output signal, inputs the output signal to the clock input φ, inputs the signal from the output Q of the flip-flop 48 to the reset input R, and inputs a carry signal from the output C to the reset input R of the flip-flop 48. and an n-ary counter 54 which applies the voltage to the signal.

Reference numeral 56 denotes a coincidence detection circuit, which inputs the count value of the counter 22 indicating the current time and the count value of the counter 36 indicating the set operation start time, and outputs the first timer signal _T1 when a coincidence is detected. It is something.

58 is a coincidence detection circuit which inputs the count value of the counter 22 and the count value of the down counter 42 and outputs a second timer signal _T2 when a coincidence is detected.

In the master clock timer 2 having the above configuration, when the setting switch 32 is turned on, the display switching circuit 24 becomes in a state of outputting the count value of the counter 36, and the display 28 shows the operation start time corresponding to the count value. Is displayed.

At the same time, the AND gate 34 is opened and a clock signal _φ1 is generated at its output, and the counter 36 inputting this signal fast-forwards its count value and the operation start time is corrected and set.

On the other hand, when the setting switch 32 is turned off, a pulse is output from the one-shot circuit 40, and the down counter 42, which inputs this pulse to the preset input PR, inputs the count value of the counter 36 and is set to that count value. Ru.

At this time, the pulse from the one-shot circuit 40 is delayed by the delay circuit 46 and applied to the set input S of the flip-flop 48 to set it.

Therefore, the output Q becomes H level, and the AND gate 50 inputting this becomes open, and the clock signal φ ₂ is generated at its output.

This clock signal φ ₂ is applied to the clock input φ of the down counter 42.
decrements the count value by the number of input pulses.

The clock signal φ ₂ from the AND gate 50 is also applied to the n-ary counter 54 via the inverter 52, and the n-ary counter 54 counts the pulses in synchronization with the rising edge of the inverted pulse. Output a signal.

This carry signal is applied to the reset input R of flip-flop 48 to reset it, thereby closing AND gate 50 and its output signal also going to L level.

As a result, the count value of the down counter 42 becomes a value indicating a time a certain period of time before the operation start time set in the counter 36.

Therefore, the coincidence detection circuit 58 that compares the count value of the down counter 42 and the current time detects a coincidence a certain period of time earlier than the coincidence detection circuit 56 that compares the set operation start time and the current time. Therefore, the second timer signal T ₂ is output a certain period of time earlier than the first timer signal T ₁ .

The master clock timer 2 shown in FIG. 3 uses a multi-stage counter to output the first and second timer signals T ₁ ,
It can also be configured to output T ₂ .

FIG. 4 is a diagram showing the circuit configuration of the control signal generation circuit 12 shown in FIG. 1.

60 is an address counter which inputs the second timer signal _T2 to the clock input φ and inputs the signal from the initial reset circuit 62 to the reset input R.

64 is a card reader, which selects music, starts operation,
Based on the signal from the address counter 60, the data is read from a memory card that stores data on each timing setting value and song title for the end of the operation.

66 is a counter output that stores and outputs the numerical value corresponding to each performance song from the card reader 64 as a song title, and 67 inputs the output signal and a signal B from a timer circuit described later and outputs a song name signal A. And gate.

68 is a timer circuit that outputs signals B, C, and D at each timing based on the signal from the card reader 64 and the reference signal φ. This timer circuit 6
Reference numeral 8 denotes a counter 70 that inputs and counts a reference signal φ, a decoder 72 that converts the count into a code signal, a display 74 that inputs and displays the output signal, and a music selection outputted from the card reader 64. , counters 71, 73, and 7 for inputting each timing setting value of operation start and operation end, respectively.
5, and coincidence detection circuits 76, 78, and 80 which input each of these output signals and the count value of the counter 70, detect their coincidence, and output a music selection signal B, a start signal C, and an end signal D, respectively. , is composed of.

The control signal generation circuit 12 having the above configuration outputs each timing setting value read from the card reader 64 as signals B, C, and D in synchronization with the reference signal φ.

Therefore, along with the decoration drive control circuit 8 and the CD deck 10 which are operated by the first and second timer signals T ₁ and T ₂ , the control signal generation circuit 12 outputs a signal synchronized with the operation thereof.

(Effects of the Invention) According to the present invention, the first
Since the circuits that respectively control the decoration and the music to be played are activated by the second timer signal, the operation of the decoration and the music to be played can be synchronized.

This eliminates the need for fine adjustments when exchanging musical pieces, making it easy to select and play a designated piece from a large number of pieces.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the circuit configuration of a decorative clock according to an embodiment of the present invention, Fig. 2 is a time chart of the signals shown in Fig. 1, and Fig. 3 is a circuit of the master clock timer shown in Fig. 1. FIG. 4 is a diagram showing the circuit structure of the control signal generation circuit shown in FIG. 1. FIG. 2... Master clock timer, 6... Decoration body, 8... Decoration body drive control circuit, 10... CD deck, 12...
...Control signal generation circuit, 14...Sound generation circuit.

Claims (1)

[Scope of Claims] 1. A decorative clock in which a decorative object such as a doll operates at a predetermined time, which outputs a reference signal, and outputs a first timer signal based on the reference signal at the predetermined time, a master clock timer that outputs a second timer signal based on the reference signal a predetermined time before; a decoration drive control circuit that operates the decoration in response to the first timer signal; A compact optical disk deck that responds by selecting a song from the performance songs stored in the compact optical disk and outputting a performance signal, and each timing setting value and song name for song selection, operation start, and operation end that control the operation of the compact optical disk deck. a memory card storing data; and a control signal generator for reading the data stored in the memory card in response to the reference signal and the second timer signal and outputting a control signal to the compact optical disk deck in accordance with the data. A decorative clock comprising: a circuit; and a sound generation circuit that inputs a performance signal from the compact optical disk deck and generates a performance piece.