JPH0587646U - Multi data transmission device - Google Patents

Abstract

(57) [Abstract] [Purpose] When the original two-dimensional array is divided and the results are transmitted from multiple devices, the data are arranged in the order of the first column, the second column ... It is necessary to output, and a multi-data transmission device that combines the data of the respective devices through the transmission path and outputs them as apparently one-dimensional array data is obtained. [Structure] A first count that determines an output start position in one-dimensional data, that is, one column, a second count that determines the number of outputs, a third count that counts the total output, and a start signal from a transmission line. It has means for initializing the third count. [Effect] By using the third count value as the memory address by the means, the data for one section can be output to the transmission path in the order of the memory addresses.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a synchronous multi-data transmission device for transmitting digital data from a plurality of self-devices to a partner device in a computer system that executes signal processing or image processing.

[0002]

[Prior Art]

 FIG. 5 is a diagram showing a connection configuration of devices using the multi-data transmission device. In the figure, the transmission line is composed of a clock signal 1, a start trigger signal 3 and a data bus 4, and a data input section 5 receives data from the transmission line. The data value of the data on the data bus 4 changes in synchronization with each clock of the clock signal 1, and the activation trigger signal 3 instructs the data output section to send out the data. By monitoring the clock signal on the transmission line, the data output section 6a sends out data at an arbitrary time point to the data bus 4. The data sent out is the result processed by the processing unit 7a stored in the memory unit in the data output unit. 6b to 6n are the same as the data output unit 6a, and 7b to 7n are the same as the processing unit 7a. The respective data output sections are independent of each other and output the data to the data bus 4 of the transmission line in a time division manner. This is because the results of distributed processing in the processing unit are combined on the transmission line and are fetched as a series of data in the data input unit.

FIG. 6 is a block diagram of a conventional multi-data transmission device showing the data processing unit 6a of FIG. 5 in detail. In the figure, 8 is an output position counter that starts operation by the signal of the activation trigger signal 3 and counts the number of clocks of the clock signal 1, 9 is an output position setting unit that indicates the output position, and 10 is a comparison of two values. A first comparator that determines the magnitude of two values, 11 is an output number counter that counts the number of data outputs, 12 is an output number setting unit that indicates the number of outputs, and 13 is a value that compares two values Is a second comparator for determining the magnitude of the, and a memory unit 14 stores data in the order of address addresses.

Next, the operation will be described. The output trigger counter 3 initializes the output position counter 8 to zero. At the same time, the output position counter 8 starts counting the clock signal 1. When the value set by the output position setting unit 9 is equal to or more than the value, the output 15 of the first comparator 10 1 becomes valid. From the point of time, the output number counter 11 starts counting the clock signal 1 and outputs the memory valid signal 17 and the count value 18. When the value exceeds the value set by the output number setting unit 12, the output 16 of the second comparator 13 becomes valid, and as a result, the output number counter 11 stops operating. At the same time, the memory valid signal 17 is also stopped. When the memory valid signal 17 is valid, the memory section 14 outputs data to the data bus signal 4 for each clock signal 1 using the count value 18 as an address address. Through the series of operations described above, it is possible to output the necessary number of data from the designated position to the data bus from the designated position in the data string synchronized with the clock signal.

FIG. 7 is a timing chart showing the operation example. In the figure, 19 indicates the timing of the clock signal 1, 20 indicates the timing of the activation trigger signal 3, 21 indicates the timing of the count value 18 of the number of data outputs in the first data output section, and 22 indicates the same data output. The timing of the memory valid signal 17 of a part is shown. Reference numerals 23 and 24 represent timings in the data output section 6b, which are a count value 18 and a memory valid signal 17, respectively. Reference numeral 25 represents the timing of the data bus 4, and shows the state in which the data from the two data output units are connected. In the first data output section, the number of outputs is set after 2 clocks from the output position setting. As a result, after starting at the timing 20, the timings 21 and 22 become valid after two clocks, and the state continues for three clock sections. At this time, the data corresponding to the memory address at timing 21 is output from the memory section. The output values are D0, D1 and D2 of the timing 25. Similarly, in the second data output unit, the number of outputs is set to 5 after the processing position is set to 5 clocks, and the values of D3 to D6 at timing 25 are output.

[0006]

In the above-described multi-data transmission device, a specified number of one-dimensional data can be output from a specified position by a series of operations, but the one-dimensional data is repeatedly transmitted to the transmission line in time series. In the case of outputting, this has a problem that the data for one section of this two-dimensional data cannot be shared and output, which occurs when transmitting the two-dimensional data in time series.

The present invention has been made to solve the above-mentioned problems, and in transmission of two-dimensional data in which one-dimensional data is repeatedly output in time series to a transmission line, any one section in the two-dimensional data is transmitted. The purpose is to be able to output minute data.

[0008]

[Means for Solving the Problems]

 In the multi-data transmission device according to the present invention, in addition to the means for counting the timing of the output position and the means for counting the number of outputs, a third means for counting the total value of the number of outputs is added and further The third count is initialized by the signal at the start point.

Further, allocation control is performed so as to individually give a start signal to a plurality of data output sections.

[0010]

[Action]

 In this invention, the total number of outputs is counted at exactly the same time as counting the number of outputs. However, the number of outputs is restarted for each one-dimensional activation trigger signal, but the total number of outputs is counted from the continued value. Performs count operation. The memory address based on this count value is initialized only at the start, and is not initialized after that and has a continuous value.

Further, by performing the allocation control for the activation trigger of the data output unit, it is possible to further combine a plurality of two-dimensional array outputs and increase the array output in any of the two-dimensional directions. .

[0012]

【Example】

 Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention, which is exactly the same as the above-mentioned conventional device from 1, 3, 4 and 8 to 18. Reference numeral 2 is a start signal indicating the first starting point of the two-dimensional data, and 27 is a memory address counter for counting the valid period of the memory valid signal 17.

In the multi-data transmission device configured as described above, the memory address counter is initialized by the start signal 2 and data output is started from this state. An activation trigger signal for instructing the data output for the first column in the secondary array flows through the transmission line, and at this time, the output number counter 11 and the memory address counter 27 have the same value, and the data is output from the memory section. In response to the activation trigger signal for instructing the data output for the second column, the output position counter 8 and the input number counter 11 start the re-operation, but the memory address counter 27 is in the state at the end point. When the data for the second column is being output to the transmission line, the output position counter 8 and the input number counter 11 repeat exactly the same value, but the memory address counter 27 operates from the continued value. Similarly, by repeating the third and subsequent columns, the data of the necessary partition is output from each memory unit to the data bus.

FIG. 2 is an example showing a data pattern for outputting two-dimensional data by three sets of data output units using the multi-data transmission device. On the transmission path, data is transmitted in order from the data (1, 1) in the first column in the figure. The second column is then transmitted from the data (1,2). The same applies to the third and subsequent columns. In the first data output unit, the output position is no waiting after the activation trigger, the number of output data is set to 4, and the data for the frame box 28 is output. In the second data output section, the output position is set to the fifth data and thereafter, the output data number is set to five, and the data for the boxed box 29 is output. Similarly, the third data output unit outputs the data of the boxed box 30.

Example 2. In the embodiment shown in FIG. 3, reference numerals 32a and 32b are the same as the activation trigger signal 3 of the transmission line, but are signals separated so as to individually activate each data output section, and 33 is the instruction timing of the signal for performing the above activation. Is an allocation control unit that controls The figure shows the case where the output side is five. The allocation control starts its operation in response to an instruction of the start signal 2 from the data input section. The start trigger signal of 32a controls 3 of 5 units to output data. After that, the data is output from the remaining two units by the activation trigger signal of 32b.

FIG. 4 is an example showing a data pattern for outputting two-dimensional data in the above five embodiments. As in the case of FIG. 2, the first column of data is transmitted sequentially from the data (1, 1), and the second column and subsequent columns are the same. Boxes 35 to 37 indicate data amounts output by the data output units 34a to 34c by supplying the activation trigger signal 32a. Frame boxes 38 and 39 indicate data amounts output by the data output units 34d and 34e by applying the activation trigger signal 32b.

[0017]

[Effect of the device]

 As described above, according to the present invention, by controlling the three sets of counting means and the count initialization, a plurality of pieces of one-segment data are combined and are apparently transmitted to the transmission line as one secondary array data. Can be output.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data output unit showing a first embodiment of the present invention.

FIG. 2 is an example of an output data pattern of two-dimensional data according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is an example of an output data pattern of two-dimensional data according to the second embodiment of the present invention.

FIG. 5 is a configuration diagram showing multi-connection by a conventional multi-data transmission device.

FIG. 6 is a configuration diagram of a data output unit according to a conventional multi-data transmission device.

FIG. 7 is a timing chart of data output by a conventional multi-data transmission device.

[Explanation of symbols]

 1 Clock signal of transmission line 2 Start signal of transmission line 3 Start trigger signal of transmission line 4 Data bus of transmission line 5 Data input section 6 Data output section 7 Processing section 8 Output position counter 9 Output position setting section 10 First comparison Unit 11 Output number counter 12 Output number setting unit 13 Second comparator 14 Memory unit 27 Memory address counter 33 Allocation control unit

Claims (1)

[Scope of utility model registration request] 1. In a synchronous multi-data transmission device for transmitting digital data from a plurality of self-devices to a partner device, a start trigger signal of a transmission path of the self-device and a value indicating an output start time are set to set an output start state. A first counting means for instructing, a second counting means for instructing a data output state by setting a value indicating the output start state and the number of output data, and a third counting means for inputting the data output state and outputting a memory address. Counting means, a storage unit for inputting the memory address and the data output state and outputting the stored data to the data bus of the transmission line, and a start signal of the transmission line for inputting the first, second and third units. And a means for initializing the count of the multi-data transmission apparatus.