JPH0586117B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a light receiving section in which one-dimensional pixel rows in which unit pixels are arranged in a one-dimensional array are arranged at predetermined intervals;
a first transfer device that is provided corresponding to the one-dimensional pixel array and transfers pixel signals generated in each unit pixel; and a transfer section that transfers pixel signals transferred in parallel by the first transfer device. The present invention relates to a solid-state imaging device that outputs a pixel signal generated in each unit pixel.

[Technical background of the invention and its background]

A conventional solid-state imaging device is shown in FIG. This has a structure called an interline transfer structure,
It has the advantages of good vertical resolution and a simple driving circuit. A one-dimensional pixel row 1 is formed by configuring unit pixels 1-a, 1-b, . . . in a one-dimensional array. Similarly, unit pixels 2-a, 2-b, ..., 3-a, 3-
b, . . . , 4-a, 4-b . These one-dimensional pixel rows 1, 2, 3, and 4 are arranged at intervals of l to form a two-dimensional light receiving section. In the middle of one-dimensional pixel rows 1, 2, 3, and 4,
Corresponding to each one-dimensional pixel row 1, 2, 3, 4, for example, vertical transfer devices 5, 6, 7, using CCD are installed.
8 are provided, and these vertical transfer devices 5, 6, 7,
8 are connected to a common horizontal transfer device 9, and the output of this horizontal transfer device 9 is taken out by the output circuit 9 as a pixel signal. By receiving light, unit pixels 1-a, 1-b, ..., 2-a, 2-
b,...,3-a,3-b,...,4-a,4-b,
The pixel signals generated in the vertical transfer devices 5, 6,
7 and 8 and are sequentially transferred. Therefore, the pixel signals generated in the unit pixels 1-a, 2-a, 3-a, and 4-a are first transferred to the horizontal transfer device 9, and then these pixel signals are transferred from the output circuit 10 as time-series signals. It is taken out. Next, unit pixel 1-
The pixel signals generated at points b, 2-b, 3-b, and 4-b are similarly taken out from the output circuit 10 as time-series signals, and by repeating the same operation, all the pixel signals are converted into time-series signals. It can be extracted as

In such conventional solid-state imaging devices, when the distance l between the one-dimensional pixel arrays 1, 2, 3, and 4 is very long, for example, about 1 mm, the transfer length of one transfer stage is reduced to the normal transfer length (CCD (20 to 30 μm), there is a problem in that the transfer time is extremely long. For example, in the case of a two-phase drive CCD, the length of one electrode must be at least 200 μm, which requires a long transfer time and is not practical. Therefore, it may be possible to drive by increasing the frequency of the transfer pulse by providing multiple transfer stages between them, but the resulting time-series signal is wasted because invalid signals appear between the pixel signals, as shown in Figure 2. At the same time, there was a problem that complicated transfer pulses were used and unnecessary high-speed operation was required.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and
It is an object of the present invention to provide a solid-state imaging device that can operate at high speed with simple transfer pulses without using unnecessary high-speed transfer pulses.

[Summary of the invention]

A light-receiving section has a plurality of one-dimensional pixel rows in which unit pixels as light-receiving elements are arranged in a line in parallel at predetermined intervals in the width direction, and a pixel signal train generated in each one-dimensional pixel row is multiplexed and serially processed. and a transfer section that outputs the signal from the output circuit to the outside, the transfer section being provided in one-to-one correspondence with the one-dimensional pixel columns, and transferring the pixel signals from each one-dimensional pixel column in parallel. a multiplexer unit including a plurality of serial transfer units that receive and output serial signals to the next stage, and a plurality of multiplexers, each of the multiplexers having two input terminals and one output terminal; inputs either the serial signal from the serial transfer section or the serial signal from another multiplexer, and outputs a serial signal obtained by multiplexing and combining the two input serial signals from the output terminal, a multiplexer section that repeatedly multiplexes and combines two serial signals into one composite serial signal using a multiplexer, and finally outputs one composite serial signal from the output circuit; The serial transfer section and the multiplexer have a plurality of transfer electrodes arranged at predetermined intervals along the signal transfer section and to which transfer pulses are applied;
The transfer electrode in the multiplexer is
two input-side electrode groups that direct serial signals applied to one input terminal to the output terminal; and an output-side electrode group that can receive serial signals from each of the two input-side electrode groups. The size of the transfer electrode in the output electrode group is set to be large enough to receive the respective signals from the transfer electrodes of the two input electrode groups corresponding to the transfer electrode. In the multiplexer at the final stage of the transfer section, a signal is taken out from the final transfer electrode in the output electrode group to the output circuit and output as the serial signal to the outside. A solid-state imaging device featuring:

[Embodiments of the invention]

FIG. 3 shows a solid-state imaging device according to a first embodiment of the present invention. There are 2 ⁿ one-dimensional pixel rows (n=1, 2,
) is the case. Unit pixels are configured in a one-dimensional array to form one-dimensional pixel rows 11, 12, 13, 14, and these frequency pixel rows 11, 12, 13,
14 are arranged at predetermined intervals to form a two-dimensional light receiving section. In the middle of the one-dimensional pixel rows 11, 12, 13, 14, there are corresponding first transfer devices 15, 1, respectively.
6, 17, and 18 are provided, forming an inter-array transfer structure. Pixel signals generated in each unit pixel by receiving light are transferred to first transfer devices 15, 16,
17 and 18, and then sequentially transferred to the left by a transfer pulse. These first transfer devices 1
Each pixel signal transferred in parallel from 5, 16, 17, 18 is transferred to the second transfer device 19, 20, 21, 2.
2. Transferred by the transfer devices 25, 26 of the first multiplexing units 37, 38 and the second multiplexing unit 39, and extracted by the output circuit 28 as a time-series signal. Note that each of these transfer devices is of a two-phase drive type.

The operation in which each pixel signal transferred in parallel becomes a time-series signal will be explained in more detail. The pixel signals transferred from the first transfer devices 15, 16, 17, and 18 are named A, B, C, and D. The second transfer device 19 transfers the pixel signal A, and the second transfer device 20 transfers the pixel signal B. In order to double-combine the pixel signal A and the pixel signal B in the first multiplex unit 37, the second transfer device 20 has more transfer stages 23 than the first transfer device 19.
A partially enlarged view of the vicinity of the first multiplex section 37 is shown in FIG. 4, and a time chart of its operation is shown in FIG. The pixel signal A is transferred to the second transfer device 19
Transfer electrodes 191 and 19 are connected to the transfer channel 190 of
2, ..., and the image signal B is transferred on the transfer channel _{200 of} the second transfer device 20 to the transfer electrodes 201, 202,
Transfer is performed according to transfer pulses φ ₁₁ and φ ₁₂ applied to... That is, when the transfer pulse φ ₁₁ applied to the transfer electrodes 191 and 201 is at a low level and the transfer pulse φ _{12 applied to the transfer electrodes 192 and 202 is at a high level, the transfer pulse φ 12} applied to the transfer electrodes 191 and 201 is accumulated in the transfer channel below the transfer electrodes 191 and 201. The charges are transferred to transfer channels below transfer electrodes 192 and 202, respectively. By repeating these operations, the pixel signals A and B are transferred, but because the second transfer device 20 has 1/2 transfer stage, the transfer is delayed. Next, the operation in which pixel signals A and B are combined and transferred to the third transfer device 25 will be described in detail. First, at time t= _t1 , pixel signal A is transferred from transfer electrode 194 to transfer electrode 251.
Next, at time t= _t2 , the signal is further transferred from the transfer electrode 251 to the transfer electrode 252. On the other hand, pixel signal B is transferred from transfer electrode 205 to transfer electrode 251 at time t= _t3 , and at the same time pixel signal A is transferred from transfer electrode 251 to transfer electrode 252. In this way, the pixel signals A and B are combined as time-series signals to become the pixel signal AB, which is sent to the third transfer device 25.
The data are transferred using transfer pulses φ ₂₁ and φ ₂₂ . Transfer pulses φ ₂₁ and φ ₂₂ have twice the frequency compared to φ ₁₁ and φ ₁₂ .

Similarly, the pixel signals C and D are transferred to the second transfer devices 21 and 22 by the transfer pulses φ 11 and φ ₁₁ , respectively.
After being transferred at φ ₁₂ , the first multiplex unit 3
It is synthesized in 8. Since the second transfer device 22 has more transfer stages 24, the multiplexed pixel signal becomes CD and is transferred by the third transfer device 26 using transfer pulses φ ₂₁ and φ ₂₂ . Next, the pixel signals AB and CD transferred by the third transfer devices 25 and 26 are combined in a second multiplex section 39. At this time, the third transfer device 26
Since more transfer stages 27 are formed in the case of , the combined pixel signal becomes ABCD. The pixel signals ABCD synthesized in this way are output to the output circuit 28.
As a result, pulses having a frequency twice that of the transfer pulses φ ₂₁ and φ ₂₂ are extracted as time-series signals.

In this way, according to this embodiment, pixel signals can be extracted as time-series signals using simple transfer pulses without generating invalid signals.

Next, FIG. 6 shows a solid-state imaging device according to a second embodiment of the present invention. In the first embodiment, the number of one-dimensional pixel columns is 2 ⁿ (n=2), but in this embodiment, the number is not 2 ⁿ . The first
Transfer devices 48, 49, 50, 51, and 52 are provided, respectively, and have an interline transfer structure. These first transfer devices 48, 49, 50, 5
The pixel signals 1 and 52 transferred in parallel are transferred by second transfer devices 53, 54, 55, 56, and 57, respectively, and are transferred to first multiplex units 65, 66, and
67. However, since one of the pixel signals to be combined does not exist in the first multiplex unit 66, the pixel signal transferred through the second transfer device 55 and the empty signal are combined. Each pixel signal synthesized in this way is transferred to a third transfer device 58,
59 and 60 are transferred and combined in second multiplex units 68 and 69. In the second multiplex section 69, the sky signal and the image signal are combined, similar to the first multiplex section 66. Further, the combined pixel signals are transferred by fourth transfer devices 61 and 62, and finally combined by a third multiplex unit 70, transferred by a fifth transfer device 63, and sent to an output circuit 6.
4, it is extracted as a time series signal. In this way, according to this embodiment, even when the number of one-dimensional pixel columns is not 2 ⁿ , pixel signals can be similarly extracted as time-series signals.

In the first and second embodiments, the multiplex unit combines pixel signals from two transfer devices, but by making the transfer device a multiphase drive type and using multiphase transfer pulses, it is possible to combine pixel signals from three or more. The same effect can be obtained by combining pixel signals from two transfer devices.

Furthermore, it goes without saying that even if a plurality of transfer devices (for example, dual channel type) are provided for one pixel column, pixel signals can be synthesized with the same configuration.

〔Effect of the invention〕

According to the present invention, high-speed transfer can be obtained while suppressing the increase in the speed of transfer pulses, and output sensitivity can be increased. That is, in the present invention,
In multiplexing, two signals are multiplexed. Therefore, compared to the case where a larger number of signals are multiplexed, it is possible to transfer the signals using pulses that are slower and easier to handle. This made it possible to further improve the ease of handling. Furthermore, since each multiplexer multiplexes two signals, the transfer electrodes in the output side electrode group of the multiplexer can be made as small as possible to receive two signals. . Therefore, it was possible to reduce the capacitance formed by the transfer electrodes in the output side electrode group and increase the transfer speed. Furthermore, regarding the multiplexer and output circuit as the final stage, the transfer electrodes in the output side electrode group of this multiplexer are also configured to be small enough to receive two input signals as described above. Therefore, the capacitance formed by this transfer electrode was also small.
Since the sensitivity of reading by the output circuit is inversely proportional to the capacitance, it was possible to increase the sensitivity of reading.

[Brief explanation of the drawing]

Figure 1 is a structural diagram of a conventional solid-state imaging device, and Figure 2 is a time chart showing output signals from the same device.
3 is a structural diagram of a solid-state imaging device according to the first embodiment of the present invention, FIG. 4 is a partially enlarged view of the multiplexer section of the device, FIG. 5 is a time chart showing transfer pulses of the device, and FIG. The figure is a structural diagram of a solid-state imaging device according to a second embodiment of the present invention. 1, 2, 3, 4, 11, 12, 13, 14, 4
3, 44, 45, 46, 47... one-dimensional pixel row,
5, 6, 7, 8, ... vertical transfer device, 9 ... horizontal transfer device, 15, 16, 17, 18, 19, 2
0, 21, 22, 25, 26, 48, 49, 5
0, 51, 52, 53, 54, 55, 56, 5
7, 58, 59, 60, 61, 62, 63...transfer device, 37, 38, 39, 65, 66, 67,
68, 69, 70...Multiplexer section, 10,
28, 64...output circuit.

Claims (1)

[Scope of Claims] 1. A light-receiving section in which a plurality of one-dimensional pixel rows in which unit pixels as light-receiving elements are arranged in a row are arranged in parallel at predetermined intervals in the width direction; and a pixel signal generated in each of the one-dimensional pixel rows. a transfer unit that multiplexes the columns and outputs them as a serial signal from the output circuit to the outside; the transfer unit is provided in one-to-one correspondence with the one-dimensional pixel columns; a multiplexer unit including a plurality of serial transfer units that receive the pixel signals in parallel from and output them as serial signals to the next stage, and a plurality of multiplexers, each multiplexer having two input terminals and one output terminal. Each of the input terminals receives either a serial signal from the serial transfer section or a serial signal from another multiplexer, and the output terminal multiplexes and synthesizes the two input serial signals. A multiplexer outputs a serial signal, and repeats multiplexing and combining the two serial signals into one composite serial signal by a multiplexer, thereby finally outputting one composite serial signal from the output circuit. The serial transfer unit and the multiplexer have a plurality of transfer electrodes arranged at predetermined intervals along the signal transfer unit and to which transfer pulses are applied;
The transfer electrode in the multiplexer is
two input-side electrode groups that direct serial signals applied to one input terminal to the output terminal; and an output-side electrode group that can receive serial signals from each of the two input-side electrode groups. The size of the transfer electrode in the output electrode group is set to be large enough to receive the respective signals from the transfer electrodes of the two input electrode groups corresponding to the transfer electrode. In the multiplexer at the final stage of the transfer section, a signal is taken out from the final transfer electrode in the output electrode group to the output circuit and output as the serial signal to the outside. A solid-state imaging device featuring: