JPH0586083B2 - - Google Patents
Info
- Publication number
- JPH0586083B2 JPH0586083B2 JP27382685A JP27382685A JPH0586083B2 JP H0586083 B2 JPH0586083 B2 JP H0586083B2 JP 27382685 A JP27382685 A JP 27382685A JP 27382685 A JP27382685 A JP 27382685A JP H0586083 B2 JPH0586083 B2 JP H0586083B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- emitter
- gain
- bias circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は増幅器に関し、特に段階的に利得を切
換る増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier, and more particularly to an amplifier whose gain is switched stepwise.
一般に可変利得増幅器は、オーデイオ分野の信
号系や測定装置などのコントロールに使われ、外
部の直流電圧又は直流電流等により利得を変える
ことが要求される。
Generally, variable gain amplifiers are used to control signal systems and measurement devices in the audio field, and are required to change the gain depending on external DC voltage or current.
従来の可変利得増幅器の一例を第３図に示す。
この可変利得増幅器はトランジスタ２４，２５，
２６，２７，２９及び定電流源２８，３１、バイ
アス３２よりなる差動増幅器でありトランジスタ
２２を介して信号源２０が接続されている。トラ
ンジスタ２２のコレクタ−エミツタ間のインピー
ダンスはトランジスタ２２のベースに接続されて
いる。定電流源２３により可変される。ここで抵
抗３０のインピーダンスをＲ１、トランジスタ２
２のコレクタ−エミツタ間のインピーダンスを
Rceとすると、第３図における増幅器の利得は、
下式(1)になる。 An example of a conventional variable gain amplifier is shown in FIG.
This variable gain amplifier includes transistors 24, 25,
26, 27, and 29, constant current sources 28, 31, and a bias 32. The signal source 20 is connected through a transistor 22. The collector-emitter impedance of transistor 22 is connected to the base of transistor 22. It is varied by a constant current source 23. Here, the impedance of the resistor 30 is R1, and the impedance of the transistor 2 is
The impedance between the collector and emitter of 2 is
Assuming Rce, the gain of the amplifier in Fig. 3 is
The following formula (1) is obtained.
R1／Rce ……(1)
(1)式よりトランジスタ２２のコレクタ−エミツ
タ間のインピーダンスを定電流源２３の電流を可
変することにより増幅器の利得を可変することが
できる。前述のことより、オーデイオ分野の信号
系や測定装置などのコントロールに使用した場合
定電流源２３を外部に設置すれば、外部より利得
を可変することができる。 R1/Rce...(1) From equation (1), the gain of the amplifier can be varied by varying the impedance between the collector and emitter of the transistor 22 by varying the current of the constant current source 23. As mentioned above, when used to control a signal system or a measuring device in the audio field, if the constant current source 23 is installed externally, the gain can be varied externally.
第３図の従来の回路においては、設定利得の自
由度はあるが、トランジスタ２２のコレクタ−エ
ミツタ間のインピーダンスを定電流源２３によつ
て可変するため、定電流源及びトランジスタの能
力に左右される。この従来回路をFMやAMの受
信器のL0／Dx（入力感度変更回路）回路などの段
階的な利得の可変を必要とした場合、利得を調整
する定電流源のわずかな変化で利得が変化する為
設定が容易でない。また集積回路化した場合トラ
ンジスタのコレクタ−エミツタ間のインピーダン
スのバラツキも大きいため利得のバラツキも大き
くなる。
In the conventional circuit shown in FIG. 3, there is a degree of freedom in setting the gain, but since the impedance between the collector and emitter of the transistor 22 is varied by the constant current source 23, it is influenced by the capabilities of the constant current source and the transistor. Ru. When this conventional circuit is used in an FM or AM receiver's L 0 /Dx (input sensitivity change circuit) circuit that requires stepwise variable gain, the gain can be adjusted by a slight change in the constant current source that adjusts the gain. It is not easy to set because it changes. Furthermore, when integrated circuits are implemented, the impedance variation between the collector and emitter of the transistor is large, so the gain variation also becomes large.
本発明の可変利得増幅器は、極性の等しい第
１，第２，第３のTrのエミツタが共通に接続さ
れ、該共通エミツタに第１，第２，第３のTrと
同じ極性の第４のTrのコレクタが接続され、第
４のTrのベースを入力端とし、第４のトランジ
スタのベースは第１の抵抗を介して第１のバイア
ス回路に接続し、第４のTrのエミツタは第２の
バイアス回路に接続され、前記第１，第２のTr
のベースは、第３のバイアス回路に接続し第１の
Trのコレタは、第４のバイアス回路に接続され、
第２，第３のTrのコレクタは第２の抵抗を介し
て第４のバイアス回路に接続され、第３のTrの
ベースは、第５のバイアス回路に接続され、第
２，第３のTrのコレクタを出力端子とし、第１、
第２のトランジスタのエミツタの面積比によつて
利得差が設定されたことを特徴とする。
In the variable gain amplifier of the present invention, the emitters of the first, second, and third T r having the same polarity are commonly connected, and the emitters of the first, second, and third T r having the same polarity are connected to the common emitter. The collectors of the fourth T r are connected, the base of the fourth T r is used as an input terminal, the base of the fourth transistor is connected to the first bias circuit via the first resistor, and the fourth T r The emitter of T r is connected to a second bias circuit, and the emitter of the first and second T r
The base of is connected to the third bias circuit and the base of the first
The collector of T r is connected to a fourth bias circuit,
The collectors of the second and third T r are connected to the fourth bias circuit via the second resistor, the bases of the third T r are connected to the fifth bias circuit, and the second and third T r The collector of T r is the output terminal, and the first,
It is characterized in that the gain difference is set depending on the area ratio of the emitter of the second transistor.
なお、第３のバイアス回路は、第２の抵抗、第
３の抵抗、第４の抵抗の他端が直列接続され、第
２の抵抗の一端が電源電圧に接続され、第４の抵
抗の他端が接地され、前記第２の抵抗と前記第３
の抵抗の接続点が前記第３のトランジスタのベー
スに接続され、、第３の抵抗と第４の抵抗の接続
点に第４のトランジスタのコレクタに接続され、
前記第４のトランジスタのエミツタは接地され、
第４のトランジスタのベースを制御端子として第
４のバイアス回路が接続された構成とすることが
できる。 Note that in the third bias circuit, the other ends of the second resistor, the third resistor, and the fourth resistor are connected in series, one end of the second resistor is connected to the power supply voltage, and the other ends of the fourth resistor are connected in series. the second resistor and the third resistor are grounded.
a connection point between the resistors is connected to the base of the third transistor; a connection point between the third resistor and the fourth resistor is connected to the collector of the fourth transistor;
the emitter of the fourth transistor is grounded;
A fourth bias circuit may be connected to the base of the fourth transistor as a control terminal.
以下本発明について図面を参照して説明する。 The present invention will be explained below with reference to the drawings.
第１図は本発明の一実施例の回路図である。第
１のトランジスタであるトランジスタ２，第２の
トランジスタであるトランジスタ３，第３のトラ
ンジスタであるトランジスタ４（以下トランジス
タをTrと示す。）は差動構成をなし、第４のトラ
ンジスタである。Tr１０及び第１の抵抗である
抵抗６定電圧源７によりバイアスされている。
Tr２のベースは、定電圧源８によりバイアスさ
れ、Tr４のベースは電圧源９によりバイアスさ
れている。第２の抵抗である抵抗５は差動の負荷
となつている。ここで定電圧源８より電圧源９の
電位の方が高い場合信号源２０より、入力端１に
信号が印加されるとTr１０により電流増幅され
Tr４を介して負荷である抵抗５に電流が流れ、
出力端１１には、抵抗５に流れる電流に比例した
電圧が発生する。 FIG. 1 is a circuit diagram of an embodiment of the present invention. Transistor 2, which is a first transistor, transistor 3, which is a second transistor, and transistor 4, which is a third transistor (hereinafter referred to as a transistor ), have a differential configuration and are a fourth transistor. It is biased by T r 10 and a resistor 6 which is a first resistor 6 and a constant voltage source 7 .
The base of T r 2 is biased by a constant voltage source 8 , and the base of T r 4 is biased by a voltage source 9 . The second resistor 5 serves as a differential load. Here, if the potential of voltage source 9 is higher than that of constant voltage source 8, when a signal is applied to input terminal 1 from signal source 20, the current is amplified by T r 10.
Current flows through T r 4 to resistor 5, which is the load,
A voltage proportional to the current flowing through the resistor 5 is generated at the output end 11 .
逆に、定電圧源８より電圧源９の電位の方が低
い場合信号源２０より入力端１に信号が印加され
るとTr１０により電流増幅されTr３を介して負
荷でなる抵抗５に電流が流れると同時にTr２に
も電流が流れる。ここでTr１０のコレクタに流
れる電流をI0とし、Tr２のエミツタ面積をATr３
のエミツタ面積をＢとすると、抵抗５に流れる電
流は(2)式になる
抵抗５に流れる電流＝Ｂ／Ａ＋ＢI0 ……(2)
出力端１１には抵抗５に流れる電流に比例した
電圧が発生するためTr２，Tr３の面積比と抵抗
５により増幅利得が設定できる。以上のことより
定電圧源８より電圧源９の電位の方が高い場合よ
り定電圧源８より電圧源９の電位が低い方がTr
３，Tr２のエミツタ面積比分だけ出力電位すな
わち増幅利得が低下する。上記のことより負荷抵
抗５の値及びTr３，Tr２のエミツタ面積比を設
定すれば、自由に２段階の利得をもつた増幅器に
できる、従来例の第３図で問題であつた、段階的
な利得可変を容易に設定できる。すなわち抵抗
値、エミツタ面積比の設定は容易である。また第
１図において電圧源９により容易に利得の切換が
可能であり集積回路化した場合でも利得のバラツ
キは小さい。 Conversely, when the potential of the voltage source 9 is lower than that of the constant voltage source 8, when a signal is applied from the signal source 20 to the input terminal 1, the current is amplified by T r 10 and passed through T r 3 to the resistor 5 which is the load. When a current flows through T r 2, a current also flows at the same time. Here, the current flowing through the collector of T r 10 is I 0 , and the emitter area of T r 2 is AT r 3.
If the emitter area of is B, then the current flowing through the resistor 5 is expressed by equation (2). Current flowing through the resistor 5 = B/A + BI 0 ... (2) A voltage proportional to the current flowing through the resistor 5 is applied to the output terminal 11. Therefore, the amplification gain can be set by the area ratio of T r 2 and T r 3 and the resistor 5. From the above, T r
3. The output potential, that is, the amplification gain decreases by the emitter area ratio of T r 2. From the above, by setting the value of the load resistor 5 and the emitter area ratio of T r 3 and T r 2, it is possible to freely create an amplifier with two stages of gain, which was a problem in the conventional example shown in Fig. 3. , stepwise gain adjustment can be easily set. That is, it is easy to set the resistance value and emitter area ratio. Further, in FIG. 1, the gain can be easily switched by the voltage source 9, and even when integrated circuits are implemented, the variation in gain is small.
第２図に本発明で正の単電源を用いた場合の具
体例を示す。第２図において第１図と対応する部
分については、同一番号で示し説明をはぶく。抵
抗４０，４２、Tr４３は、Tr２とTr１０に所定
のバイアスを与える為の回路である。抵抗４４，
４５，４６はTr４に所定のバイアスを与える回
路でTr４７によりTr４のベースの電位をTr２，
３のベース電位に比べて高くしたり低くしたりす
ることにより、利得を可変するものである。 FIG. 2 shows a specific example in which a single positive power source is used in the present invention. Portions in FIG. 2 that correspond to those in FIG. 1 are designated by the same numbers and explanations are omitted. Resistors 40, 42 and T r 43 are circuits for applying a predetermined bias to T r 2 and T r 10. Resistor 44,
45 and 46 are circuits that apply a predetermined bias to T r 4, and T r 47 changes the base potential of T r 4 to T r 2,
By making the base potential higher or lower than the base potential of No. 3, the gain can be varied.
以上説明したように本発明は、段階的な利得可
変を容易に設定できる。
As explained above, according to the present invention, stepwise gain variation can be easily set.
第１図は本発明の一実施例の回路図、第２図は
本発明の一実施例の回路図、第３図は従来例の回
路図である。
１……入力端、２〜４……トランジスタ、５，
６……抵抗、７，８……定電圧源、９……電圧
源、１０……トランジスタ、１１……出力端、２
０……信号源、２１……入力端、２２……トラン
ジスタ、２３……電流源、２４〜２７……トラン
ジスタ、２８……定電流源、２９……トランジス
タ、３０……抵抗、３１……定電流源、３２……
出力端、４１，４２……抵抗、４３……トランジ
スタ、４４〜４６……抵抗、４７，４８……トラ
ンジスタ、４９……抵抗、５０……切換スイツ
チ、５１……定電圧。
FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of one embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional example. 1...Input terminal, 2-4...Transistor, 5,
6... Resistor, 7, 8... Constant voltage source, 9... Voltage source, 10... Transistor, 11... Output end, 2
0... Signal source, 21... Input end, 22... Transistor, 23... Current source, 24-27... Transistor, 28... Constant current source, 29... Transistor, 30... Resistor, 31... Constant current source, 32...
Output end, 41, 42...Resistor, 43...Transistor, 44-46...Resistor, 47, 48...Transistor, 49...Resistor, 50...Selector switch, 51...Constant voltage.
Claims (1)
が共通に接続され、該共通エミツタに第４のトラ
ンジスタのコレクタが接続され、前記第４のトラ
ンジスタのベースは第１の抵抗を介して第１のバ
イアス回路に接続されると共に入力信号が供給さ
れ、前記第１及び第２のトランジスタのベースは
第２のバイアス回路に、前記第３のトランジスタ
のベースは第３のバイアス回路にそれぞれ接続さ
れ、前記第１、第２のトランジスタのエミツタの
面積比によつて利得差が設定された ことを特徴とする増幅器。 ２ 第１のトランジスタのエミツタ面積が第２の
トランジスタのエミツタ面積より大きい特許請求
の範囲第１項記載の増幅器。 ３ 第３のバイアス回路は、第２の抵抗、第３の
抵抗、第４の抵抗が直列接続され、第２の抵抗の
一端が電源電圧に接続され、第４の抵抗の他端が
接地され、前記第２の抵抗と前記第３の抵抗の接
続点が前記第３のトランジスタのベースに接続さ
れ、第３の抵抗と第４の抵抗の接続点に第４のト
ランジスタのコレクタが接続され、前記第４のト
ランジスタのエミツタは接地され、第４のトラン
ジスタのベースを制御端子として第４のバイアス
回路が接続された特許請求の範囲第１項または第
２項記載の増幅器。[Claims] 1. The emitters of the first, second, and third transistors are connected in common, and the collector of the fourth transistor is connected to the common emitter, and the base of the fourth transistor is connected to the common emitter. The bases of the first and second transistors are connected to a first bias circuit through a resistor and an input signal is supplied thereto, the bases of the first and second transistors are connected to a second bias circuit, and the bases of the third transistor are connected to a third bias circuit. An amplifier characterized in that the amplifier is connected to a circuit, and a gain difference is set according to the area ratio of the emitters of the first and second transistors. 2. The amplifier according to claim 1, wherein the emitter area of the first transistor is larger than the emitter area of the second transistor. 3 In the third bias circuit, a second resistor, a third resistor, and a fourth resistor are connected in series, one end of the second resistor is connected to the power supply voltage, and the other end of the fourth resistor is grounded. , a connection point between the second resistor and the third resistor is connected to the base of the third transistor, and a collector of the fourth transistor is connected to the connection point between the third resistance and the fourth resistance, 3. The amplifier according to claim 1, wherein the emitter of the fourth transistor is grounded, and a fourth bias circuit is connected to the base of the fourth transistor as a control terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27382685A JPS62132412A (en) | 1985-12-04 | 1985-12-04 | Amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27382685A JPS62132412A (en) | 1985-12-04 | 1985-12-04 | Amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62132412A JPS62132412A (en) | 1987-06-15 |
| JPH0586083B2 true JPH0586083B2 (en) | 1993-12-09 |
Family
ID=17533089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27382685A Granted JPS62132412A (en) | 1985-12-04 | 1985-12-04 | Amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62132412A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3955596B2 (en) * | 2002-09-19 | 2007-08-08 | 三菱電機株式会社 | Variable gain amplifier |
-
1985
- 1985-12-04 JP JP27382685A patent/JPS62132412A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62132412A (en) | 1987-06-15 |
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