JPH0586013B2 - - Google Patents

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Publication number
JPH0586013B2
JPH0586013B2 JP58134079A JP13407983A JPH0586013B2 JP H0586013 B2 JPH0586013 B2 JP H0586013B2 JP 58134079 A JP58134079 A JP 58134079A JP 13407983 A JP13407983 A JP 13407983A JP H0586013 B2 JPH0586013 B2 JP H0586013B2
Authority
JP
Japan
Prior art keywords
relay
selection
contact
output
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58134079A
Other languages
Japanese (ja)
Other versions
JPS6025127A (en
Inventor
Fujio Ozawa
Tadatoshi Sakane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP13407983A priority Critical patent/JPS6025127A/en
Publication of JPS6025127A publication Critical patent/JPS6025127A/en
Publication of JPH0586013B2 publication Critical patent/JPH0586013B2/ja
Granted legal-status Critical Current

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  • Relay Circuits (AREA)

Description

【発明の詳細な説明】 本発明は符号化選択信号に応じた接点出力を得
る選択リレー出力回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selection relay output circuit that obtains a contact output according to an encoded selection signal.

この種の従来回路は第1図又は第2図に示すも
のがある。第1図において、デコーダ1は符号化
選択信号をデコードして対応する選択リレー21
〜2oを少なくとも1つ駆動し、リレー21〜2o
の各接点31〜3oはコモン端子COMと出力端子
OUT1〜OUToに接続されて接点出力として取出
される。この回路において、接点出力容量(電流
しや断能力)を大きくするには各リレーに接点容
量の大きいものを使用することが考えられるが、
リレー自体の大型化で実装スペースや価格の点で
不都合が生じる。
A conventional circuit of this type is shown in FIG. 1 or 2. In FIG. 1, a decoder 1 decodes an encoded selection signal and a corresponding selection relay 2 1
Drive at least one relay 2 1 ~ 2 o
Each contact 3 1 to 3 o is the common terminal COM and output terminal
Connected to OUT 1 to OUT o and taken out as contact output. In this circuit, in order to increase the contact output capacity (current breaking capacity), it is possible to use a relay with a large contact capacity for each relay.
The larger size of the relay itself creates problems in terms of mounting space and cost.

第2図は各リレー21〜2oの接点31〜3oとコ
モン端子COM間に接点容量の大きいパワーリレ
ー4の接点41を共通の出力接点として設け、こ
のリレー4の駆動はタイミング回路5によつて第
3図に示すタイミングで制御する構成にされる。
すなわち、タイミング回路5はデコーダ1から選
択信号のタイミンナグを得手選択リレー21〜2o
の接点閉動作に遅れて接点41を閉じるようリレ
ー4を駆動し、逆に選択リレーの開動作前に接点
1を開くようリレー4を駆動し、出力電流の開
閉はリレー4の接点41に負担させることにより、
選択リレー21〜2oにはその接点に電流しや断能
力の小さいものを使用可能にする。
In Fig. 2, the contact 41 of the power relay 4 with a large contact capacity is provided as a common output contact between the contacts 31 to 3o of each relay 21 to 2o and the common terminal COM, and the drive of this relay 4 is controlled by timing. The circuit 5 is configured to control the timing shown in FIG.
That is, the timing circuit 5 receives the timing of the selection signal from the decoder 1 and sends it to the selection relays 21 to 2o.
The relay 4 is driven to close the contact 4 1 after the contact closes, and conversely, the relay 4 is driven to open the contact 4 1 before the selection relay opens, and the output current is opened and closed by the contact 4 of the relay 4. By burdening 1 ,
For the selection relays 2 1 to 2 o , it is possible to use relays with a small current breaking capacity at their contacts.

しかし、この第2図に示す回路では、タイミン
グ回路5に補助リレーやタイマなどを多数必要と
し、回路も複雑になるし、選択符号と選択リレー
とのタイミング上の関係の変更に合わせて再調整
を必要とするなど汎用性に劣るし接点41と他の
接点の協調性がくずれる恐れがあつた。
However, in the circuit shown in FIG. 2, the timing circuit 5 requires a large number of auxiliary relays and timers, making the circuit complicated, and readjustment is required in accordance with changes in the timing relationship between the selection code and the selection relay. It is inferior in versatility , as it requires a

本発明の目的は、パワーリレーと選択リレーの
動作タイミングを確実にしかも変更を容易にした
選択リレー出力回路を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a selection relay output circuit in which the operating timings of a power relay and a selection relay can be reliably changed and easily changed.

本発明は、パワーリレー及び選択リレーの制御
をマイクロコンピユータによりプログラム処理
し、各リレーの補助接点状態から夫々の接点動作
データを取込んで制御タイミング及び処理の可否
を決定することを特徴とする。
The present invention is characterized in that the control of the power relay and the selection relay is programmed by a microcomputer, and the control timing and whether or not to perform processing are determined by taking in contact operation data from the auxiliary contact state of each relay.

第4図は本発明の一実施例を示す回路構成図で
ある。パワーリレー4及び選択リレー21〜2o
その接点41を共通出力接点とし接点31〜3o
選択出力接点とした接続される。パワーリレー4
及び選択リレー21〜2oはマイクロコンピユータ
6のデイジタル出力回路7の各チヤンネル出力と
して駆動される。また、パワーリレー4及び選択
リレー21〜2oは夫々の補助接点81及び91〜9o
が接点81は単独で、接点91〜9oは並列接続で
マイクロコンピユータ6のデイジタル入力回路1
0にチヤネル接続され、夫々の接点状態すなわち
リレー4,21〜2oの動作状態がオン・オフ信号
として取込まれる。デイジタル入力回路10は選
択信号を取込むチヤネルも具える。マイクロコン
ピユータ6はデイジタル出力回路7、入力回路1
0をCPU11及びメモリ12と共にバス結合し、
CPU11はメモリ12のプログラムに従つて選
択信号に対応するリレー21〜2oを選択制御し、
その制御にパワーリレー4のタイミング制御及び
各リレーの補助接点81,91〜9oの状態データ
を取込む。
FIG. 4 is a circuit configuration diagram showing an embodiment of the present invention. Power relay 4 and selection relays 2 1 to 2 o are connected with contact 4 1 as a common output contact and contacts 3 1 to 3 o as selection output contacts. power relay 4
The selection relays 2 1 to 2 o are driven as respective channel outputs of the digital output circuit 7 of the microcomputer 6. In addition, the power relay 4 and the selection relays 2 1 to 2 o are connected to auxiliary contacts 8 1 and 9 1 to 9 o, respectively.
The contact 81 is connected alone, and the contacts 91 to 9o are connected in parallel to the digital input circuit 1 of the microcomputer 6.
0, and the state of each contact, that is, the operating state of the relays 4, 2 1 to 2 o , is taken in as an on/off signal. Digital input circuit 10 also includes a channel for receiving selection signals. The microcomputer 6 has a digital output circuit 7 and an input circuit 1.
0 is bus-coupled with the CPU 11 and memory 12,
The CPU 11 selects and controls the relays 21 to 2o corresponding to the selection signal according to the program in the memory 12,
The timing control of the power relay 4 and the state data of the auxiliary contacts 8 1 , 9 1 to 9 o of each relay are incorporated into the control.

以下、マイクロコンピユータ6の制御態様を第
3図のタイムチヤートを参照して説明する。
The control mode of the microcomputer 6 will be explained below with reference to the time chart of FIG.

デイジタル入力回路10を通して取込む選択信
号(第3図のt1)はCPU11において各選択リレ
ー21〜2oに割当てる符号と比較することで選択
されたリレーを判定する(デコード機能)。次に、
選択されたリレーに対応するチヤネル出力をデイ
ジタル出力回路7から出力させ、当該選択リレー
を駆動させる。この選択リレーの駆動により、そ
の接点状態が変化したことを入力回路10を通し
てCPU11に取込み(時刻t2)、このデータから
CPU11は出力回路7を通してパワーリレー4
の駆動制御をする。パワーリレー4の接点41
オン時には既に選択されたリレーの接点が閉じて
おり、リレー4の接点オン時(時刻t3)には出力
端子OUT1〜OUToのうちの少なくとも1つから
外部出力を得ることができる。
The selection signal (t 1 in FIG. 3) taken in through the digital input circuit 10 is compared with the code assigned to each selection relay 2 1 to 2 o in the CPU 11 to determine the selected relay (decoding function). next,
A channel output corresponding to the selected relay is outputted from the digital output circuit 7, and the selected relay is driven. By driving this selection relay, the change in the contact state is input to the CPU 11 through the input circuit 10 (time t 2 ), and from this data
The CPU 11 connects to the power relay 4 through the output circuit 7.
control the drive. When the contact 41 of the power relay 4 is on , the contact of the selected relay is already closed, and when the contact of the relay 4 is on (time t3 ), the external You can get the output.

次に、選択信号が停止されたとき(時刻t4)、
CPU11はまずパワーリレー4の駆動を停止し、
パワーリレー4の接点41が開いたことを補助接
点81の状態から判別して選択していたリレーを
駆動停止させる(時刻t3)。従つて、パワーリレ
ー4の接点開時(時刻t6)には選択リレーの接点
は未だ閉じており、パワーリレーによる外部出力
しや断をする。
Next, when the selection signal is stopped (time t 4 ),
The CPU 11 first stops driving the power relay 4,
It is determined from the state of the auxiliary contact 8 1 that the contact 4 1 of the power relay 4 is open, and the selected relay is stopped (time t 3 ). Therefore, when the contact of the power relay 4 is open (time t 6 ), the contact of the selection relay is still closed, and the external output by the power relay is cut off.

従つて、本発明によれば、選択リレーの接点に
共通に直列接続のパワーリレー接点を設け、外部
出力の開閉にはパワーリレー接点の開閉で行な
い、選択リレーの接点は外部出力を選択する選択
リレー出力回路において、パワーリレー及び選択
リレーの駆動条件及びタイミング処理にはパワー
リレー及び選択リレーの補助接点の状態から得る
ため、簡単なプログラムにして確実なタイミング
での制御を可能にする。また、マイクロコンピユ
ータは外部出力対象機器の制御中枢部として機能
させる場合にはリレー制御及びデコード機能をそ
の一部機能として持たせ、リレー出力回路の制御
手段を特別に用意する必要性を解消する。
Therefore, according to the present invention, a power relay contact connected in series is provided in common to the contacts of the selection relay, and the external output is opened and closed by opening and closing the power relay contact, and the contact of the selection relay is used to select the external output. In the relay output circuit, the drive conditions and timing processing of the power relay and selection relay are obtained from the states of the auxiliary contacts of the power relay and selection relay, so a simple program can be used to control with reliable timing. Furthermore, when the microcomputer functions as a control center of an external output target device, it is provided with relay control and decoding functions as part of its functions, thereby eliminating the need for a special control means for the relay output circuit.

なお、実施例において、選択リレーの補助接点
は並列接続で共通入力としているが、これは補助
接点状態データを個別に取込む構成にして一層正
確な制御を可能にする。
In the embodiment, the auxiliary contacts of the selection relays are connected in parallel and used as a common input, but a configuration in which the auxiliary contact state data is individually taken in enables more accurate control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来の選択リレー出力回路
図、第3図は第2図及び第4図におけるタイムチ
ヤート、第4図は本発明の一実施例を示す回路図
である。 21,22,2o……選択リレー、4……パワー
リレー、6……マイクロコンピユータ、7……デ
イジタル出力回路、81……パワーリレーの補助
接点、91、92,9o……選択リレーの補助接点、
10……デイジタル入力回路、11……CPU、
12……メモリ。
1 and 2 are conventional selection relay output circuit diagrams, FIG. 3 is a time chart in FIGS. 2 and 4, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. 2 1 , 2 2 , 2 o ... selection relay, 4 ... power relay, 6 ... microcomputer, 7 ... digital output circuit, 8 1 ... power relay auxiliary contact, 9 1 , 9 2 , 9 o ...Selection relay auxiliary contact,
10...Digital input circuit, 11...CPU,
12...Memory.

Claims (1)

【特許請求の範囲】[Claims] 1 符号化選択信号に応じて複数の選択リレーの
うちの少なくとも1つを駆動して当該選択リレー
の接点出力を外部出力として得る選択リレー出力
回路において、上記選択リレーの各接点に共通に
直列接続した大容量接点を有するパワーリレー
と、このパワーリレーと上記選択リレーを駆動で
きる出力回路及び該パワーリレーと選択リレーの
補助接点の動作状態を入力できる入力回路を有す
るマイクロコンピユータとを含み、このマイクロ
コンピユータは符号化選択信号に応じて上記選択
リレーを選択駆動及び駆動停止し、この駆動時間
内にパワーリレーを駆動するよう上記補助接点の
動作状態によつて制御する構成にしたことを特徴
とする選択リレー出力回路。
1. In a selection relay output circuit that drives at least one of a plurality of selection relays in response to a coded selection signal and obtains the contact output of the selection relay as an external output, the selection relay is commonly connected in series to each contact of the selection relay. The microcomputer includes a power relay having large-capacity contacts, an output circuit capable of driving the power relay and the selection relay, and an input circuit capable of inputting operating states of the auxiliary contacts of the power relay and the selection relay. The computer selectively drives and stops driving the selection relay in response to the encoded selection signal, and controls the power relay to drive within this driving time based on the operating state of the auxiliary contact. Selective relay output circuit.
JP13407983A 1983-07-21 1983-07-21 Selective relay output circuit Granted JPS6025127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13407983A JPS6025127A (en) 1983-07-21 1983-07-21 Selective relay output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13407983A JPS6025127A (en) 1983-07-21 1983-07-21 Selective relay output circuit

Publications (2)

Publication Number Publication Date
JPS6025127A JPS6025127A (en) 1985-02-07
JPH0586013B2 true JPH0586013B2 (en) 1993-12-09

Family

ID=15119905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13407983A Granted JPS6025127A (en) 1983-07-21 1983-07-21 Selective relay output circuit

Country Status (1)

Country Link
JP (1) JPS6025127A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586912B1 (en) 2002-01-09 2003-07-01 Quallion Llc Method and apparatus for amplitude limiting battery temperature spikes

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442271U (en) * 1987-09-08 1989-03-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442271U (en) * 1987-09-08 1989-03-14

Also Published As

Publication number Publication date
JPS6025127A (en) 1985-02-07

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