JPH058558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal synthesis device that is suitably used when transmitting a large amount of numerical data, such as a dimming signal in a dimming device, between different models. .

BACKGROUND TECHNOLOGY In recent years, when lighting a stage or a television studio, etc., data on lighting conditions corresponding to the progress of the scene is input and stored in advance using potentiometers, etc. A storage dimming device or the like that reads and executes this information is used. In such a storage light control device, a light control console in which the potentiometer and the like are arranged;
The transmission of the dimming signal to and from the dimming unit is carried out by a so-called multiplex transmission device. A typical conventional example of such a transmission device is shown in FIG.

FIG. 10 is a block diagram showing the configuration of a conventional light control device. Referring to FIG. 10, the dimming operation console 1 has a plurality of faders F1 to Fn (indicated by reference mark F when collectively referred to as F) for setting the dimming level of the lighting load, and selects the fader F. multiplexer 2 for deriving a dimming signal to the transmission line l1.
and a selection means 3 for inputting a fader selection signal for selecting the fader F into the multiplexer 2 and outputting a signal for selecting the lighting load to be dimmed to the transmission line 12.

Via the transmission lines l1 and l2, the light control console 1
The dimmer panel B1 connected to the dimmer panel B1 has a signal conversion circuit 4 which receives a dimming signal and a lighting load selection signal and converts these serial signals into parallel signals, and a signal converter circuit 4 which receives the parallel-converted dimming signal and converts the serial signals into parallel signals. , and a drive circuit C1 that drives the selected lighting loads CH1 to CH40 at dimming levels. The parallel-converted dimmer signal output from the signal conversion circuit 4 is used by a driving circuit C2 that drives the lighting loads CH41 to CH80 of the dimmer panel B2 and a lighting load of the dimmer panel B3.
It is also given to the drive circuit C3 of CH81 to CH120.

FIG. 11 is a timing chart illustrating the operation of the light control device shown in FIG. 10. FIG. 11 1 shows the fader selection signal output from the selection means 3 to the multiplexer 2, FIG. 11 2 shows the dimming signal level derived from the multiplexer 2 via line l1, and FIG. Represents a lighting load selection signal for selecting a lighting load CH. 1st
1. Reference symbols f1 to f9 in FIG. 1 indicate addresses of selected faders F1 to F9, and reference symbols ch1 to ch64 in FIG. 11 indicate numbers of selected lighting loads CH1 to CH64.

On the other hand, when a fader selection signal indicating the addresses f1 to fn of the faders F1 to Fn as shown in FIG. Then, faders F1 to Fn are selected, and the 11th fader set by the selected faders F1 to Fn is selected.
A dimming signal as shown in FIG. 2 is output on line l1. On the other hand, the selection means 3 outputs a fader selection signal and selects the selected lighting load CH1.
The number data ch1 to chn of ~CHn are transmitted to the dimmer panel B1 as serial data as shown in FIG.

In the dimmer panel B1, these signals are parallel-converted by the signal conversion circuit 4, and the lighting loads Ch1 to CH120 selected by the drive circuits C1 to C3 included in the dimmer panels B1 to B3 are controlled according to the set adjustment. Driven by light level.

In the conventional dimmer device as described above, a plurality of dimmer panels B1 to B3 are connected to a single dimmer console 1 and controlled.

On the other hand, in the case of stage lighting, etc., there is a case where changing lighting, such as electric light, is inserted during the reproduction lighting operation according to the preset lighting data and its development procedure as described above. Conceivable. In such a case, it is generally necessary to use a plurality of dimmer consoles, such as a dimmer console used to control the reproduction illumination, and a dimmer console used to control the electric lights. In such a case, in the conventional light control device as described above, when attempting to synthesize the serial signals transmitted from each light control console 1, the signal conversion circuit 4 converts them into parallel signals and then synthesizes them. There was no other way, and it required an unnecessarily complicated procedure. Therefore, there has been a need for a signal synthesis device that can easily synthesize signals from a plurality of dimming consoles.

Purpose It is an object of the present invention to solve the above-mentioned problems, to have a simple configuration, and to transmit transmission signals of a plurality of different scenes.
It is an object of the present invention to provide a signal synthesis device that can perform synthesis in synchronization with a desired mode and has significantly improved usability.

Structure of the Invention The present invention includes a first receiving means 11 that receives a first data signal and a first address signal corresponding to the first data signal; a second receiving means 12 for receiving a second address signal corresponding to the first data signal to be combined with the data signal; storage means for storing the first data signal at the address indicated by the address signal, and reading out the first data signal stored at the address specified by the second address signal in response to the output of the second receiving means 12; , a first data signal read out from the storage means each time the second reception means receives the second data signal and the second address signal in response to each output of the second reception means 12 and the storage means. and a signal synthesizing means 29 that performs a synthesis operation with a second data signal.

Embodiment FIG. 1 is a block diagram showing the basic configuration of the present invention. The basic configuration of the present invention will be explained with reference to FIG. The dimming device 10, which is a signal synthesis device, includes a serial signal receiving device 11, which receives a serial signal including an analog signal such as dimming level data via lines l3 and l4.
12 and the address data (serial data) of the dimmer, which will be described later, via lines l5 and l6 are received by period detecting devices 13 and 14, and in response to signals from the period detecting devices 13 and 14, for example, random access is performed. A write address setting means 16 that sets a write address for the storage unit 15 realized by a memory (RAM), etc., and a read address setting means 17 that similarly sets a read address.
, a serial signal transmitting device 18 that combines and transmits the stored content read from the storage unit 15 and the serial signal from the serial signal receiving device 12, and a light control device outputted from the transmitting device 18 via line l7, for example. A distributor 20 realized by, for example, a plurality of sample and hold circuits, to which an analog signal such as level data and an address signal such as the address of a plurality of dimmers 19 are inputted via a line l8. and the dimmer 1, which is individually connected to generally a plurality of lighting loads 21 and energizes them to realize dimming control.
9.

FIG. 2 is a block diagram showing a specific configuration of a light control device 10a according to an embodiment according to the basic configuration shown in FIG. Referring also to FIG. 2, the light control device 10
The configuration of a will be explained. In this specific example, the serial signal receiving devices 11 and 12 are connected to lines l3 and l.
4, respectively, and serial/parallel converters 24, 25 connected to lines 15, 16, respectively.

Further, the period detecting devices 13 and 14 are inputted with parallel signal outputs from the serial/parallel converters 24 and 25, and signals serving as comparison standards are inputted with the comparison value setting means 26 and 27. Comparators 28 and 28a each perform a comparison operation.
It consists of the following.

The data output from the analog/digital converter 22 is input, and the serial/parallel converter 2
A storage section 15 is provided which takes as an address setting signal a signal from a write address setting means 16 realized by a counter or the like which performs a counting operation by using the parallel signal as a clock input every time a parallel signal is input from the memory section 4.

Further, the serial signal transmitting device 18 transmits the stored contents of the storage section 15 read out by the address output from the read address setting means 17, which is realized by a counter similar to the write address setting means 16, and the analog/digital converter. 13, a signal synthesis means 29 having a configuration as described below which synthesizes these signals, a digital/analog converter 30 which converts the digital output of the signal synthesis means 29 into an analog output, and a read address. The circuit includes a parallel/serial converter 31 for converting a parallel signal, which is the clock output of the setting means 17, into a serial signal.

On the other hand, the serial/parallel converters 24, 2
The outputs of the comparators 28 and 28a are applied to the clock input terminals of the write address setting means 16 and the read address setting means 17 via the lines l9 and l10, and the output signals of the comparators 28 and 28a as described later are applied to the lines l11 and l12. is applied to the reset input terminals of write address setting means 16 and read address setting means 17 via. Also digital/
Analog signals such as dimming level data are transmitted to the line l13 that connects the analog converter 30 and the distributor 20, and the line l1 that connects the parallel/serial converter 31 and the distributor 20
4, a serial signal such as an address signal for selecting the address of the dimmer 19 is transmitted via the distributor 20.

FIG. 3 is a block diagram showing a specific example of the signal combining means 29. That is, the signal combining means 29
In, read data K from the storage unit 15,
The output data F from the analog/digital converter 23 is subjected to the calculation (K+F) by the adder 32, and this is output.

FIG. 4 is a block diagram showing another example of the configuration of the signal combining means 29. The signal synthesizing means 29 of this configuration example receives the data K and F as described with reference to FIG. Ru. The comparator 33 outputs, for example, logic "1" when K≧F...(1), and outputs logic "0" when K<F...(2), and this output signal "1". , "0" causes the data selector 34 to output data K and F, respectively, in the case of the first equation or the second equation. This makes it possible to realize a synthesis process in which the maximum value of data K and F is selected.

FIG. 5 is a timing chart showing the operation of the light control device 10a shown in the second figure. The operation of the present light control device 10a will be explained with reference to FIGS. 2 and 5. As described above, the illumination level data is transmitted from the lines 13 and 14 for each dimmer 19. Therefore, as shown in FIGS. 1 and 2, on lines l3 and l5, level signals A having levels LV1, LV2, . Address signal DIMi (i = 1, 2, ..., n) that individually specifies
The signal is provided to the serial signal receiving device 11 in synchronization with the serial signal receiving device 11.

At this time, the serial/parallel converter 24 outputs pulses as shown in FIG. 5 at times t1, t2, and t3 when the serial signal is input, and inputs the pulses as the clock signal C to the write address setting means 16. On the other hand, the comparator 28 is set to data "0" by the comparison value setting means 26, and the output data from the serial/parallel converter 24 is "0" and "1" as shown in FIG. ”,
When given in the order of "2", ..., "n-1",
At the time when the data "0" is input (time t2 in this embodiment), the reset signal D shown in FIG.
is output, and the write address setting means 16 is reset.

The storage unit 15 includes a write address setting means 16.
The dimming level signal A shown in FIG. 1 is written in synchronization with the write address signal E shown in FIG. 5 from FIG. 5 and stored at a predetermined address.

Next, when attempting to read out the dimming data stored in the storage section 15, the analog/digital converter 23, A read address setting means 17 having the same configuration and operation as the write address setting means 16, which is operated by the serial/parallel converter 25, the comparison value setting means 27, and the comparator 28a, reads data to the storage section 15. The address is output, and thereby the dimming data at a predetermined address in the storage section 15 is read out.

Lines 13 and 15 are connected to a certain dimmer console, and lines 14 and 16 are connected to another different dimmer console. That is, in this embodiment, when inputting various dimming data into the storage unit 15 by one of the dimming consoles and reading and reproducing the data, signals from the other dimming console are input to the storage unit 15. This is an attempt to realize synthetic reproduction control.

When performing such a signal combining operation, the dimming level data F shown in FIGS. 5 and 7 and the address signal G are applied to the serial signal receiving device 12 via lines 14 and 16. The read address setting means 17 performs a counting operation based on the clock signal H shown in FIG.
The counting operation is reset based on the reset signal I shown in FIG.

From this read address setting means 17, the fifth
The address data for each dimmer 19 shown in FIG. 10 is output as parallel data, and based on this, the read data K shown in FIG.
is output. At this time, for example, in the address data G of the dimmer 19, the transmission end time a2 of the data DIM1 and the transmission end time b of the level data LV1 of the dimmer 19 corresponding to the address DIM1.
In the synthesizable period T1 shown in FIG. 5 12 between the data LVi (i=1, 2, . . .
The currently input dimming level data F shown in FIG. 6 can be synchronized and synthesized. Thereafter, data is synthesized in the same manner. This synthesis work may be performed using the addition circuit 32 and maximum value detection circuit described with reference to FIGS. 3 and 4.

Therefore, from the signal combining means 29 shown in the second figure, the combined level data N shown in FIG.
is output, and a desired dimmer 19 is selected in synchronization with the address signal of the read address setting means 17 which is output to the parallel/serial converter 31, thereby lighting up the dimmer 19.

According to this embodiment as described above, lines l3,
Input of dimming data via l5 and lines l4 and l6 is performed at completely different timings, and despite this, in this embodiment, such multiple types of input data can be easily synthesized and It is possible to output in a synchronized state.

FIG. 6 is a block diagram of a second specific example of a light control device 10b based on the basic configuration shown in FIG. This embodiment is similar to the previous embodiment, and corresponding parts are given the same reference numerals. What should be noted about this embodiment is that compared to the configuration shown in the second figure, the period detection device 1
3, 14, the configuration is such that the write address setting means 16 and the read address setting means 17 are excluded, and the output of the serial/parallel converter 24 of the serial signal receiving device 11 is given to the storage section 15, and the address signal via line l6 is is converted into a parallel signal by the serial/parallel converter 25 and then directly applied to the storage section 15.

Further, the data signal via line l4 is input to the signal combining means 29 of the serial signal transmitting device 18, and the read data from the storage section 15 is input to the digital/analog converter 30 of the serial signal transmitting device 18.
After being input into the signal generator and converted into an analog signal, the signal is input to the signal synthesizing means 29 as the other input.

FIG. 7 is a circuit diagram showing a specific example of the signal synthesizing means 29 shown in FIG. In the configuration example shown in FIG. 7, the signal synthesizing means 29 includes an amplifier OP1 to which an analog signal from a digital/analog converter 30 is input via a resistor R1, and a data signal from a line l4 to the amplifier OP1. In this case, it is configured to include a resistor R2 interposed in series. The output of the amplifier OP1 is V0 as follows: V0=V1+V2 (3), and the signals are synthesized by this.

FIG. 8 is a circuit diagram showing another specific example of the signal synthesizing means 29. The signal synthesizing means of the present invention includes two diodes D1 and D connected in parallel.
Consists of 2. That is, the analog signals V1 and V2 similar to that in FIG.
They are input to the anodes of D2, respectively, and the cathodes of diodes D1 and D2 are combined at a connection point 36 to obtain a combined output V0. In other words, in the state shown in Figure 8, the following output is obtained: V0 = MAX (V1, V2) (4). The signal synthesis function can also be achieved with such a circuit configuration.

FIG. 9 is a timing chart explaining the operation of the light control device 10b shown in FIG. The operation of the light control device 10b of this embodiment will be described with reference to FIGS. 6 and 9. The analog data signal via the line l3, through which the dimming level data is transmitted, is converted into a digital signal by an analog/digital converter 22. On the other hand, the serial address signal specifying the lighting load 19 is
Serial/parallel converter 2 via line l5
4 and is applied to the storage section 15 as a parallel signal shown in FIG. 92, and the data signal shown in FIG. 91 is stored at a predetermined address. Each time address data is received by the serial/parallel converter 24 in this way, the digitally converted dimming level data shown in FIG. 9 is written into the address indicated by the data.

During the read operation from the storage section 15, the line l
The address data G of the dimmer 19 shown in FIG. The dimming data at the address is read out as shown in FIG. 9 and converted into an analog signal by the digital/analog converter 30.

The dimming level data F from another dimming control console as shown in FIG. 94 is read out from the storage unit 15 based on the address data G as shown in FIG. The stored contents are synthesized by the signal synthesizing means 29 having the configuration example described with reference to FIGS. 7 and 8, and a synthesized output as shown in FIG. 9 is obtained.

That is, even with the configuration and operation of this embodiment, signals from a plurality of different light control consoles can be easily combined and output. Further, this embodiment differs from the configuration of the first embodiment described above with reference to FIG. 2 in the following points. In other words, in the first embodiment, since the cycle detection devices 13 and 14 are used, by changing the comparison value set by the comparison value setting means 16 and 17, it is possible to set the comparison value at any time in one cycle. Writing to storage unit 15/
The read operation can be stopped. As a result, transmission can be performed at a cycle shorter than the original cycle (n in this embodiment). Also, the storage unit 15
If the address setting means 17 is made into a table of operation contents of various frequency dividers, etc. in a read-only memory (ROM), for example, it is possible to synthesize arbitrary different signals.

On the other hand, the second embodiment has a somewhat simplified configuration compared to the first embodiment, and therefore the basic operation used by the present invention can be realized, but the first embodiment It is no longer possible to change the transmission cycle or change the addresses of signals to be combined, which were previously possible. However, since the configuration is much simpler than that of the first embodiment, it can be suitably used when the configuration is to be significantly downsized.

Effects As described above, according to the present invention, the first receiving means 1
1 receives a first data signal and a first address signal corresponding to the first data signal, thereby causing the storage means to store the first data signal in the first address signal. The second receiving means 12 stores the address of the storage means at which the second data signal and the first data signal to be combined with the second data signal are stored. The storage means reads out the first data signal stored at the address specified by the second address signal, and the signal synthesis means receives the second data signal representing the second address signal. Each time a second data signal and a second address signal are received by the means, the first data signal read from the storage means by the second address signal;
, for example, addition or maximum value detection. In this way, even if the transmission timings of the first and second data signals are completely different, they can be combined and output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, and FIG. 2 is a light control device 10a according to an embodiment of the present invention.
3 is a block diagram showing one specific example of the signal synthesizing means 29, FIG. 4 is a block diagram showing another specific example of the signal synthesizing means 29, and FIG. 5 is a block diagram showing the configuration of the light control device 10a. 6 is a block diagram showing the configuration of a light control device 10b according to another embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of the signal synthesizing means 29 in this embodiment. FIG. 8 is a circuit diagram showing another configuration example of the signal synthesizing means 29, FIG. 9 is a timing chart explaining the operation of FIG. 6, and FIG. 10 is a block diagram explaining the configuration of a typical prior art. FIG. 11 is a timing chart illustrating the operation of the configuration shown in the first diagram. 10, 10a, 10b... Light control device, 11, 1
2...Serial signal receiving device, 13, 14...Synchronization detection device, 15...Storage unit, 16...Write address setting means, 17...Reading address setting means, 18...Serial signal transmitting device, 22... Addition circuit, 23..., 26... Comparison value setting means, 2
8... Comparator, 29... Signal synthesis means, 34...
Data selector, OP1...Amplifier, D1, D2
……diode.

Claims (1)

[Claims] 1. A first device receiving a first data signal and a first address signal corresponding to the first data signal.
receiving means 11; second receiving means 12 for receiving a second data signal and a second address signal corresponding to the first data signal to be combined with the second data signal; and first receiving means. In response to the output of the second receiving means 12, the first data signal is stored at the address indicated by the first address signal, and in response to the output of the second receiving means 12, the first data signal is stored at the address indicated by the second address signal. a storage means for reading out a first data signal stored in the storage means; and a storage means for reading a first data signal stored in the second reception means 12 and a second address signal from the second reception means in response to each output of the second reception means 12 and the storage means. A signal synthesizing device characterized in that it includes a signal synthesizing means 29 that performs a synthesizing operation on a first data signal read from a storage means and a second data signal every time it is received.