JPH05851B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a MIS type semiconductor device.

(b) Background of the technology In recent years, in MOS semiconductor ICs, the channel length has become extremely short in order to improve the operating speed, and the area of the transistor region has also been extremely miniaturized in order to improve the degree of integration. It's coming.

(c) Prior art and problems Conventional MOS transistors usually had a structure as shown in FIG. In the same figure, 1
is a p-type silicon (Si) substrate, 2 is a field insulating film, 3 is a gate oxide film, 4 is an N ⁺ type Si gate electrode,
5 is an N ⁺ type source region, 6 is an N ⁺ type drain region,
7 is a phosphosilicate glass (PSG) membrane, 8 is an electrode window,
9 is a source extraction electrode, 10 is a drain extraction electrode, 11 is a channel region, L is a channel length, and X _j
indicates the junction depth of the source/drain region.

In such a conventional structure, the source/drain regions 5 and 6 are arranged on the side surface of the channel region 11, and the depth X _j is also relatively deep (>0.3 [μm]).
It is formed. Therefore, when the channel length L becomes 1 [μm] or less, the threshold voltage Vth of the MOS transistor shows a steep downward curve due to the generally known short channel effect. Therefore, a slight change in the channel length due to dimensional errors in the formation of the gate electrode 4 and the source/drain regions 5 and 6 causes Vth to fluctuate.
It has been extremely difficult to form transistors.

The above channel effect can be improved by making X _j shallower, but in the conventional structure, if X _j is made shallower than the above value, the sheet resistance of the source/drain regions 5 and 6 will increase, and the device characteristics will be affected in this respect. be damaged.

Further, in the above conventional structure, an electrode window 8 is formed in the insulating film, for example, the PSG film 7 on the source/drain regions 5 and 6.
Aluminum (A) is formed through the electrode window 8.
) and the like are formed. Therefore, the electrode window 8
In consideration of alignment errors and side etching during formation, it is usually necessary to provide an interval of about 3 [μm] or more between the gate electrode 4 and the electrode window 8. Therefore, there is a problem in that the area of the element region is expanded, and high integration of the elements is hindered.

(d) Object of the Invention An object of the invention is to provide a MOS transistor having a source/drain region with a junction depth of almost 0 and a method for manufacturing the same, thereby eliminating the above-mentioned problems.

(e) Structure of the Invention That is, the present invention comprises a step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, and a step of forming an oxidizing material on a region where a gate electrode is to be formed on the gate insulating film. A step of forming a temporary pattern having a substantially vertical side surface and an oxidation-resistant film on the top thereof, and oxidizing the side surface of the temporary pattern using the oxidation-resistant film as a mask to form a temporary pattern on the side surface of the temporary pattern. a step of forming a sidewall oxide film; a step of removing the oxidation-resistant film and the gate insulating film exposed on the base; a step of removing the temporary pattern while leaving the sidewall oxide film; and a step of removing the temporary pattern on the base. a gate electrode formation region surrounded by the sidewall oxide film and the gate oxide film;
A second conductivity type semiconductor layer is formed in the source/drain formation regions on both sides of the gate electrode formation region, thereby forming a gate electrode and a source/drain region electrically isolated from the gate electrode by the sidewall oxide film. The present invention relates to a method of manufacturing a semiconductor device, comprising a step of forming a drain region.

(f) Embodiments of the Invention The present invention will be described below with reference to the cross-sectional structural diagram of one embodiment shown in FIG. 2, the process cross-sectional diagrams shown in FIGS. This will be explained in detail using

A MOS type semiconductor formed by the method of the present invention has a structure as shown in FIG. 2, for example.

In the figure, 21 is a p-type silicon (Si) substrate,
22 is a field oxide film, 23 is a gate oxide film,
26 is aluminum oxide (Al ₂ O ₃ ) film, 28 is
N ⁺ type Si source region, 29 N ⁺ type Si drain region, 30 N ⁺ type Si gate electrode, 31 phosphosilicate glass (PSG) insulating film, 33 source wiring, 3
4 indicates a drain wiring.

When forming a MOS type semiconductor device having the above structure, in the method of the present invention, for example, as shown in FIG. A field oxide film 22 is formed to expose the surface, and then thermal oxidation is applied to the surface of the element formation region of the Si substrate 21.
A gate oxide film 23 having a normal thickness of about 500 Å is formed. Next, an oxidizing material such as an aluminum (Al) layer with a thickness of about 5000 [Å] is formed on the main surface by a vapor deposition method or the like, and then the Al layer is formed by a normal chemical vapor deposition (CVD) method. thickness on top
An oxidation-resistant film, such as a silicon nitride (Si ₃ N ₄ ) film, with a thickness of about 1000 Å is formed. Next, the Si ₃ N ₄ film and Al
The layers are sequentially patterned to the desired width and the top
Al temporary pattern 25 with Si ₃ N ₄ oxidation resistant film 24
form.

Next, using the Si ₃ N ₄ oxidation-resistant film 24 as a mask, the side surface of the Al temporary pattern 25 is selectively oxidized by a desired method such as hot water oxidation, plasma oxidation, or anodic oxidation, which is commonly used, as shown in FIG. 3B. For example, 3000 to 5000 [Å] on the side surface of the Al temporary pattern 25.
Aluminum oxide (Al ₂ O ₃ ) film 26 with a thickness of
form. Note that the width of the temporary pattern including the Al ₂ O ₃ film 26 becomes the gate length when the device is completed.
Therefore, during patterning in the previous step, the width of the temporary Al pattern 25 must be made narrower than the gate length by an amount corresponding to the increase due to oxidation.

Next, Si ₃ N ₄ oxidation-resistant film 2 was formed using hot phosphoric acid (H ₃ PO ₄ ).
4, ammonium fluoride (NH ₄ F) + hydrofluoric acid (HF)
The gate oxide film 23 exposed on the sides of the temporary pattern is selectively etched away using the system liquid, and the Al temporary pattern 2 is formed as shown in FIG. 3C.
p-type Si substrate 21 on the top surface of 5 and on the side of the temporary pattern
express it. Note that the Si ₃ N ₄ oxidation-resistant film 24 and gate oxide film 23 may be removed by dry etching. Also, it does not matter which order comes first.

Next, the Al temporary pattern 25 is dissolved and removed using an ordinary aluminum etching solution consisting of potassium hydroxide (KOH) solution, hydrochloric acid (NCl), phosphoric acid (H ₃ PO ₄ ), etc., as shown in FIG. 2D. 5000 to
A gate oxide film 23 having a wall-like Al ₂ O ₃ film 26 having a height of about [Å] and a thickness of about 3000 to 5000 [Å] on its edge is formed.

Next, as shown in Fig. 3 E, a normal high-temperature vapor phase growth method is carried out at a temperature of about 1000 [°C] in monosilane (SiH ₄ ) at a reduced pressure of about 10 [Torr].
A non-doped film having a thickness of, for example, about 5000 [Å] so that only the upper part of the wall-like Al ₂ O ₃ film 26 is exposed on the main surface.
A Si layer 27' is formed. In this vapor phase growth, the Si layer 27 is not deposited on the upper surface of the extremely narrow wall-shaped Al ₂ O ₃ film 26, but on the gate oxide film 23 sandwiched between the Al ₂ O ₃ films 26. On the p-type Si substrate 21 exposed to the side of the gate oxide film 23 and on the field oxide film 2
Deposit on 2.

Next, as shown in Figure 3, arsenic ions (As ⁺ ) are implanted into the Si layer at a high concentration under conditions of, for example, 150 [KeV], 4×10 ¹⁵ [atm/cm ³ ], and 30 [minutes]. After the implantation, annealing treatment is performed at about 1050 [°C] to transform the Si layer into an N ⁺ type Si layer 27 having a high As concentration of about 10 ²¹ [atm/cm ³ ] and high electrical conductivity. do. Note that the above annealing treatment is not performed at this point.
Generally, this is done at the same time as reflowing the side surface of the contact window formed on the phosphosilicate glass (PSG) film in the later process, but for the sake of explanation, in this example, annealing is performed at the above point. Processing is in progress. Further, the N ⁺ type Si layer 27 becomes a polycrystalline layer on the oxide film as is known in the art, but it is not particularly necessary to form it into a single crystal layer.

Next, as shown in Figure 3, the normal photo
The N ⁺ type Si layer 27 is patterned by an etching method to form an N ⁺ type Si source region 28 and an N ⁺ type Si drain region 29. Note that the N + type Si layer deposited on the gate oxide film 23 while being separated from the source region 28 and drain region 29 by the wall-shaped Al ₂ O ₃ film 26 becomes the N ^{+ type} Si gate electrode 30. .

Thereafter, a PSG insulating film 31 is formed on the main surface as shown in FIG.
A contact window 32 is formed in the PSG insulating film 31,
After performing a reflow process on the side surface of the contact window 32, a source wiring 33, a drain wiring 34, etc. made of Al or the like are formed. Although not shown, a cover insulating film is formed on the main surface, and a MOS type semiconductor device according to the method of the present invention is provided.

FIG. 4 shows a structure in which the N ⁺ type Si source region 28 and the N ⁺ type Si drain region 34 are extended out onto the field oxide film 22 and used for the lead electrode wiring. Each symbol in the figure is It represents the same area as FIG.

(g) Effects of the Invention In the MOS type semiconductor device formed by the method of the present invention shown in the above embodiments, the source and drain regions are arranged on the semiconductor substrate in parallel with the gate, so short channel effects are avoided. The junction depth of the effective source/drain regions becomes 0.

Therefore, according to the present invention, the channel length is [μm]
Even in the following high-speed MOS transistors, the threshold voltage Vth does not decrease.

Further, according to the present invention, the gate and the source/drain regions, which also function as electrodes, are self-aligned via a thin insulating film, so that the device area can be reduced.

As is clear from the above explanation, the present invention
It is effective for increasing the speed and integration of MOSIC.

In the method of the above embodiment, the temporary pattern corresponding to the gate electrode is not limited to a metal material such as aluminum, but may also be formed of a semiconductor material such as silicon.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional MOS transistor.
FIG. 2 is a sectional view of an embodiment of a MOS type semiconductor device formed by the method of the present invention, and FIGS. Figure 4 shows a modified example. In the figure, 21 is a p-type silicon substrate, 22 is a field oxide film, 23 is a gate oxide film, 24 is a silicon nitride oxidation-resistant film, 25 is an aluminum temporary pattern, 26 is an aluminum oxide film, and 27' is an aluminum oxide film.
N ⁺ type silicon layer, 27 is N ⁺ type silicon layer, 28
29 is an N ⁺ type silicon source region, 29 is an N ⁺ type silicon drain region, 30 is an N ⁺ type silicon gate electrode, 31 is a phosphosilicate glass insulating film, 32 is a contact window, 33 is a source wiring, and 34 is a drain Shows the wiring.

Claims (1)

[Scope of Claims] 1. A step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, the gate insulating film is made of an oxidizing material, is formed in a region where a gate electrode is to be formed on the gate insulating film, and the side surfaces of the gate insulating film are substantially vertical. forming a temporary pattern having a shape of a step of removing the oxidation-resistant film and the gate insulating film exposed on the base; a step of removing the temporary pattern leaving the sidewall oxide film; and a step of removing the temporary pattern on the sidewall on the base. A second layer is formed in the gate electrode formation region surrounded by the oxide film and the gate oxide film, and in the source/drain formation regions on both sides of the gate electrode formation region.
A semiconductor device comprising a step of forming a gate electrode and a source/drain region electrically isolated from the gate electrode by the sidewall oxide film by forming a conductive semiconductor layer. Production method.