JPH0584519B2 - - Google Patents
Info
- Publication number
- JPH0584519B2 JPH0584519B2 JP60063414A JP6341485A JPH0584519B2 JP H0584519 B2 JPH0584519 B2 JP H0584519B2 JP 60063414 A JP60063414 A JP 60063414A JP 6341485 A JP6341485 A JP 6341485A JP H0584519 B2 JPH0584519 B2 JP H0584519B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- transparent
- mask
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 13
- 239000010408 film Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ドツトマトリツクス液晶表示用スイ
ツチングデバイスの絵素電極の形成法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a picture element electrode of a switching device for a dot matrix liquid crystal display.
（従来の技術）
近年、ドツトマトリツクス液晶表示は、薄膜表
示デバイスとして、注目を浴びている。(Prior Art) In recent years, dot matrix liquid crystal displays have attracted attention as thin film display devices.
以下図面を参照しながら、従来の絵素電極形成
法を説明する。第２図ａ，ｂは、スイツチングデ
バイスに、非晶質シリコンを用いた薄膜トランジ
スタ（TFT）を形成した液晶用表示絵素の断面
図と平面図を示したものである。１は絶縁性ガラ
ス基板、２はゲート電極、３はゲート絶縁体、４
は非晶質シリコン、７ａ，７ｂはそれぞれドレイ
ン電極およびソース電極、８は絵素電極である。
このスイツチングデバイスの絵素電極８の形成方
法は、TFTを形成後、ITO（インジウム・スズ酸
化物）を基板全面に成膜しマスクを用いて通常の
フオトリソグラフイにより所定の形状にパターニ
ングする。（1983年、ジヤパンデイスプレイ
（Japan Display）第356頁参照）
（発明が解決しようとする問題点）
しかしながら従来のような構成では、通常のマ
スクを使用する限り、絵素開口率を上げようと
し、ゲート走査電極バスバー幅を狭くしていく
と、絵素電極のパターニング精度を保つための条
件が厳しくなるという問題点を有していた。 A conventional picture element electrode forming method will be described below with reference to the drawings. FIGS. 2a and 2b show a cross-sectional view and a plan view of a liquid crystal display picture element in which a thin film transistor (TFT) using amorphous silicon is formed as a switching device. 1 is an insulating glass substrate, 2 is a gate electrode, 3 is a gate insulator, 4
is amorphous silicon, 7a and 7b are drain and source electrodes, respectively, and 8 is a picture element electrode.
The method for forming the pixel electrode 8 of this switching device is to form a TFT, then form a film of ITO (indium tin oxide) on the entire surface of the substrate, and pattern it into a predetermined shape by ordinary photolithography using a mask. . (See Japan Display, 1983, p. 356) (Problems to be solved by the invention) However, in the conventional configuration, as long as a normal mask is used, attempts are made to increase the pixel aperture ratio. As the width of the gate scanning electrode bus bar is made narrower, there is a problem in that the conditions for maintaining the patterning accuracy of the picture element electrode become stricter.
本発明は上記問題点に鑑み、ゲート電極幅を細
くしても、絵素電極のパターニング精度を考慮せ
ず、任意の形状にパターニングできる絵素電極形
成法を提供するものである。 In view of the above-mentioned problems, the present invention provides a method for forming a picture element electrode that can be patterned into an arbitrary shape even if the width of the gate electrode is made thin without considering the patterning accuracy of the picture element electrode.
（問題点を解決するための手段）
上記の問題点を解決するための本発明の絵素電
極形成法は、スイツチング用薄膜を形成する透明
絶縁基板上に設けたゲート電極をマスクにして、
スイツチング素子を形成後成膜した透明導電性膜
を、透明絶縁基板裏面から露光パターニングする
ことにより、ゲート電極以外の部分と整合した形
状に形成し、再度信号線部分を通常のフオトリソ
グラフイを用いて除去して所定の形状に形成する
ことを特徴とするものである。(Means for Solving the Problems) In order to solve the above problems, the picture element electrode forming method of the present invention uses a gate electrode provided on a transparent insulating substrate on which a thin film for switching is formed as a mask.
After forming the switching element, the formed transparent conductive film is exposed and patterned from the back side of the transparent insulating substrate to form a shape that matches the area other than the gate electrode, and the signal line area is again formed using normal photolithography. It is characterized in that it is removed and formed into a predetermined shape.
（作用）
本発明は、上記した製造法により、ゲート電極
と整合したパターン形成が可能なため、ゲート電
極幅が細くなつても、パターニング精度よく絵素
電極を形成することができるものである。(Function) According to the present invention, a pattern matching the gate electrode can be formed by the above-described manufacturing method, so that even if the width of the gate electrode becomes narrow, a pixel electrode can be formed with high patterning accuracy.
（実施例）
以下本発明の一実施例の絵素電極形成法につい
て、図面を参照しながら説明する。第１図ａない
しｃにその工程を示している。第１図ａはTFT
形成後、透明導電性膜８ａを基板上に成膜し、そ
の上にフオトレジスト９を塗布したものを透明絶
縁基板１の裏面からエキシマレーザーを用いて光
照射する段階を示している。第１図ｂは、第１図
ａでゲート電極２以外の部分と整合した形状で透
明導電性膜８ａをパターニングしたものに対し、
後に形成する信号線部分のレジストを除去するた
めのフオトレジスト９をパターニングしたものを
示す。第１図ｃは、絵素電極８を形成した後、ド
レイン電極７ａ、ソース電極７ｂを構成したスイ
ツチング絵素部の最終平面図である。(Example) A method for forming a picture element electrode according to an example of the present invention will be described below with reference to the drawings. The process is shown in FIGS. 1a to 1c. Figure 1a is TFT
After the formation, a transparent conductive film 8a is formed on the substrate, and a photoresist 9 is applied thereon, which is then irradiated with light from the back surface of the transparent insulating substrate 1 using an excimer laser. In contrast to FIG. 1b, the transparent conductive film 8a is patterned in a shape that matches the portion other than the gate electrode 2 in FIG. 1a.
A patterned photoresist 9 is shown for removing the resist of a signal line portion to be formed later. FIG. 1c is a final plan view of the switching picture element section in which the drain electrode 7a and source electrode 7b are formed after the picture element electrode 8 is formed.
以上のように本実施例によると、第２図ｂの従
来例に較べ、第１図ｃの斜線部分の絵素面積が拡
がることになる。 As described above, according to this embodiment, the area of the picture element in the shaded area in FIG. 1c is expanded compared to the conventional example shown in FIG. 2b.
上記実施例に対し、ゲート電極をマスクにして
絵素電極８を形成するため、ゲート電極以外に基
板上に第２電極を設けておけば、ゲート電極とそ
の第２電極上の透明電極を除去することが可能で
ある。 In the above embodiment, since the pixel electrode 8 is formed using the gate electrode as a mask, if a second electrode is provided on the substrate in addition to the gate electrode, the gate electrode and the transparent electrode on the second electrode can be removed. It is possible to do so.
（発明の効果）
以上のように本発明は、基板上に設けた金属に
より、スイツチング素子形成後成膜した透明電極
を自己整合型にパターニングすることにより、絵
素開口率を上げることができる。しかも基板が大
きくなつても、精度のいるパターニングは、自己
整合で対応できるため、作業が容易且つ確実であ
る。(Effects of the Invention) As described above, according to the present invention, the pixel aperture ratio can be increased by patterning the transparent electrode formed after the formation of the switching element in a self-aligned manner using the metal provided on the substrate. Moreover, even if the substrate becomes larger, accurate patterning can be achieved by self-alignment, making the work easy and reliable.
第１図ａないしｃは、本発明による絵素形成法
の工程図、第２図ａ，ｂは、従来例の断面図およ
び平面図である。
１……ガラス基板、２……ゲート電極、３……
ゲート絶縁体、４……非晶質シリコン、７ａ……
ソース電極、７ｂ……ドレイン電極、８……絵素
電極、８ａ……透明導電性膜、９……フオトレジ
スト。
1A to 1C are process diagrams of a picture element forming method according to the present invention, and FIGS. 2A and 2B are a sectional view and a plan view of a conventional example. 1... Glass substrate, 2... Gate electrode, 3...
Gate insulator, 4...Amorphous silicon, 7a...
Source electrode, 7b...Drain electrode, 8...Picture element electrode, 8a...Transparent conductive film, 9...Photoresist.
Claims (1)
ート電極として形成した透明絶縁基板上にスイツ
チング用薄膜を成膜、パターニングし、 表示用絵素電極として導電性透明膜を成膜し、
上にフオトレジストを塗布し、透明絶縁基板の裏
面からの光照射によりゲート電極をマスクにして
ゲート電極以外の部分と整合した形状でフオトレ
ジストをパターニングし、それをマスクにして透
明電極をエツチングし、フオトレジストを除去す
る第１の工程と、上記基板に対し通常のマスクを
使用して所定の形状に透明電極をパターン形成す
る第２の工程とを含み、ゲート電極に対し自己整
合により透明導電性膜を形成することを特徴とす
る絵素電極形成法。 ２ 透明導電性膜を成膜した基板に対し、マスク
を用いて予め通常のフオトリソグラフイによりパ
ターニングする第１の工程と、上記基板に再度フ
オトレジストを塗布し透明絶縁基板の裏面からゲ
ート電極をマスクにして光照射を行ない、走査電
極以外の部品と整合した形状にレジストをパター
ニングし、透明導電性膜をエツチングしてパター
ンを形成する第２の工程により、ゲート電極と自
己整合させて、所定の形状にパターニングするこ
とを特徴とする特許請求の範囲第１項記載の絵素
電極形成法。 ３ 第１のゲート電極と同一基板上に、ゲート電
極とは所定の位置で絶縁された第１のゲート電極
と同一金属の第２電極を形成した透明絶縁基板を
用いることにより、薄膜上の透明導電性膜のパタ
ーニングをゲート電極および第２電極上以外の部
分と整合した形状に行なうことを特徴とする特許
請求の範囲第１項記載の絵素電極形成法。 ４ 透明絶縁基板裏面からゲート電極をマスクに
して、透明絶縁基板上に設けられた透明導電性膜
上のパターニング用レジストを光照射するのにエ
キシマレーザーを用いて行なうことを特徴とする
特許請求の範囲第１項記載の絵素電極形成法。[Scope of Claims] 1. A thin film for switching is formed and patterned on a transparent insulating substrate on which a metal that is opaque to light of wavelengths below ultraviolet rays is formed as a gate electrode, and a conductive transparent film is formed as a pixel electrode for display. membrane,
A photoresist is applied on top, and the gate electrode is used as a mask to pattern the photoresist in a shape that matches the area other than the gate electrode by irradiating light from the back side of the transparent insulating substrate.Using this as a mask, the transparent electrode is etched. , a first step of removing the photoresist, and a second step of patterning a transparent electrode in a predetermined shape on the substrate using an ordinary mask, forming a transparent conductive electrode by self-alignment with the gate electrode. A method for forming a picture element electrode characterized by forming a transparent film. 2. The first step is to pattern the substrate on which the transparent conductive film has been formed using a mask using normal photolithography, and then apply photoresist to the substrate again and form the gate electrode from the back side of the transparent insulating substrate. The second step is to apply light irradiation using a mask, pattern the resist into a shape that matches the parts other than the scanning electrode, and then etch the transparent conductive film to form a pattern.The resist is self-aligned with the gate electrode and formed into a predetermined shape. 2. The method for forming a picture element electrode according to claim 1, wherein the pixel electrode is patterned in the shape of . 3 By using a transparent insulating substrate in which a second electrode made of the same metal as the first gate electrode, which is insulated from the gate electrode at a predetermined position, is formed on the same substrate as the first gate electrode, the transparent 2. The method for forming a picture element electrode according to claim 1, wherein the conductive film is patterned in a shape that matches the portions other than those on the gate electrode and the second electrode. 4. A patent claim characterized in that an excimer laser is used to irradiate a patterning resist on a transparent conductive film provided on a transparent insulating substrate with light from the back surface of the transparent insulating substrate using the gate electrode as a mask. The method for forming a picture element electrode according to scope 1.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063414A JPS61223781A (en) | 1985-03-29 | 1985-03-29 | Formation of picture element electrode |
| DE8686302414T DE3680806D1 (en) | 1985-03-29 | 1986-04-01 | THICK LAYER TRANSISTOR ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF. |
| EP86302414A EP0196915B1 (en) | 1985-03-29 | 1986-04-01 | Thin film transistor array and method of manufacturing same |
| US07/188,623 US4958205A (en) | 1985-03-29 | 1988-04-29 | Thin film transistor array and method of manufacturing the same |
| US07/454,990 US5137841A (en) | 1985-03-29 | 1989-12-22 | Method of manufacturing a thin film transistor using positive and negative photoresists |
| US07/833,921 US5166086A (en) | 1985-03-29 | 1992-02-12 | Thin film transistor array and method of manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60063414A JPS61223781A (en) | 1985-03-29 | 1985-03-29 | Formation of picture element electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61223781A JPS61223781A (en) | 1986-10-04 |
| JPH0584519B2 true JPH0584519B2 (en) | 1993-12-02 |
Family
ID=13228605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60063414A Granted JPS61223781A (en) | 1985-03-29 | 1985-03-29 | Formation of picture element electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61223781A (en) |
-
1985
- 1985-03-29 JP JP60063414A patent/JPS61223781A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61223781A (en) | 1986-10-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |