JPH0583778A - Time slot replacing circuit - Google Patents

Abstract

PURPOSE:To lessen the set quantity of replacement information when (i) pieces of time slots are replaced. CONSTITUTION:A selector 3 selects one side of the address data of the lower order (j) bit from a data preparing part 1a and the counted value of the (j) bit from a (j) step counter 2 and outputs it to a memory 6 for controlling to replace a time slot. A control part 1, when it performs the (i) pieces of the time slot replacement, controls so as to select the counted value of the (j) bit from the (j) step counter 2 by the selector 3. In the memory 6 for controlling to replace the time slot, the address data composed of the address data of the higher order (i) bit prepared by the data preparing part 1a and the counted value of the (j) bit from the (j) step counter 2 are written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot switching circuit, and more particularly to a time slot switching circuit for switching time slots of two types of setting units having different sizes.

[0002]

2. Description of the Related Art Conventionally, in a time slot switching circuit, as shown in FIG. 2, the input data is a RAM 14 using a count value from a write counter 15 as an address.
When the data is written in, the time slot is exchanged by reading the data from the RAM 14 by the read address supplied from the time slot exchange control memory (hereinafter referred to as control memory) 13.

Address data generated by the data generation unit 11a of the control unit 11 is written in the control memory 13 based on the address generated by the address generation unit 11b.
The address data written in the control memory 13 is read by the count value from the m-stage read counter 12,
It is output to the RAM 14 as a read address. Therefore, the data written in the RAM 14 is the control memory 13
The address data will be read in the order of.

That is, n-bit data D1 to Dm are written in the addresses 1 to m of the RAM 14 according to the write addresses 1 to m supplied from the write counter 15, respectively.

In this case, if the address data 15, 18, 2, 4, 16, ... Are written in the control memory 13, the data D15, D18, D2, D4, D16 ,. It is read from the RAM 14. By this, "Data D
, D2, D3, D4, D5, ..., Dm "are replaced with" data D15, D18, D2, D4, D16, ... "

Further, when setting i time slots of (n × j) -bit data having a size different from the above-mentioned n-bit data, the write counter 15 supplies them to the addresses 1 to m of the RAM 14, respectively. Write address
Data of (n × j) bits is written according to 1 to m. In this case, i groups each consisting of j sequential address data are written in the control memory 13. Here, i, j, n, and m are positive integers, and m = i × j.

For example, i = 3, j = 6, m = 3 × 6 = 1
8 indicates the address of the RAM 14 as shown in FIG.
1 to 18 have n-bit data D1 to D1 according to the write addresses 1 to 18 supplied from the write counter 15 respectively.
D18 is written.

In this case, if the address data written in the control memory 13 is 15, 18, 2, 4, 16, ..., 1, 3, the data D15, D18, D2, D4, in that order. D
16, ..., D1 and D3 are read from the RAM 14. As a result, "data D1, D2, D3, D4, D5,
"..., D17, D18" to "Data D15, D18, D2, D
4, D16, ..., D1, D3 "are replaced in time slots.

On the other hand, when three time slots of (n × 6) -bit data having a size different from the above-mentioned n-bit data are set, the address 1 of the RAM 14 is
Data of (n.times.6) bits are written in .about.18 in accordance with the write addresses 1 to 18 supplied from the write counter 15, respectively. In this case, the control memory 13 is stored in FIG.
As shown in FIG. 3, three groups of 6 pieces of sequential address data 7 to 12, 13 to 18, and 1 to 6 are written.

In such a conventional time slot exchange circuit, even when i time slots of (n × j) bits are exchanged, the control memory 13 is stored in the same manner as when m time slots are exchanged. Since it is necessary to set m pieces of address data, there is a problem that j times as many pieces of information must be set in order to replace i time slots.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned problems of the prior art, and it is possible to reduce the set amount of replacement information when replacing i time slots. The purpose is to provide a replacement circuit.

[0012]

A time slot exchange circuit according to the present invention comprises data storage means for storing data to be exchanged in time slots and address storage means for storing an address for reading the data from the data storage means. A time slot replacement circuit having, wherein when data having a bit width j times the bit width of the data storage means (j is a positive integer of 2 or more) is targeted for time slot replacement, each of the data Upper address generation means for generating a higher address indicating a storage area in the storage means, lower address generation means for sequentially generating a lower address indicating an address in the storage area, and the higher address generated by the higher address generation means Every time the data is stored in the address storage means, the The lower address is added to the upper address, characterized in that a control means for controlling so as to be stored in said address storage means.

[0013]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the data generator 1 of the controller 1
The a generates m-bit address data composed of upper i-bit address data and lower j-bit address data, and outputs the address data to the time slot replacement control memory (hereinafter referred to as control memory) 6. The address generator 1b generates an m-bit address composed of an upper i-bit address and a lower j-bit address,
The address is output to the control memory 6. Where i,
j and m are positive integers, and m = i × j.

The j-stage counter 2 generates a j-bit count value and outputs the count value to the selectors 3 and 4, respectively. Under the control of the control unit 1, the selector 3 selects one of the lower j-bit address data from the data generation unit 1a and the j-bit count value from the j-stage counter 2 and outputs the selected value to the lower j. It is output to the control memory 6 as bit address data. Selector 4 is control unit 1
On the basis of the control of 1), one of the lower j-bit address from the address generator 1b and the j-bit count value from the j-stage counter 2 is selected, and the selected value is used as the lower j-bit address. Output to 6.

Therefore, in the control memory 6, m-bit address data composed of the upper i-bit address data generated by the data generation unit 1a and the lower j-bit address data selected by the selector 3 is generated. Part 1
It is written based on an m-bit address composed of the upper i-bit address generated in b and the lower j-bit address selected by the selector 4.

The input data is written in the RAM 7 as a write address based on the value designated by the write counter 8. From the RAM 7, the value designated by the read counter 5 is read out as a read address from the control memory 6. The data is read according to the addressed data.

When replacing m time slots,
Since the selector 3 selects the lower j-bit address data generated by the data generator 1a of the controller 1, the control memory 6 stores the upper i-bit address data and the lower j bits generated by the data generator 1a. 1 to m address data consisting of bit address data is written. Therefore, m pieces of data are read from the RAM 7 according to the address data of 1 to m from the control memory 6, and m timeslots are replaced.

On the other hand, when the i time slots are replaced, the selector 3 selects the j-bit count value from the j-stage counter 2, so that the control memory 6 has the high-order data generated by the data generator 1a. 1 to m address data consisting of i-bit address data and the j-bit count value from the j-stage counter 2 are written. In this case, in the control unit 1, the data generation unit 1a generates the high-order i-bit address data, and the address generation unit 1b only generates the high-order i-bit address. It is sufficient to set the replacement information of.

As described above, when data having a bit width j times the bit width of the RAM 7 (j is a positive integer of 2 or more) is targeted for time slot replacement, the upper i bits indicating the storage area of each data are stored. Data is generated by the data generation unit 1a, the lower j-bit count value indicating the address in this storage area is sequentially generated by the j-stage counter 2, and added to the upper i-bit address data from the data generation unit 1a. And stores it in the control memory 6,
It is possible to reduce the setting amount of the replacement information when replacing the individual time slots.

[0021]

As described above, according to the present invention, when the data having the bit width j times the bit width of the data storing means for storing the data to be subjected to the time slot replacement is targeted for the time slot replacement. By generating an upper address indicating a storage area of each of the data, sequentially generating a lower address indicating an address in the storage area, adding the lower address to the upper address, and performing time slot replacement by these addresses. , I time slots are exchanged, the effect is that the amount of exchange information set can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a time chart showing a time slot switching operation according to a conventional example.

FIG. 4 is a diagram showing the contents of a time slot exchange control memory shown in FIG.

[Explanation of symbols]

 1 Control Unit 1a Data Generation Unit 1b Address Generation Unit 2 j-stage Counter 3, 4 Selector 6 Time Slot Replacement Control Memory 7 RAM

Claims (1)

[Claims] 1. A time slot replacement circuit having a data storage means for storing data to be replaced by a time slot and an address storage means for storing an address for reading the data from the data storage means.
When data having a bit width j times the bit width of the data storage means (j is a positive integer of 2 or more) is targeted for time slot replacement, a high-order address indicating the storage area of the data storage means in the data storage means A lower address generating means for sequentially generating a lower address indicating an address in the storage area, and an upper address generated by the upper address generating means for storing the upper address in the address storing means. And a control means for controlling the lower address sequentially generated by the lower address generation means to be added to the upper address and stored in the address storage means.