JPH0583591A - Frame timing detecting circuit - Google Patents

Abstract

PURPOSE:To make it hard for the frame pulse detection performance to be influenced by the fluctuation of the C/N of a transmitting signal and to improve the stability. CONSTITUTION:A coarse detecting circuit 12 detects the prescribed pattern of a frame pulse (FP) signal. An integration counter in an FP gate generating circuit 19, while the frame pulse is detected, counts a clock, a comparator compares an integration counter value and a set value and at the time of the constant relation, outputs a detecting signal. Based on the detecting signal, in the system in which the subsequent timing signal generating means generated various kinds of the timing signal of the system, a set value control circuit 100 for comparison responds to the timing of immediately before and after the frame pulse signal starts, latches the above-mentioned integration counted value, prepares the integrated value monitoring data, switches the above- mentioned set value set to a comparator in accordance with the value of the integrated value monitoring data and in accordance with the C/N, the set value is adaptively switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame timing detection circuit for detecting the frame timing of a television signal or the like.

[0002]

2. Description of the Related Art As one of the high-definition television broadcasting systems in Japan, MUSE (multiple sub-Nyquist sampling)
ling encoding) method. The signal transmission format of the MUSE system is a format as shown in FIG. 6, and the sync signal includes an HD signal and a frame pulse. FIG. 7 shows the waveform by extracting a part of the frame pulse. The frame pulse (FP) signal is a signal that is inserted in the latter half of the first line and the second line and takes a binary change equal to the video signal amplitude. The frame pulse is a pattern in which a high level “H” and a low level “L” are repeated every 4 clocks.
The first line and the second line have an inverted relationship. HD
The signal is a signal for horizontal synchronization and is inserted in the first half of the video signal and in the form of a trapezoidal wave in each line. However, there is an inverted relationship between the lines. Further, a clamp level signal is inserted in the line at the end of each field of the MUSE signal to give a reference for the signal levels of the transmitting side and the receiving side. The level set by the clamp level signal indicates the midpoint amplitude of the video signal. Next, when receiving a MUSE signal and reproducing video and audio, it is necessary to detect the position of the synchronization signal as described above and synchronize the system. Next, a circuit for detecting the above frame pulse signal will be described.

In FIG. 8, the input terminal 11 is provided with MUSE.
Most significant bit (MS) of signal (which is digitized)
B) is input. The most significant bit is input to the 1H delay unit 12a inside the frame pulse coarse detection circuit 12, one end of the exclusive OR circuits 12c and 12d, and the 4-clock delay unit 12b. Exclusive or circuit 12
The outputs of the 1H delay device 12a and the 4 clock delay device 12b are supplied to the other ends of c and 12d. Note that 1H is one horizontal scanning period. Next, the exclusive OR circuit 1
The outputs of 2c and 12d are input to the AND circuit 12e.

In the frame pulse signal, as shown in FIG. 7, 17 pairs of "H" level and "L" level for 4 clocks are alternately repeated so that it can be clearly distinguished from other video lines. Moreover, the polarities of the first and second lines are reversed. The arrival of the frame pulse signal is detected by utilizing this feature (inverse correlation). That is, while the frame pulse signal arrives, the outputs of the exclusive OR circuits 12c and 12d become "H" level, the output of the AND circuit 12e becomes "H" level, and the frame pulse signal arrives. Rough detection is performed.

The output of the AND circuit 12e is the OR circuit 1
The signal is supplied to the clear terminal (CLR) of the integration counter 19a in the FP gate generation circuit 19 via 5 and 16. The output of the OR circuit 15 is also supplied to the enable input terminal (E) of the integration counter 19a. The integration counter 19a is cleared when the output of the AND circuit 12e becomes low level, and is enabled when it becomes high level, and the counting is performed. The output of the AND circuit 12e is input to the AND circuit 17 and also to the group of latch circuits 13 and 14 connected in two stages. The outputs of the latch circuits 13 and 14 are also input to the AND circuit 17. Therefore, when the output of the AND circuit 12e continues for 2 clock periods, the output of the AND circuit 17 becomes high level, indicating the arrival of the FP signal, and the AND circuit 20 described later.
Entered in. First, the FP gate generation circuit 19 will be described.

FIG. 9 is a timing chart of the operation of the frame pulse signal detection circuit. Now, it is assumed that there is input data shown in (A) of the figure, the integration counter 19a is enabled as shown in (B) and (C) of the figure, and is cleared after a fixed period. Then, the count value of the integration counter 19a becomes as shown in FIG. Here, the output of the integration counter 19a is input to the comparator 19b and compared with a predetermined value. When the output of the integration counter 19a exceeds a predetermined value, the output of the comparator 19b becomes a logical output "H" as shown in FIG.
c, input to the exclusive OR circuit 19d. The output of the 3-clock delay unit 19c is also supplied to the exclusive OR circuit 19d. The output of the exclusive OR circuit 19d and the output of the 3-clock delay device 19c are input to the AND circuit 19e. The output of the AND circuit 19e is delayed by the delay device 19f and output. The output of the delay device 19f is delayed and output as shown in FIG. 9 (F), and input to the AND circuit 20.

The output from the above-mentioned AND circuit 17 is supplied to the AND circuit 20. AND circuit 17
Is output at the timing shown in FIG. 9 (G). As a result, a pulse having a width of 2 clocks is obtained from the AND circuit 20. This pulse is input to the edge detection circuit 21. As a result, the edge detection circuit 21 outputs from FIG.
An edge detection pulse as shown in (H) is output.

The latch circuits 13 and 14 are provided in order to prevent the enable state of the integration counter 19a and the clear operation from being affected by an input error such as noise. That is, the operation of the FP coarse detection circuit 19 can be accurately obtained even if the C / N decreases.

The output of the edge detection circuit 21 is input to the synchronization determination circuit 25 and the NAND circuit 22. The synchronization determination circuit 25 uses the internal F generated by the timing generation circuit 24.
A phase comparison is performed with the P signal (a pulse similar to the above edge detection pulse). If the phases of both are the same,
The low level is output and input to the NAND circuit 22.
Therefore, the output of the NAND circuit 22 is
Always high level. However, in the asynchronous state,
The output of the synchronization determination circuit 25 becomes high level. Then, the NAND circuit 22 outputs a clear pulse when the edge detection pulse (negative) is obtained. As a result, the system counter 23 is cleared and forcibly reset at the timing of the edge detection pulse. As a result, the timing generation circuit 24, in which an address is designated by the output of the system counter 23 and various timing pulses are generated,
The pulse output timing of is also output in a predetermined pattern mode in synchronization with the edge detection pulse. In addition,
In order to stabilize the system, the synchronization determination circuit 25
The synchronization deviation between the internal FP signal and the edge detection pulse is 15
When a frame continues, it is determined as an asynchronous state.

[0010]

According to the conventional frame timing detection circuit described above, the predetermined value set in the comparator 19b to which the output of the integration counter 19a is supplied is always a fixed value. However, because of this, the transmission C /
The start timing of the integration counter 19a may deviate depending on the change of the N value. This effect is particularly great when multiple errors occur at the leading edge of the counter enable signal. Therefore, the conventional circuit is inferior in the frame pulse detection accuracy with respect to the C / N value fluctuation of the transmission signal. Therefore, the present invention uses the C
It is an object of the present invention to provide a frame timing detection circuit that is unlikely to be affected by the frame pulse detection performance due to a change in / N.

[0011]

According to the present invention, there is provided coarse detection means for detecting a predetermined pattern of a frame pulse signal, and integral counter means for counting a clock while the coarse detection means is detecting a frame pulse. Comparing means for comparing the output count value of the integration counter means with a set value to output a comparison result signal for determining whether the integrated value has a predetermined relationship with the set value; In a frame timing detection circuit having timing signal generating means for generating various timing signals of the system based on the comparison result signal obtained from the means, the timing signal generating means allows the timing of immediately before and at the end of the frame pulse signal. Generate a clear pulse and a latch pulse corresponding to the timing. And a means for generating integrated value monitoring data for latching the integrated value in response to a loss, and a means for switching the set value set in the comparing means in accordance with the value of the integrated value monitoring data. ..

[0012]

The above means utilizes the fact that the count value of the integral counter means changes depending on the state of C / N. In other words, the value of the integration counter deviates from the original value when reset occurs due to noise during the frame pulse period. Therefore, the deviation is determined from the integrated value monitoring data, and the set value is switched to correct the detection timing of the original value. This allows
Even if the integral value of the integral counter does not reach the set value within a predetermined time due to the deterioration of the C / N of the transmission signal (effect of noise, etc.),
There is no delay in the timing of generating the FP gate pulse.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a comparison set value control circuit 10 which is an essential part of this embodiment.
The configuration of 0 is shown in detail. Further, FIG. 3 shows a timing chart of the circuits shown in FIGS.
In FIG. 1, parts having the same functions as those of the circuit of FIG. 8 are designated by the same reference numerals. Therefore, only the parts different from the circuit of FIG. 8 will be described.

First, the output of the OR circuit 16 (clear pulse of the integration counter 19a in the FP gate generation circuit 19) is
It is supplied to the FP gate generation circuit 19 via the latch circuit 18. The output of the OR circuit 16 is input to the comparison set value control circuit 100.

The comparison set value control circuit 100 judges the C / N state of the input signal from the contents of the integral counter 19a in the FP gate generation circuit 19, and sets the set value to be given to the comparator 19b in the FP gate generation circuit 19. It can be switched. When the C / N state is bad, the set value (threshold value) is lowered, and when the C / N state is good, the control is switched to the standard value.

Therefore, the comparison set value control circuit 100 includes
The count value of the integration counter 19a is input from the FP gate generation circuit 19. Inside the comparison set value control circuit 100, a preset circuit, a latch circuit, and the like are included as described in FIG. Therefore, in order to control the operation timing of the comparison control circuit 100, a power-on reset signal, a clear signal from the timing generation circuit 24, a clock signal, etc. are input from the terminal 101.

In FIG. 2, the comparison set value control circuit 10 is shown.
The inside of 0 will be described. The power-on reset signal is supplied to the preset terminal / PR of the latch circuit 26c. Then, the latch circuit 26c becomes "FFH" because the output data is all "0" and it is 8 bits.
This value is given to the data conversion circuit 26d as an address. The data read from the data conversion circuit 26d has 2 bits and is latched by the latch circuit 26e at the timing of the system clock. The output of the latch circuit 26e is given to the selector 26f as a control signal.
When this control signal is given, the selector 26f gives a set value (initial setting threshold value) to the comparator 19b.

After that, until the frame pulse is detected and the system is synchronized, the output of the synchronization determination circuit 25 is at the "L" level, and therefore the AND circuit 2 is used.
No latch pulse is obtained from 7 (FIG. 1). Therefore, the initial setting threshold value is maintained. When the synchronization is locked, a clear pulse is obtained from the timing generation circuit 24 immediately before the frame pulse period. This clear pulse clears the latch circuit 26b. This is the timing immediately before the frame pulse signal. Next, a latch pulse is applied from the OR circuit 16 through the inverter 26g.

Then, the latch circuit 26b latches the count value of the integral counter 19a. If there is no error in the output of the OR circuit 16, the value of the integration counter 19a will be latched at the end of the frame pulse period. However, when an error is encountered in the output of the OR circuit 16, that is, when the output of the AND circuit 12e (see FIG. 8) is continuously "L" for 3 clocks or more, the integration counter 19a is cleared in the middle of the frame pulse signal period. Therefore, the integrated count value at the end of the frame pulse signal period is smaller than that in the case where there is no error. Therefore, if there is an error in the frame pulse period, the integration counter 19a may be cleared, so it is necessary to add the total number of counts in the frame pulse period. Therefore, the adder 26a is provided on the input side of the latch circuit 26b. The output of the adder 26a is input to the latch circuit 26b. Then,
When an error occurs, the integral counter 19a is reset and the integration is performed again. However, the count value before the error occurs is latched by the latch circuit 26b, and the next integral value is added by the adder 26a. become. Therefore, even if the integration counter 19a is reset due to an error, the integration value so far is not wasted, and at the end of the frame pulse, a value having this as an initial value is used as the latch circuit 2.
It will be latched at 6b. However, as described above, the value of the latch data when an error occurs is smaller than the final latch data when the error is normal. Therefore, in this system, such a phenomenon is judged as the C / N being deteriorated, and the comparator 1
The set value in 9b is switched so that edge detection can be obtained even if the integrated count value is low.
FIG. 3 is a timing signal of each part of this embodiment. The generation position of each signal is as shown in each part of FIG.

With the above configuration, when the C / N is high, the error detection of the FP signal can be strengthened because the data error is small, and the stability of the operation can be increased. When the transmission C / N is low, there are many data errors and FP
Signal detection is difficult, but set value (threshold value)
It was possible to lower the detection limit of the FP signal by setting a low value. Therefore, the operation performance of the frame pulse signal detection with respect to the C / N fluctuation of the transmission signal can be improved. The present invention is not limited to the above embodiments.

FIG. 4 shows only the essential parts of another embodiment of the present invention. Since the basic configuration is the same as that of the circuits of FIGS. 1 and 2, the same reference numerals are given and only different portions will be described. In this embodiment, when the control signal is obtained, the output of the data conversion circuit 26d is latched by the latch circuit 26e and then returned to the higher address of the data conversion circuit 26d. In this way, the data conversion circuit 2
The output characteristic of 6d can have a hysteresis characteristic as shown in FIG. With such a characteristic, stable data conversion can be realized even if vibration occurs near the change point of the output of the data conversion circuit 26d.

Description will be made with reference to FIG. Latch circuit 26
If the latch output value of e changes from 0 to B, for example, the output of the data conversion circuit 26d changes from 0 to 1,
In order for it to be fed back to higher addresses,
The relationship of the output data with respect to the input address of the data conversion circuit 26d is switched, and the latch circuit 26 detected next is detected.
If the output of c does not drop from B to A, the output does not change from 1 to 0. Therefore, even if the output of the latch circuit 26c vibrates near points A, B, ... F, the output of the data conversion circuit 26d will be stable. Thereby, the stability of the FP detection operation can be further enhanced.

[0024]

As described above, according to the present invention, the frame pulse detection performance is hardly affected by the fluctuation of the C / N of the transmission signal, and the stability can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an essential part of the circuit of FIG.

FIG. 3 is a timing chart shown to explain the operation of the circuit of FIG.

FIG. 4 is a diagram showing a main part in another embodiment of the present invention.

5 is a diagram shown for explaining the operating characteristics of the circuit of FIG. 4;

FIG. 6 is a diagram shown for explaining a transmission format of a MUSE signal.

FIG. 7 is a diagram showing a waveform of a frame pulse signal.

FIG. 8 is a diagram showing a conventional frame timing detection circuit.

9 is a timing chart shown for explaining the operation of the circuit of FIG.

[Explanation of symbols]

12 ... FP (frame pulse) coarse detection circuit, 13, 1
4, 18, 20 ... Latch circuit, 15, 16 ... OR circuit,
17, 20, 27 ... AND circuit, 19 ... FP gate generation circuit, 21 ... Edge detection circuit, 22 ... NAND circuit, 23
... system counter, 24 ... timing generation circuit, 25
... synchronization determination circuit, 100 ... comparison set value control circuit.

Claims (1)

[Claims] 1. A coarse detection means for detecting a predetermined pattern of a frame pulse signal, an integration counter means for counting a clock during a period during which the coarse detection means detects a frame pulse, and an output count of the integration counter means. Comparing means for outputting a comparison result signal for judging whether or not the integrated value has a predetermined relationship with the set value by comparing the value with the set value; and the comparison result signal obtained from the comparing means. In a frame timing detection circuit including timing signal generating means for generating various timing signals of the system based on the above, a clear pulse corresponding to the timing of the start and end timing of the frame pulse signal by the timing signal generating means, a latch Pulse is generated, and the integrated value is calculated in response to the clear pulse and latch pulse. A frame timing detection circuit comprising: means for generating integrated value monitoring data to be latched; and means for switching the set value set in the comparing means in accordance with the value of the integrated value monitoring data.