JPH0582745A - Cmos lsi - Google Patents

Abstract

PURPOSE:To facilitate display with a display device, particularly a current-driven display device such as an LED, which is connected to a low-voltage-driven CMOS LSI such as a microcomputer or gate array. CONSTITUTION:A voltage multiplying circuit device group 2 which is mainly composed of MOS transistors M1-M4, a gate control circuit 3 which is composed of MOS transistors M103-M40n and inverters g1-Gn and a large current output terminals 4 which are composed of MOS transistors M5-Mn are provided. With this constitution, a high voltage can be generated efficiently from the power supply of the CMOS LSI and a display device such as an LED can be used easily. Further, the CMOS LSI having the large current output terminal whose ON-resistance is small can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS such as a microcomputer or a gate array operated at a low voltage.
Applies to LSI.

[0002]

2. Description of the Related Art As battery-powered portable equipment becomes widespread, the power supply voltage of a CMOS LSI such as a microcomputer or a gate array used in the portable equipment tends to gradually decrease. According to this, the LS
Display element controlled or driven by I, especially LED (Li
The driving voltage of the current driving element such as ght Emitting Diode) or the current driving capability of the control terminal is insufficient, and display by these becomes difficult.

[0003]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the prior art, and a display element connected to a CMOS LSI such as a low voltage drive microcomputer or a gate array, particularly a current drive type such as an LED. The purpose is to enable display by the display element.

[0004]

According to the present invention, a CMO
One or more MO transistors among the MOS transistors forming the MOS switch, which incorporates a MOS switch required for a voltage multiplication circuit using a capacitor in an SLSI and a control circuit for controlling the gate of the MOS switch.
The voltage generated by the voltage multiplying circuit is applied to the gate of the S transistor.

Further, according to the present invention, a large current output terminal configured to apply the voltage generated by the voltage multiplier circuit to the gate of the MOS transistor in the current output terminal formed of the MOS transistor in the CMOS LSI. Have.

[0006]

According to the present invention, a switch forming a voltage multiplication circuit using a capacitor is constituted by a MOS transistor, and the switch
An OS transistor and a gate control circuit for the MOS transistor are built in a CMOS LSI such as a microcomputer or a gate array, and a high voltage generated by the voltage multiplier circuit is applied to the gate of one or more MOS transistors of the MOS transistors. On /
Control off. Further, the high voltage generated by the voltage multiplication circuit is also used for the gate of the MOS transistor forming the large current output terminal built in the CMOS LSI to control ON / OFF.

[0007]

EXAMPLES Next, the present invention will be described in detail with reference to Examples. FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, M1, M3, M4 are P-channel MOS transistors, M2 is an N-channel MOS transistor.
Each of the transistors 1 to M4 is a MOS switch that constitutes a voltage multiplier circuit. R1 is a current limiting resistor, D1
Is a diode. T1 to Tn are CMOS LSI1
The MOS transistors M1 to M4, the resistor R1, and the diode D1 form a voltage multiplier circuit element group 2 at the terminal. M5 to Mn are N-channel MOS transistors and form a large current output terminal 4. M104, M204, M3
04 and M404 are CMOSs which are driven by the voltage multiplier circuit generated voltage Vc in each P-channel and N-channel transistor
A level conversion circuit having a two-stage inverter structure is configured, and an output terminal is connected to the gate of the MOS transistor M4. Similarly, M103, M203, M303, and M403 are CMs with P-channel and N-channel MOS transistors.
It constitutes a level conversion circuit by an OS inverter, and its output terminal is connected to the gate of the MOS transistor M3. M
105, M205, M305, M405-M10n, M
Similarly, 20n, M30n, and M40n also form a level conversion circuit by a CMOS inverter with each P-channel and N-channel MOS transistor, and the output terminals are connected to the gates of the MOS transistors M5 to Mn. G1 to Gn are CMOs driven by the power supply voltage Vcc of the CMOS LSI1
It is an S inverter. These MOS transistors M10
3 to M40n level conversion circuit and CMOS
The inverters G1 to Gn form a MOS switch for the voltage multiplier circuit and a gate control circuit 3 for a large current output terminal. R
2, R3 to Rn are resistors, C1 and C2 are capacitors, and D2
~ Dn are LEDs, these elements are CMOS LSI1
External circuit.

FIG. 2 is an embodiment of the present invention including a known voltage multiplier circuit. In the figure, S1 to Sn are MOS switches, R1 to Rn are resistors, C1 and C2 are capacitors, and D.
Reference numeral 1 is a diode, T1 to Tn are input / output terminals of the CMOS LSI 1, and D2 to Dn are LEDs. In FIGS. 1 and 2, the same reference numerals denote the same components.
Further, M1 to Mn in FIG. 1 and S1 to Sn in FIG. 2 are corresponding components. The broken line indicates a switch driven by the voltage multiplier circuit generated voltage Vc.

Next, the operation of this circuit will be described. In the initial state, it is assumed that all the switches S1 to Sn are off. In this state, the capacitor C2 connected to the input / output terminal T3 is charged to the power supply voltage Vcc of the CMOS LSI 1 through the resistor R1 and the diode D1. First, the switches S1 and S2
When turned on, the capacitor C1 is charged to the power supply voltage Vcc. Next, when the switches S1 and S2 are turned off and the switch S3 is turned on, the potential of the input / output terminal T1 connected to the electrode of the capacitor C1 becomes 2 × Vcc. Next, when the switch S4 is turned on, the charge of the capacitor C1 is changed to the capacitor C.
Move to 2. By repeating this operation, the capacitor C
The terminal voltage Vc of 2 is boosted to 2 × Vcc. Next, for example, when the switch S5 is turned on for t1 seconds, the current i
LED lights up. During this period, the terminal voltage Vc of the capacitor C2 decreases by ΔVc. If the average of the current i is I, then ΔVc = I × t1 / C2. For example, I = 5m
If A, t1 = 0.2s and C2 = 5mF, then ΔVc =
It becomes 0.2V. It is possible to intermittently turn on the LED by compensating for this voltage drop again by the above charging operation. Here, the MOS transistor M4, which is the switch S4, operates at a potential higher than the power supply voltage Vcc of the CMOS LSI for both the source and the drain. Therefore MO
The gate of the S transistor M4 is normally driven by the terminal voltage Vc of the capacitor C2, which is the highest voltage of this circuit, that is, the voltage multiplier circuit generated voltage Vc. Further, in this embodiment, the switches S3, S5-Sn, that is, the MOS transistors M3, M5-Mn are also driven at the same voltage Vc in order to reduce the MOS transistor size or the on-resistance. The MOS switch control circuit 3 uses these M
This is a circuit for controlling the gates of the MOS transistors M1 to Mn that serve as OS switches.

[0010]

According to the present invention, CMOS such as a microcomputer or a gate array driven by a low voltage is used.
The LSI has a built-in element group 2 such as a switch required for a voltage multiplication circuit and a gate control circuit 3 of a MOS transistor which is the switch. The gate control circuit 3 is provided at the gate of the MOS switch by the voltage multiplication circuit. By applying the generated voltage, a high voltage can be efficiently generated and the CM
It is possible to easily use a display element such as an LED that requires a high voltage that cannot be driven by the power supply voltage of the OS LSI.

Further, according to the present invention, the CMOS LSI 1 described above is used.
MO having a large current output terminal 4 and constituting the output terminal 4
By applying the voltage generated by the voltage multiplier circuit to the gate of the S-transistor, a large current output terminal having a small ON resistance can be formed.

The effect of the present invention is not limited to the configurations of the voltage multiplier circuit element group 2, the gate control circuit 3, and the large current output terminal 4 shown in the embodiments.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the present invention.

[Explanation of symbols]

1 ... CMOS LSI, 2 ... Voltage multiplier circuit element group, 3
... Gate control circuit, 4 ... Large current output terminals, M1-Mn ...
MOS transistors, M103 to M40n ... MOS transistors, G1 to Gn ... Inverters, T1 to Tn ... Input / output terminals, C1 to C2 ... Capacitors, R1 to Rn ... Resistors,
D1 ... Diode, D2-Dn ... LED, S1-Sn ... M
OS switch.

Claims (2)

[Claims] 1. A CMOS LSI having a P-channel and an N-channel MOS, which has a built-in MOS switch necessary for a voltage multiplier circuit using a capacitor and a gate control circuit for controlling the gate of the MOS switch.
A CMOS LSI characterized in that a voltage generated by the voltage multiplying circuit is applied to the gate of a required MOS transistor among the MOS transistors constituting the OS switch. 2. The high current output terminal according to claim 1, further comprising a current output terminal formed of a MOS transistor, and a large current output terminal configured to apply the voltage generated by the voltage multiplier circuit to the gate of the MOS transistor. A CMOS LSI characterized in that