JPH1066259A - Power supply on/off sequence circuit - Google Patents

Power supply on/off sequence circuit

Info

Publication number
JPH1066259A
JPH1066259A JP8215615A JP21561596A JPH1066259A JP H1066259 A JPH1066259 A JP H1066259A JP 8215615 A JP8215615 A JP 8215615A JP 21561596 A JP21561596 A JP 21561596A JP H1066259 A JPH1066259 A JP H1066259A
Authority
JP
Japan
Prior art keywords
power
switch
power supply
turned
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8215615A
Other languages
Japanese (ja)
Other versions
JP3088298B2 (en
Inventor
Takashi Horikoshi
隆 堀越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Gunma Ltd
Original Assignee
NEC Gunma Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Gunma Ltd filed Critical NEC Gunma Ltd
Priority to JP08215615A priority Critical patent/JP3088298B2/en
Publication of JPH1066259A publication Critical patent/JPH1066259A/en
Application granted granted Critical
Publication of JP3088298B2 publication Critical patent/JP3088298B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To achieve the following power on/off sequence in a power supply on/off circuit contained in an electronic device using a simple circuit without need for a control unit: When power is turned on, 5V is turned on and then 3.3V is turned on; when power is turned off, 3.3V is turned off and then 5V is turned off. SOLUTION: A load circuit 5 has a first power supply 1 as 5V voltage source and a second power supply 2 as 3.3V voltage source. A first switch 3 is placed between the first power supply 1 and the load circuit 5, and a second switch 4 is placed between the second power supply 2 and the load circuit 5. The power supplies to the load circuit 5 are turned on/off by turning on/off the respective switches. A first delay circuit 7 and a second delay circuit 8 are placed between a power supply on/off control signal 6 for turning on/off power supply and the first switch 3 and between the power supply on/off control signal 6 and the second switch 4, respectively, in order to adhere to the power supply on/off sequence.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電源ON/OFF
シーケンス回路に関し、特に、ノートパソコン用電源に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a sequence circuit, and particularly to a power supply for a notebook computer.

【0002】[0002]

【従来の技術】従来のシーケンス回路は、特開平5−1
30733号公報に記載された動作式電源装置がある。
この装置のブロック図を図4に示す。
2. Description of the Related Art A conventional sequence circuit is disclosed in
There is an operation type power supply device described in Japanese Patent No. 30733.
A block diagram of this device is shown in FIG.

【0003】図4において、連動スイッチ10は、電源
ラインに接続され、相互に連動して作動する一対のスイ
ッチ部10a,10bを有する。第1リレースイッチ1
1は、連動スイッチ10と並列に接続されている。第2
リレースイッチ12は、連動スイッチ10の一方のスイ
ッチ部10aに直列に接続されている。第1電源部13
は、連動スイッチ10と他方のスイッチ部10bおよび
第1リレースイッチ11にそれぞれ直列に接続されてい
る。第2電源部14は、第2リレースイッチ12に直列
に接続されている。第1リレースイッチ制御部15は、
第2電源部14の出力に設けられて、第1リレースイッ
チ11の開閉を制御するものである。第2リレースイッ
チ制御部16は、第1電源部13の出力側に設けられ
て、第2リレースイッチ12の開閉を制御するものであ
る。
In FIG. 4, an interlocking switch 10 has a pair of switch sections 10a and 10b which are connected to a power supply line and operate in conjunction with each other. 1st relay switch 1
1 is connected in parallel with the interlocking switch 10. Second
The relay switch 12 is connected in series to one switch section 10a of the interlock switch 10. First power supply unit 13
Are connected in series to the interlock switch 10, the other switch section 10b, and the first relay switch 11, respectively. The second power supply unit 14 is connected to the second relay switch 12 in series. The first relay switch control unit 15
It is provided at the output of the second power supply unit 14 and controls opening and closing of the first relay switch 11. The second relay switch control section 16 is provided on the output side of the first power supply section 13 and controls opening and closing of the second relay switch 12.

【0004】このシーケンス動作式電源装置では、連動
スイッチ10を投入すると、直ちに第1電源部13を通
じて出力が立ち上がりONとなる。続いて、出力が
ONとなったことによって、第2リレースイッチ制御部
16が駆動し、第2リレースイッチ12が閉じてONと
なり、第2電源部14を通じて出力が立ち上がりON
となる。なお、出力がONとなった後、第1リレース
イッチ制御部15が駆動し、第1リレースイッチ11が
閉じてONとなっている。次に、連動スイッチ10をO
FFにすると、直ちに出力がOFFになる。続いて、出
力がOFFとなったことによって、第1リレースイッ
チ制御部15が作動して、第2リレースイッチ12が開
いてOFFになっている。
In this sequence operation type power supply, when the interlock switch 10 is turned on, the output immediately rises through the first power supply unit 13 and turns on. Subsequently, when the output is turned on, the second relay switch control unit 16 is driven, the second relay switch 12 is closed and turned on, and the output rises through the second power supply unit 14 and is turned on.
Becomes After the output is turned on, the first relay switch control unit 15 is driven, and the first relay switch 11 is closed and turned on. Next, the interlock switch 10 is turned on.
When it is set to FF, the output is turned off immediately. Subsequently, when the output is turned off, the first relay switch control unit 15 is operated, and the second relay switch 12 is opened and turned off.

【0005】図5の(a)〜(c)は、上述したシーケ
ンス動作式電源装置におけるタイムチャートである。電
源スイッチONの場合は、出力が先に立ち上がってか
ら出力がONとなり、電源スイッチOFFの場合は、
出力が先に立ち上がってから出力がOFFとなって
いる。
FIGS. 5A to 5C are time charts in the sequence operation type power supply device described above. When the power switch is ON, the output turns on after the output rises first, and when the power switch is OFF,
The output has been turned off since the output started first.

【0006】[0006]

【発明が解決しようとする課題】従来の技術では、リレ
ースイッチを用いて電源ON/OFFシーケンスを実現
している。従って、リレースイッチ制御部が必要であ
り、回路構成が複雑で、コストアップになる。
In the prior art, a power ON / OFF sequence is realized using a relay switch. Therefore, a relay switch control unit is required, the circuit configuration is complicated, and the cost increases.

【0007】本発明の目的は、電源ON/OFFシーケ
ンスにおいて、リレースイッチ制御部を必要としない簡
単な回路で実現することにある。
An object of the present invention is to realize a power ON / OFF sequence with a simple circuit that does not require a relay switch control unit.

【0008】[0008]

【課題を解決するための手段】本発明は、電源ONする
ときには第1電源をONしてから第2電源をONし、電
源OFFするときには、第2電源をOFFしてから第1
電源をOFFするような電源ON/OFFシーケンスが
定められている電源ON/OFF回路を有する電子装置
であって、5Vの電源である第1電源と、3.3Vの電
源である第2電源とを有し、第1電源と負荷回路との間
に第1スイッチを、第2電源と負荷回路との間に第2ス
イッチを設けて、第1スイッチおよび第2スイッチをO
N/OFFすることにより、負荷回路への電源供給をO
N/OFFすることを特徴とする電源ON/OFFシー
ケンス回路である。
According to the present invention, when the power is turned on, the first power is turned on and then the second power is turned on. When the power is turned off, the second power is turned off and then the first power is turned off.
An electronic device having a power ON / OFF circuit in which a power ON / OFF sequence for turning off the power is defined, wherein a first power source as a 5V power source and a second power source as a 3.3V power source are provided. A first switch is provided between the first power supply and the load circuit, a second switch is provided between the second power supply and the load circuit, and the first switch and the second switch are connected to each other.
N / OFF turns off the power supply to the load circuit.
This is a power ON / OFF sequence circuit characterized by N / OFF.

【0009】また、第1スイッチおよび第2スイッチ
を、電源ON/OFF制御信号によって制御するように
すれば良い。
The first switch and the second switch may be controlled by a power ON / OFF control signal.

【0010】さらに、電源ON/OFF制御信号を、N
−チャンネルMOSFETを用いて送出するようにすれ
ば良い。
Further, the power ON / OFF control signal is set to N
-Transmission may be performed using a channel MOSFET.

【0011】またさらに、電源ON/OFFシーケンス
回路を実現するために、ON/OFF制御信号と各スイ
ッチとの間に遅延回路を設けるようにすれば良い。
Further, in order to realize a power ON / OFF sequence circuit, a delay circuit may be provided between the ON / OFF control signal and each switch.

【0012】この発明は、5Vの電源および3.3Vの
電源を、ノートパソコンの電源として使用すれば最適で
ある。
The present invention is optimal if a 5V power supply and a 3.3V power supply are used as a power supply for a notebook personal computer.

【0013】本発明の電源ON/OFFシーケンス回路
は、電源ONするときには5VをONしてから3.3V
をONし、電源OFFするときには、3.3VをOFF
してから5VをOFFする。具体的には、電源ONする
ときに5Vが早く立ち上がるように、3.3Vを遅延さ
せる手段と、電源OFFするとき5Vが3.3Vよりも
遅くたち下がるように保持させる手段を有する。
In the power ON / OFF sequence circuit of the present invention, when power is turned ON, 5V is turned ON and then 3.3V.
Is turned on and 3.3V is turned off when the power is turned off.
And then turn off 5V. Specifically, it has a means for delaying 3.3 V so that 5 V rises earlier when the power is turned on, and a means for holding the voltage so that 5 V falls later than 3.3 V when the power is turned off.

【0014】[0014]

【発明の実施の形態】次に、本発明の実施例について図
面を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

【0015】図1は、本発明の電源ON/OFFシーケ
ンス回路の構成を示すブロック図である。この回路は、
5V電圧源である第1電源1と、3.3V電圧源である
第2電源2とがあり、第1電源1と負荷回路5との間に
第1スイッチ3を、第2電源2と負荷回路5との間に第
2スイッチ5を設けて、それぞれのスイッチをON/O
FFすることにより、負荷回路5への電源供給をON/
OFFしている。また、電源をON/OFFするための
電源ON/OFF制御信号6と第1スイッチ3,第2ス
イッチ4との間には、電源ON/OFFシーケンスが守
られるように第1遅延回路7,第2遅延回路8が接続さ
れる構成になっている。
FIG. 1 is a block diagram showing the configuration of a power ON / OFF sequence circuit according to the present invention. This circuit is
There is a first power supply 1 which is a 5V voltage source, and a second power supply 2 which is a 3.3V voltage source. The first switch 3 is provided between the first power supply 1 and the load circuit 5, and the second power supply 2 is connected to the load. A second switch 5 is provided between the switch 5 and the circuit 5, and each switch is turned ON / O.
By performing FF, the power supply to the load circuit 5 is turned ON / OFF.
It is off. In addition, a first delay circuit 7 and a second delay circuit 7 are provided between a power ON / OFF control signal 6 for turning ON / OFF the power and the first switch 3 and the second switch 4 so as to maintain a power ON / OFF sequence. The configuration is such that the two delay circuits 8 are connected.

【0016】電源ONするときは、電源ON/OFF制
御信号6から第1スイッチ3と第2スイッチ4とをON
するための信号が出力され、5Vを先にONしてから
3.3VをONさせるために、第2遅延回路8で第2ス
イッチ4に加わる電圧を遅延させている。また、電源O
FFするときは、電源ON/OFF制御信号6から第1
スイッチ3と、第2スイッチ4とをOFFするための信
号が出力され、3.3Vを先にOFFしてから5VをO
FFさせるために、第1遅延回路7で第1スイッチ3に
加わっている電圧を一定時間保持させている。
When the power is turned on, the first switch 3 and the second switch 4 are turned on from the power ON / OFF control signal 6.
The second delay circuit 8 delays the voltage applied to the second switch 4 in order to turn on 5 V first and then turn on 3.3 V. Power supply O
When performing FF, the power ON / OFF control signal 6
A signal for turning off the switch 3 and the second switch 4 is output, and after turning off 3.3 V first, 5 V is turned on.
In order to perform FF, the voltage applied to the first switch 3 is held by the first delay circuit 7 for a certain period of time.

【0017】このように、電源ON/OFF制御信号6
から出力される信号を、第1遅延回路7と第2遅延回路
8とでシーケンスに合うようにしてあげれば、電源ON
/OFFシーケンスは容易に実現できることになる。
As described above, the power ON / OFF control signal 6
If the signals output from the first and second delay circuits 7 and 8 are made to conform to the sequence, the power is turned on.
The / OFF sequence can be easily realized.

【0018】図2は、本発明の実施例を示す電源ON/
OFF回路図である。図1の第1電源1がVCC5−
1,第2電源2がVCC3−2,第1スイッチ3がFE
T1−3,第2スイッチ4がFET2−4,負荷回路5
がZ−5,電源ON/OFF制御信号がVPP−6,第
1遅延回路7と第2遅延回路8が点線で示されている。
この回路構成は、5V電圧源である5V電源VCC5−
1と3.3V電圧源である3.3V電源VCC3−2が
あり、5V電源VCC5−1,3.3V電源VCC3−
2と負荷回路Z−6との間にはN−チャンネルMOSF
ETによりスイッチを設けて5V電源用はスイッチFE
T1−3を、3.3V電源用にはスイッチFET2−4
をON/OFFすることにより負荷回路Z−5の電源供
給をON/OFFしている。また、電源をON/OFF
するための電源ON/OFF制御信号VPP−6とスイ
ッチFET1−3との間には、ゲート抵抗R1,ゲート
・ソース間コンデンサC1,ゲート・ソース間抵抗R
3,ゲート放電抵抗R5,ダイオードD1で構成される
第1遅延回路7(点線の枠内)があり、スイッチFET
2との間にはゲート抵抗R2,ゲート・ソース間コンデ
ンサC2,ゲート・ソース間抵抗R4で構成される第2
遅延回路8(点線の枠内)が接続されている。
FIG. 2 is a circuit diagram showing an embodiment of the present invention.
It is an OFF circuit diagram. The first power supply 1 of FIG.
1, the second power supply 2 is VCC3-2, the first switch 3 is FE
T1-3, second switch 4 is FET2-4, load circuit 5
, The power ON / OFF control signal is VPP-6, the first delay circuit 7 and the second delay circuit 8 are indicated by dotted lines.
This circuit configuration includes a 5V power supply VCC5-
There are a 3.3V power supply VCC3-2, which is a 1 and 3.3V voltage source, and a 5V power supply VCC5-1 and a 3.3V power supply VCC3-
2 and a load circuit Z-6, an N-channel MOSF
A switch is provided by ET, and a switch FE is used for 5V power supply.
T1-3 is replaced with a switch FET2-4 for a 3.3V power supply.
Is turned on / off, the power supply of the load circuit Z-5 is turned on / off. Also power on / off
Between the power supply ON / OFF control signal VPP-6 and the switch FET1-3, the gate resistance R1, the gate-source capacitor C1, and the gate-source resistance R
3, there is a first delay circuit 7 (within a dotted frame) composed of a gate discharge resistor R5 and a diode D1.
A second gate resistor R2, a gate-source capacitor C2, and a gate-source resistor R4.
The delay circuit 8 (within a dotted frame) is connected.

【0019】次に、本発明の実施例の動作について説明
する。
Next, the operation of the embodiment of the present invention will be described.

【0020】電源をON/OFFするための電源ON/
OFF制御信号VPP−6には電源ONの時12Vで、
電源OFFの時0Vである。5VをON/OFFするた
めには、5V用FETであるスイッチFET1−3を、
3.3VをON/OFFするには3.3V用FETであ
るスイッチFET2−4をON/OFFしなければなら
ない。電源ONするとき、5VがONする時間は、ゲー
ト抵抗R2とゲート・ソース間抵抗R4とゲート・ソー
ス間コンデンサC2により決定される。電源OFFする
とき、3.3VがOFFする時間は、ONするときと同
様に、ゲート抵抗R2とゲート・ソース間抵抗R4とゲ
ート・ソース間コンデンサC2により決定するが、5V
がOFFする時間は、ゲート・ソース間抵抗R3とゲー
ト・ソース間コンデンサC1とゲート放電用抵抗R1と
により決定される。
Power ON / OFF for power ON / OFF
The OFF control signal VPP-6 has a voltage of 12 V when the power is on,
It is 0 V when the power is off. To turn on / off 5V, switch FET1-3, which is a 5V FET,
To turn 3.3V ON / OFF, the switch FET2-4, which is a 3.3V FET, must be turned ON / OFF. When the power is turned on, the time during which 5V is turned on is determined by the gate resistance R2, the gate-source resistance R4, and the gate-source capacitor C2. When the power is turned off, the time during which 3.3 V is turned off is determined by the gate resistance R2, the gate-source resistance R4, and the gate-source capacitor C2, as in the case of turning on the power.
Is turned off by the gate-source resistance R3, the gate-source capacitor C1, and the gate discharge resistance R1.

【0021】各ゲート・ソース間抵抗,コンデンサに同
じ抵抗値,容量のものを使用した場合、5Vを先に立ち
上げるようにするには、5V用のゲート抵抗R1を3.
3Vのゲート抵抗R2より小さくすればよい。また、
3.3Vを先に立ち上げようとするには、3.3V用ゲ
ート抵抗R2を5Vのゲート放電用抵抗R5より小さく
すればよい。
When the same resistance and capacitance are used for each gate-source resistance and capacitor, 5V gate resistor R1 must be set to 3.
What is necessary is just to make it smaller than the gate resistance R2 of 3V. Also,
In order to raise 3.3V first, the 3.3V gate resistance R2 may be smaller than the 5V gate discharge resistance R5.

【0022】すなわち、R1<R2、R5 ∴C=C
2,R3=R4となる。
That is, R1 <R2, R5∴C = C
2, and R3 = R4.

【0023】ただし、出力電圧が5Vと3.3Vである
ことと、5Vの第1遅延回路7にはダイオードD1があ
ることからスイッチに加えられる電圧がそれぞれ異なる
ことを考慮する必要がある。
However, it is necessary to consider that the output voltages are 5 V and 3.3 V, and that the first delay circuit 7 of 5 V has a diode D1 so that the voltages applied to the switches are different from each other.

【0024】例えば、下記のような部品で電源ON/O
FFシーケンス回路を構成した場合を考察してみる。 5V側 スイッチ FET1→4VでON,2VでOFF ゲート抵抗 R1=10kΩ ゲート・ソース間抵抗 R3=200kΩ ゲート・ソース間コンデンサC1=0.1μF ゲート放電抵抗 R5=200kΩ ダイオード D1→VF=0.6V 3.3V側 スイッチ FET2→4VでON,2VでOFF ゲート抵抗 R2=33kΩ ゲート・ソース間抵抗 R4=200kΩ ゲート・ソース間コンデンサC2=0.1μF 電源をONするとき、スイッチFET1およびスイッチ
FET2がONする時間を求めると、 V:スイッチのゲート・ソース間に加わる電圧[V] E:電源ON/OFF制御信号VPPと負荷回路間の等
価電圧[V] C:ゲート・ソース間コンデンサ容量[μF] R:等価ゲート抵抗[Ω] ton=−C・R・loge(V/E)[s]・・・・・・・・・・(1) 等価ゲート抵抗Rは、 Rg :ゲート抵抗 Rgs:ゲート・ソース間抵抗 R=Rg・Rgs/(Rg+Rgs)[Ω]・・・・・・・・・・・(2) 電源ON/OFF制御信号VPPと負荷回路間の等価電
圧は、 E’ :電源ON時の電源ON/OFF制御信号VPP
の電圧[V] VCC:スイッチからの出力電圧[V] E=VCC+(E’−VCC)・Rgs/(Rg+Rgs) −VCC・Rg/(Rg+Rgs)[V]・・・・・・・・・・(3) スイッチのゲート・ソース間に加わる電圧は、Von:
スイッチがONする電圧[V] V=VCC+Von−VCC・Rg/(Rg+Rgs)[V]・・・(4) スイッチがOFFなので、スイッチからの出力電圧は、
VCC=0Vである。よって、(3),(4)式は、 E=E’・Rgs/(Rg+Rgs)[V}・・・・・・・・・・・(5) V=Von[V]・・・・・・・・・・・・・・・・・・・・・・・(6) (1)式に(2),(5),(6)式を代入すると、
For example, power on / off with the following parts:
Let us consider the case where an FF sequence circuit is configured. 5V side switch FET1 → ON at 4V, OFF at 2V Gate resistance R1 = 10kΩ Gate-source resistance R3 = 200kΩ Gate-source capacitor C1 = 0.1μF Gate discharge resistance R5 = 200kΩ Diode D1 → VF = 0.6V 3 .3V side switch FET2 → ON at 4V, OFF at 2V Gate resistance R2 = 33kΩ Gate-source resistance R4 = 200kΩ Gate-source capacitor C2 = 0.1μF When power is turned on, switch FET1 and switch FET2 are turned on. When the time is obtained, V: voltage applied between the gate and source of the switch [V] E: equivalent voltage [V] between the power supply ON / OFF control signal VPP and the load circuit C: capacitance between the gate and source [μF] R : equivalent gate resistor [Ω] ton = -C · R · log e (V / E [S] ········ (1) Rg: gate resistance Rgs: gate-source resistance R = Rg · Rgs / (Rg + Rgs) [Ω] ··· (2) The equivalent voltage between the power ON / OFF control signal VPP and the load circuit is E ': the power ON / OFF control signal VPP when the power is ON.
VCC: output voltage from the switch [V] E = VCC + (E′−VCC) · Rgs / (Rg + Rgs) −VCC · Rg / (Rg + Rgs) [V]・ (3) The voltage applied between the gate and source of the switch is Von:
Switch ON voltage [V] V = VCC + Von−VCC · Rg / (Rg + Rgs) [V] (4) Since the switch is OFF, the output voltage from the switch is:
VCC = 0V. Therefore, the equations (3) and (4) are expressed as follows: E = E ′ · Rgs / (Rg + Rgs) [V} (5) V = Von [V] (6) Substituting equations (2), (5) and (6) into equation (1) gives

【0025】[0025]

【数1】 (Equation 1)

【0026】スイッチFET1がONする時間t1を求
めると、電源ON/OFF制御信号VPPとスイッチF
ET1との間にダイオードD1が接続されているため、
E’は、E’=VPP−VF[V]となる。また、ゲー
ト放電抵抗R5は、ゲート抵抗R1に比べて10倍以上
大きいためゲート放電抵抗R5を無視すると、
When the time t1 at which the switch FET1 is turned on is obtained, the power ON / OFF control signal VPP and the switch F
Since the diode D1 is connected to the ET1,
E ′ becomes E ′ = VPP−VF [V]. Further, since the gate discharge resistance R5 is 10 times or more larger than the gate resistance R1, ignoring the gate discharge resistance R5,

【0027】[0027]

【数2】 (Equation 2)

【0028】スイッチFET2がONする時間t2は同
様に、
The time t2 when the switch FET2 is turned on is similarly

【0029】[0029]

【数3】 (Equation 3)

【0030】t1<t2であるため、5VがONしてか
ら3.3VがONすることになる。電源をOFFすると
き、スイッチFET1とスイッチFET2がONする時
間を求めると、 toff=−C・R・loge(V/E)[s]・・・・・・・・・・(9) スイッチのゲート・ソース間に加わる電圧は、 Voff:スイッチがOFFする電圧[V] V=VCC+Voff−VCC・Rg/(Rg+Rgs)[V]・・・(10) (9)式に(2),(3),(10)式を代入すると、
Since t1 <t2, 3.3V is turned on after 5V is turned on. When the power is turned OFF, the seek time switch FET1 and the switch FET2 is ON, toff = -C · R · log e (V / E) [s] ·········· (9) Switch The voltage applied between the gate and the source of Voff is: Voff: The voltage at which the switch is turned off [V] V = VCC + Voff−VCC · Rg / (Rg + Rgs) [V] (10) In equation (9), Substituting equations 3) and (10) gives

【0031】[0031]

【数4】 (Equation 4)

【0032】スイッチFET1がOFFする時間t3を
求めると、
When the time t3 at which the switch FET1 is turned off is obtained,

【0033】[0033]

【数5】 (Equation 5)

【0034】5V側は、遅延回路にダイオードD1が接
続されているためゲート・ソース間コンデンサの放電に
は、ゲート抵抗R1ではなく、ゲート放電用抵抗R5を
経由して電流が流れる。また、電源ON/OFF制御信
号VPPとスイッチFET1との間にダイオードD1が
接続されているため、E’=VPP−VF[V]とな
り、
On the 5V side, because the diode D1 is connected to the delay circuit, a current flows through the gate discharge resistor R5 instead of the gate resistor R1 to discharge the gate-source capacitor. Further, since the diode D1 is connected between the power ON / OFF control signal VPP and the switch FET1, E ′ = VPP−VF [V], and

【0035】[0035]

【数6】 (Equation 6)

【0036】スイッチFET2がOFFする時間t4は
同様に、
The time t4 when the switch FET2 is turned off is similarly

【0037】[0037]

【数7】 (Equation 7)

【0038】t3>t4であるため、3.3VがOFF
してから5VがOFFすることになる。よって、図3の
ような電源ON/OFFシーケンスが守られていること
がわかる。
Since t3> t4, 3.3 V is OFF
Then, 5V is turned off. Therefore, it is understood that the power ON / OFF sequence as shown in FIG. 3 is maintained.

【0039】図3は、上述した本発明の電源ON/OF
Fシーケンス回路におけるタイムチャートである。電源
スイッチONの場合は、第1スイッチからの出力電圧が
先に立ち上がってから第2スイッチからの出力電圧がO
Nとなり、電源スイッチOFFの場合は、第2スイッチ
からの出力電圧が先に立ち上がってから第2スイッチか
らの出力電圧がOFFとなる。
FIG. 3 shows the power ON / OF of the present invention described above.
5 is a time chart in the F-sequence circuit. When the power switch is ON, the output voltage from the first switch rises first and then the output voltage from the second switch becomes O.
N, and when the power switch is OFF, the output voltage from the second switch is turned off after the output voltage from the second switch rises first.

【0040】[0040]

【発明の効果】本発明は、電源ON/OFFシーケンス
を制御する制御回路が無く、遅延回路のみで実現してい
る。従って、簡単な回路で構成されているためコスト的
に安価になるという効果がある。
According to the present invention, there is no control circuit for controlling the power ON / OFF sequence, and only the delay circuit is used. Therefore, there is an effect that the cost is low because the circuit is constituted by a simple circuit.

【0041】また、本発明は、スイッチにN−チャンネ
ルMOSFETを使用している。従って、スイッチでの
損出が少なく、電磁式リレースイッチのようなON/O
FF回路の制限やON/OFF時のチャタリング発生が
ない。
Further, the present invention uses an N-channel MOSFET for the switch. Therefore, there is little loss in the switch, and ON / O like an electromagnetic relay switch is used.
There is no limitation of the FF circuit and no chattering at ON / OFF.

【0042】さらに、遅延回路により負荷への電源立ち
上がりをスロースターとしているため、負荷にコンデン
サなどの静電容量が接続されても電源ON時に発生する
突入電流を抑えることができる。
Further, since the delay circuit uses the rise of the power supply to the load as a slow star, the inrush current generated when the power supply is turned on can be suppressed even when the load is connected to an electrostatic capacity such as a capacitor.

【0043】またさらに、本発明のスイッチ回路では、
スイッチ回路を制御するための制御回路が不要であるた
め、スイッチ回路構成の簡易化が図れる。
Further, in the switch circuit of the present invention,
Since a control circuit for controlling the switch circuit is unnecessary, the configuration of the switch circuit can be simplified.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の回路の構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of a circuit of the present invention.

【図2】本発明の実施例を示す回路図である。FIG. 2 is a circuit diagram showing an embodiment of the present invention.

【図3】本発明の実施例における電源ON/OFF時の
タイムチャートである。
FIG. 3 is a time chart at the time of power ON / OFF according to the embodiment of the present invention.

【図4】従来の装置の構成を示すブロック図である。FIG. 4 is a block diagram showing a configuration of a conventional device.

【図5】従来の装置の電源ON/OFF時のタイムチャ
ートである。
FIG. 5 is a time chart at the time of power ON / OFF of a conventional apparatus.

【符号の説明】[Explanation of symbols]

1 第1電源 2 第2電源 3 負荷回路 4 第1スイッチ 5 第2スイッチ 6 電源ON/OFF制御信号 7 第1遅延回路 8 第2遅延回路 10 連動スイッチ 10a,10b スイッチ部 11 第1リレースイッチ 12 第2リレースイッチ 13 第1電源部第 14 第2電源部 15 第1リレースイッチ制御部 16 第2リレースイッチ制御部 DESCRIPTION OF SYMBOLS 1 1st power supply 2 2nd power supply 3 Load circuit 4 1st switch 5 2nd switch 6 Power supply ON / OFF control signal 7 1st delay circuit 8 2nd delay circuit 10 Interlocking switch 10a, 10b Switch part 11 1st relay switch 12 Second relay switch 13 First power supply unit No. 14 Second power supply unit 15 First relay switch control unit 16 Second relay switch control unit

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】電源ONするときには第1電源をONして
から第2電源をONし、電源OFFするときには、第2
電源をOFFしてから第1電源をOFFするような電源
ON/OFFシーケンスが定められている電源ON/O
FF回路を有する電子装置において、 前記第1電源と、前記第2電源と、前記第1電源と負荷
回路との間に設けられた第1スイッチと、前記第2電源
と負荷回路との間に設けられた第2スイッチとを具備
し、 前記第1スイッチおよび前記第2スイッチをON/OF
Fすることにより、前記負荷回路への電源供給をON/
OFFすることを特徴とする電源ON/OFFシーケン
ス回路。
When the power is turned on, the first power is turned on and then the second power is turned on. When the power is turned off, the second power is turned on.
A power ON / O in which a power ON / OFF sequence for turning off the first power after turning off the power is defined.
An electronic device having an FF circuit, wherein the first power supply, the second power supply, a first switch provided between the first power supply and the load circuit, and a first switch provided between the second power supply and the load circuit. And a second switch provided, wherein the first switch and the second switch are turned on / off.
F, the power supply to the load circuit is turned ON /
A power ON / OFF sequence circuit which is turned off.
【請求項2】前記第1電源が5V電圧源で、前記第2電
源が3.3V電圧源であることを特徴とする、請求項1
に記載の電源ON/OFFシーケンス回路。
2. The power supply according to claim 1, wherein said first power supply is a 5V voltage source, and said second power supply is a 3.3V voltage source.
2. A power ON / OFF sequence circuit according to 1.
【請求項3】前記第1スイッチおよび前記第2スイッチ
を、電源ON/OFF制御信号によって制御することを
特徴とする、請求項1または2に記載の電源ON/OF
Fシーケンス回路。
3. The power supply ON / OF according to claim 1, wherein the first switch and the second switch are controlled by a power supply ON / OFF control signal.
F-sequence circuit.
【請求項4】前記電源ON/OFF制御信号を、N−チ
ャンネルMOSFETを用いて送出することを特徴とす
る、請求項1〜3のいずれかに記載の電源ON/OFF
シーケンス回路。
4. The power ON / OFF according to claim 1, wherein the power ON / OFF control signal is transmitted using an N-channel MOSFET.
Sequence circuit.
【請求項5】前記電源ON/OFFシーケンス回路を実
現するために、前記ON/OFF制御信号と前記第1ス
イッチとの間に第1遅延回路を設けることをことを特徴
とする、請求項1〜4のいずれかに記載の電源ON/O
FFシーケンス回路。
5. A first delay circuit is provided between the ON / OFF control signal and the first switch to realize the power ON / OFF sequence circuit. Power ON / O described in any one of-
FF sequence circuit.
【請求項6】前記電源ON/OFFシーケンス回路を実
現するために、前記ON/OFF制御信号と前記第2ス
イッチとの間に第2遅延回路を設けることをことを特徴
とする、請求項1〜5のいずれかに記載の電源ON/O
FFシーケンス回路。
6. A power supply ON / OFF sequence circuit, wherein a second delay circuit is provided between the ON / OFF control signal and the second switch. Power ON / O described in any one of-
FF sequence circuit.
【請求項7】前記第1電源および前記第2電源を、ノー
トパソコンの電源として使用することを特徴とする、請
求項1〜6のいずれかに記載の電源ON/OFFシーケ
ンス回路。
7. The power ON / OFF sequence circuit according to claim 1, wherein said first power supply and said second power supply are used as a power supply for a notebook personal computer.
JP08215615A 1996-08-15 1996-08-15 Power ON / OFF sequence circuit Expired - Fee Related JP3088298B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP08215615A JP3088298B2 (en) 1996-08-15 1996-08-15 Power ON / OFF sequence circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08215615A JP3088298B2 (en) 1996-08-15 1996-08-15 Power ON / OFF sequence circuit

Publications (2)

Publication Number Publication Date
JPH1066259A true JPH1066259A (en) 1998-03-06
JP3088298B2 JP3088298B2 (en) 2000-09-18

Family

ID=16675351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08215615A Expired - Fee Related JP3088298B2 (en) 1996-08-15 1996-08-15 Power ON / OFF sequence circuit

Country Status (1)

Country Link
JP (1) JP3088298B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000324807A (en) * 1999-05-10 2000-11-24 Seiko Instruments Inc Switching regulator
JP2001170325A (en) * 1999-12-17 2001-06-26 Sanyo Product Co Ltd Control device for game machine
JP2011125146A (en) * 2009-12-10 2011-06-23 Onkyo Corp Power supply control circuit
US8049745B2 (en) 2005-09-16 2011-11-01 Samsung Electronics Co., Ltd. Display apparatus and control method thereof
JP2011233145A (en) * 2010-04-26 2011-11-17 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi Electronic equipment
CN102749856A (en) * 2012-05-30 2012-10-24 曙光信息产业(北京)有限公司 Power-on sequential control circuit and method
JP2016048973A (en) * 2014-08-27 2016-04-07 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2021117669A1 (en) * 2019-12-10 2021-06-17 日立Astemo株式会社 Drive device for electric motor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000324807A (en) * 1999-05-10 2000-11-24 Seiko Instruments Inc Switching regulator
JP2001170325A (en) * 1999-12-17 2001-06-26 Sanyo Product Co Ltd Control device for game machine
US8049745B2 (en) 2005-09-16 2011-11-01 Samsung Electronics Co., Ltd. Display apparatus and control method thereof
JP2011125146A (en) * 2009-12-10 2011-06-23 Onkyo Corp Power supply control circuit
JP2011233145A (en) * 2010-04-26 2011-11-17 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi Electronic equipment
CN102749856A (en) * 2012-05-30 2012-10-24 曙光信息产业(北京)有限公司 Power-on sequential control circuit and method
CN102749856B (en) * 2012-05-30 2016-04-20 曙光信息产业(北京)有限公司 A kind of power-on time sequence control circuit and method
JP2016048973A (en) * 2014-08-27 2016-04-07 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2021117669A1 (en) * 2019-12-10 2021-06-17 日立Astemo株式会社 Drive device for electric motor

Also Published As

Publication number Publication date
JP3088298B2 (en) 2000-09-18

Similar Documents

Publication Publication Date Title
US7061217B2 (en) Integrated power switching circuit
JPH05276737A (en) Booster circuit
US6642750B1 (en) Sequencing circuit for applying a highest voltage source to a chip
JP2002136106A (en) Circuit adapted to receive input voltage, switch mode power converter, and method of operating the circuit
KR970705237A (en) Supply and interface configurable input / output buffers (SUPPLY AND INTERFACE CONFIGURABLE INPUT / OUTPUT BUFFER)
JP3088298B2 (en) Power ON / OFF sequence circuit
US20190081564A1 (en) Method and circuitry for sensing and controlling a current
US20140354258A1 (en) Supply voltage circuit
US7088151B1 (en) High voltage gate driver using a low voltage multi-level current pulse translator
JPH1188159A (en) Charge pump circuit
US7292075B2 (en) Rail-to-rail pad driver with load independent rise and fall times
JPH02500558A (en) Apparatus and method for attenuating transient noise by premagnetizing parasitic inductance
JP3314473B2 (en) Power MOSFET control device
US20050052209A1 (en) Linear voltage tracking amplifier for negative supply slew rate control
JPS63148173A (en) Chopper type comparator
US5872477A (en) Multiplexer with CMOS break-before-make circuit
JP2607304B2 (en) Semiconductor integrated circuit device
JP4362973B2 (en) Voltage level conversion circuit
KR910008925A (en) Power supply circuit for constant voltage regulator with boost switching structure
JPH05335911A (en) Drive circuit
JPH03131916A (en) Constant voltage circuit
JP3912169B2 (en) Driving circuit
JP6613256B2 (en) Protection circuit and load drive circuit
JPH03198421A (en) Semiconductor output circuit
US10186942B2 (en) Methods and apparatus for discharging a node of an electrical circuit

Legal Events

Date Code Title Description
S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070714

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080714

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090714

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100714

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110714

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110714

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees