JPH0582641B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog/digital information recording/reproducing apparatus for recording and reproducing analog information and digital information on a cassette-type magnetic tape under certain record management.

[Technical background of the invention and its problems] Conventionally, magnetic tape recording devices using cassette magnetic tape (hereinafter referred to as CMT) as a recording medium have mainly been used to record and reproduce analog audio when used alone. Instructions such as recording, playback, stop, rewind, fast forward, etc. are left entirely to humans.

Also, when using a cassette type magnetic tape recording device for external recording of a personal computer,
Each command operation, such as starting and stopping, is left to humans. Conventionally, when this cassette-type magnetic tape recording device is connected to a personal computer as external storage, the cassette-type magnetic tape recording device becomes a storage device exclusively for digital data and cannot be used for recording or reproducing analog audio. At this time, by disconnecting the cassette-type magnetic tape recording device from the personal computer and canceling its connection, analog audio can be stored and played back, but there is a gap between analog audio and digital data on the CMT. There are no restrictions whatsoever, and in any case, it is not possible to handle analog audio and digital data in an integrated manner with the same device.

Furthermore, when a cassette-type magnetic data recording device is used as an external storage device for a personal computer, the FM modulation method is generally widely used for recording/reproducing digital data. The relationship between the data bits (“1”, “0”) at this time and the pulse waveform after waveform shaping (after demodulation) during playback is shown in Figure 1.
FIG. 2 shows the relationship between the reproduced signal waveform and the waveform-shaped pulse waveform. In Figure 1, d ₁ =2・
d ₀ , and the signal waveform of “0” has twice the frequency of the signal waveform of “1”.

Here, when reproducing data (during demodulation),
As shown in Figure 2, when converting the reproduced analog voltage waveform into a pulse waveform using a zero-cross circuit to obtain "1" and "0" signals as shown in Figure 1, noise (waveform distortion) V _o is generally present. Therefore, due to the influence of this noise, the timing of signal state transition is shifted by d _o . This deviation, combined with other factors, caused errors in digital data. For this reason, conventionally, there have been problems with reliability when storing digital data as a CMT storage medium.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and is capable of handling analog audio information and digital information in an integrated manner, expanding the usage of a cassette-type magnetic tape recording device, and having an inexpensive structure. I can do it,
Another object of the present invention is to provide an analog/digital information recording and reproducing device that is less susceptible to the effects of noise during digital data demodulation and is capable of recording and reproducing highly reliable digital data.

[Summary of the Invention] The present invention provides a cassette-type magnetic tape recording device that includes an input/output interface section for transmitting and receiving data to and from an external processing unit (CPU), and also provides a ,CMT
A position control mechanism that searches for any recording/playback position on the CMT according to external instructions, and a fixed storage area are installed between each recording/playback circuit provided corresponding to the plurality of channels above and the CMT drive control unit. A one-chip microcomputer with a management mechanism for analog audio information and digital information in units of (constant tape length), a byte assembly control mechanism during data demodulation, etc. is installed, and under the control of this microcomputer, external Specify the recording/playback position according to the instructions (positioning), and analog audio/
The structure is configured to record and reproduce digital data, and thereby a cassette-type magnetic tape recording device that can integrally manage analog audio information and digital information can be realized compactly and at low cost. Furthermore, when assembling the above-mentioned byte, a data demodulation control mechanism is provided that detects a shift in waveform rise timing between bit cells and corrects a part of the shift on a bit cell basis.
This eliminates the influence of noise during data demodulation, greatly reducing the frequency of data errors and improving reliability.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. In the figure, 11 is the upper processing unit (hereinafter referred to as CPU).
12 is a digital input/output interface section for transmitting and receiving information to and from a microphone (MIC), and an output terminal (i.e. This is an analog input/output interface with a speaker (SP) connection end.

13 sends and receives data and various control signals to and from the CPU via the input/output interface section 11, and outputs analog audio information and digital information on a CMT (cassette type magnetic tape) according to instructions from the CPU. It is a one-chip microcomputer (CMTC), for example, equivalent to 8749 or 8748, which controls the recording and playback (writing/reading) of the CPU.
Various information (DATA/STATUS/COMMAND) including write/read data is sent and received via port 1.
Various control information (RD/, /IBF, /
STROBE, PAUSE/, BUSY,
STOP, COM), and also uses port 2 to control the input/output switching of analog audio information/digital information inside the device.
and generation of various control information for mechanism drive control, input/output control, etc.

14 is a CMT control that drives and controls the CMT mechanism under the control of the microcomputer 13 mentioned above;
It is LSI14. CM, AM, RM are each
These are drive motors for the CMT mechanism that are drive-controlled by the CMT control LSI 14, where CM is a capstan motor, AM is an assist motor, and RM is a reel motor.

15 is a recording/playback circuit for the left channel (L-CH), and 16 is a recording/playback circuit for the right channel (R-CH). Here, the right channel (R
-CH) is used as a track (main track) for recording analog audio information and digital information, and the left channel (L-CH) is used as a marker track for recording a marker signal of a specific frequency for positioning. 17 is the left channel (L-
18 is a recording/playback head for the same channel (L-CH), 19 is a recording/playback head for the right channel (R-CH), and 20 is an erase head for the same channel (R-CH). 2
1 is the left channel (L-CH) recording/playback circuit 1
A driver (DRV) 5 supplies a recording signal (marker signal) converted into an analog waveform to a driver (DRV), and a driver (DRV) 22 supplies a recording signal (analog audio/
A driver (DRV) that supplies (digital data),
23 is a zero cross comparator (CMP) that detects the zero cross of the signal (marker signal) reproduced by the left channel (L-CH) recording/playback circuit 15;
4 is right channel (R-CH) recording/playback circuit 1
Zero cross comparator (CMP), 25, which detects the zero cross of the digital data signal reproduced by 6.
is the right channel (R-CH) recording/playback circuit 16
Buffer (BUF) 26 is a buffer buffer (BUF) that voltage amplifies the analog audio signal reproduced by
This is a power amplifier (AMP) that amplifies the power of the analog audio signal obtained from the AMP. 27 and 28 are exclusive OR circuits for inputting the output signal waveforms (pulse waveforms representing bit "1"/"0") of zero cross comparators (CMP) 23 and 24 to the 1-chip microcomputer 13. 29 is a 1-chip microcomputer 13
A latch circuit that latches the CMT mechanism operation level control code output from (port 2), 30
decodes a part of the code latched by the latch circuit 29 and outputs the mechanism drive control signal (FF,
31 is a decoder that generates CMT status information (PAUSE, REC, PLY, REW, STP);
TRBL,／,・・・
Driver (DRV) that shapes the waveform of PROTECT)
It is. 32 is a phototransistor that detects the transparent parts at both ends of the CMT, that is, the start end (BOT) and end end (EOT) of the tape; 33 allows recording and playback only when the CMT used is a chrome tape, and only allows playback when the CMT is a normal tape. The CMT type determination circuit 34 is a solenoid driver that drives the eject solenoid 35. 36 to 39
are switch circuits, and 36 is a marker generation signal (MA) output from bit 1 of port 2 of the 1-chip microcomputer 13, and a write (record) control signal (WD/ENA-S) output from bit 3. 37 is a switch circuit for generating a pulse waveform of a marker signal, 37 is a switch circuit whose switch is controlled by a write (record) control signal (WD/ENA-M) output from the latch circuit 29, and 38 is a switch circuit from the latch circuit 29. A switch circuit 39 is switched on and controlled by the output data selection control signal (・) to enable recording input of digital data, and a switch circuit 39 is switched on and controlled by the inverted data selection control signal (DATA/SEL) to record analog audio. This is a switch circuit that enables input. 40 is an amplifier circuit that amplifies the audio signal of the microphone (MIC), and 41 is a 1-chip microcomputer 13.
The data bits output from bit 0 of port 2 are sent to the right channel (R-CH) recording/playback circuit 16.
This is a buffer (BUF) for supplying to the world.

Figure 4 shows the above-mentioned 1-chip microcomputer 1.
3 is a flowchart showing the processing flow of the entire microprogram in block form. In the figure, 40 is a routine (simple executive) for receiving and interpreting commands, and 41 to 50 are command execution routines, respectively. Among the above command execution routines 41, 42,...50,
REWIND (CMT rewind), EJECT (CMT eject), STOP (CMT stop), and STATUS (CMT
Excluding commands such as mechanism status notification),
READ (reads physical records on CMT as digital data), WRITE (records input data as one physical record on CMT),
PLAY (reading analog audio records),
RECORD (recording analog audio records),
For commands such as FORWARD (CMT forward fast forward (fast forward skip)) and BACKWARD (CMT backward fast forward (high speed backward skip)), the named command execution routines are preprocessing 4iA and Main loop 4iB and post-processing 4iC (i
=2,3,...7).

FIG. 5 is a diagram showing details of the main loop 42A of the READ command execution routine shown in FIG. 4 above. One round of this main loop corresponds to reading one byte of data, and each step 50, 51, . . . , 57 corresponds to each bit forming one byte. 50 steps each,
51,...57 are three substeps 5i1, 5i2, 5i3
(i=0, 1,...7). Among these, substeps 5i2 and 5i3 are each step 50, 51, 52,...
57, this routine reads the signal waveform recorded in the CMT and stores 1 bit in the byte assembly buffer. Also, substep 5i1
is a routine that sends data assembled into bytes to the CPU, and its work is divided into steps. That is, in substep 501 of step 50, the contents of the byte assembly buffer are transferred to a buffer for data transfer, and in substep 511 of step 51, the content of the byte assembly buffer is transferred to a buffer for data transfer.
Then, the buffer pointer and buffer management counter are updated and the substeps of steps 52 and 56 are executed.
521 and 561, the 1-byte data stored in the buffer is sent via the input/output interface section 11.
In substeps 531 and 571 of steps 53 and 57, the buffer pointer and buffer management counter are updated. In substep 541 of step 54, the byte counter and block counter are updated. 551 performs an error check.

FIG. 6 is a diagram showing the correspondence between one bit of step 5i (i=0, 1, 2, . . . 7) in FIG. 5 and the CMT read signal waveform. Here, the substep 5i3 is a substep (timing adjustment routine) for maintaining the synchronization relationship of the execution timing of steps according to the waveform, and here it is further divided into 5i4 and 5i5. Of these, 5i4
5i5 is a routine (timing detection routine) that detects the timing of the waveform rise between bit cells, and 5i5 is a routine (timing adjustment routine) that adjusts the start timing of the next step (5i+1) according to the timing.

FIG. 7 is a diagram showing the details of substep (timing adjustment routine) 5i3 in FIG. 6, and approximately the left half of the diagram is the timing detection routine.
5i4, and the right half corresponds to the timing adjustment routine.

Here, the operation of one embodiment will be explained with reference to FIGS. 3 to 7. The CPU sends commands/data to the 1-chip microcomputer 13 via the input/output interface section 11. When sending a command, a control signal COM is sent at the same time. This causes an interrupt in the firmware of the 1-chip microcomputer 13, and a command interpretation routine (40 in FIG. 4) is activated. Then, under the control of the 1-chip microcopy computer 13, a mechanism operation level control code according to the input command is latched in the latch circuit 29, and a part of the code is decoded by the decoder 30 and supplied to the CMT control LSI 14. The CMT is drive controlled by this. On this occasion,
The decoder 30 selectively outputs mechanism drive control signals such as FF (fast forward), PAUSE (pause), REC (recording), PLY (playback), REW (rewind), STP (stop), etc. The CMT control LSI 14 drives the CMT mechanism by controlling the drive control signal and the output signal from the CMT type determination circuit 33, thereby driving the CMT.

Furthermore, a part of the control code output from the one-chip microcopy computer 13, and a part of the control code latched in the latch circuit 29 (WD/
ENA-S, WD/ENA-M, DATA/SEL) switch circuits 36, 37, 38, and 39 are selectively turned on, and the control signals (REC, POUSE) output from the CMT control LSI 14 , left channel (L-CH) recording/playback circuit 1
5 and the right channel (R-CH) recording/reproducing circuit 16 are controlled to record/reproduce digital data or analog audio.

That is, for example, in the case of a WRITE command, the command execution routine 43 shown in FIG. 4 is activated,
Next, the data sent via the bus is treated as one physical record, and the signal waveform that follows that data is created.
Record on CMT. In this case, the pulse waveform according to the data bit as shown in FIG.
1-switch circuit 37-switch circuit 38 to the driver (DRV) 22, is converted into an analog waveform with +/- amplitude, and is sent to the right channel (R
-CH) is supplied to the recording/playback circuit 16. Furthermore, at this time, the pulse waveform of the marker signal is output from bit 1 of port 2 of the 1-chip microcomputer 13 at fixed time intervals, and this signal is sent to the driver (DRV) 21 via the switch circuit 36. After being converted into an analog waveform in the same manner as described above, the signal is supplied to the left channel (L-CH) recording/playback circuit 15. At this time, the output terminals of the drivers (DRV) 21 and 22 have a zero potential when the switch is off, and are amplified +/- according to the input waveform only when the switch is on.

This allows the right channel (R-CH) on the CMT to
The data signal waveform is recorded by the recording/playback circuit 16 and the recording/playback head 19, and the left channel (L-CH) is recorded by the recording/playback circuit 1.
5 and the recording/playback head 17 record marker signal waveforms at constant physical record intervals.

Further, in the case of a RECORD command, the command execution routine 45 shown in FIG. 4 is activated, and the analog voice waveform according to the voice message input from the microphone (MIC) is recorded in the CMT in a fixed physical record unit. . At this time, the audio signal input from the microphone (MIC) is recorded/played on the right channel (R-CH) via the input/output interface section 12 - amplifier circuit 40 - switch circuit 39 - driver (DRV) 22. circuit 16
Right channel (R-CH) on CMT
recorded in At this time, as well as when executing the WRITE command above, the marker signal waveform changes to the left channel (L-CM) with a certain physical record interval.
recorded in

Also, FORWARD command or BACKWARD
In the case of a command, a command execution routine 46 or 47 shown in FIG. 4 is activated, and the CMT is advanced or retracted at high speed by the number of frames designated by the CPU. At this time, the recording state on the CMT is monitored and positioned while the CMT is running at a high speed of about 20 to 30 times the speed of executing commands such as READ and PLAY. Furthermore, at this time, high-speed skipping is performed while monitoring the number of markers in order to detect the stop position. In addition, during the above-mentioned high-speed skip, it is difficult to stop the CMT quickly due to its large inertia, so in the final stage of positioning, a firmware control means is used to make the CMT run at a low speed and stop at the desired marker point. It's getting better.

Next, the execution processing operation of the READ command will be explained. When this READ command is issued, the command execution routine 42 shown in FIG. 4 is activated, reads the next physical record as digital data, and transfers the read data in bytes to the CPU. At this time, the read signal (playback signal) output from the right channel (R-CH) recording/playback circuit 16 is zero-cross detected by the zero-cross comparator (CMP) 24, converted into a pulse waveform, and then converted into an exclusive OR signal. It is supplied to the test input terminal (TO) of the one-chip microcomputer 13 through the circuit 27, and the READ signal as shown in FIGS.
After being converted into digital data by a command execution routine, byte assembly processing is performed. Furthermore,
During this byte assembly, a shift in waveform rise timing between bit cells is detected, and a portion of the shift is corrected for each bit cell.

This operation will be explained with reference to FIGS. 5 to 7.

FIG. 5 shows details of the main loop 42A of the READ command execution routine shown in FIG. One round of this main loop corresponds to reading one byte of data, and each step 50, 51, . . . 57 corresponds to each bit (bit7 to bit0) constituting one byte. Each step 50, 51,...57 has three substeps 5i1,
Divided into 5i2 and 5i3 (i=0, 1,...7). Of these, substeps 5i2 and 5i3 are each step 50,
This routine is common to 51, 52, . . . 57, and reads the signal waveform recorded in the CMT and stores 1 bit in the byte assembly buffer. Also, substep 5i1 processes the data assembled into bytes.
This is a routine sent to the CPU, and as mentioned above, the work is divided for each step. On this occasion,
The data transmission to the CPU and the corresponding pointer update routine are executed twice for each byte read, as is clear from the description of FIG. 5 above. As a result, the data accumulated in the buffer when the CPU is busy gradually decreases when the CPU becomes free, and the buffer is usually in an empty state.

FIG. 6 shows the correspondence between the 1-bit step 5i (i=0, 1, 2, . . . , 7) in FIG. 5 and the CMT read signal waveform. Here, discrimination as to whether the waveform represents "1" or "0" is performed in substep 5i2. The waveform is sensed three times as indicated by the arrows in the waveform, "1"/"0" is identified by majority vote, and the bit is placed in the byte assembly buffer. Substep 5i3 is
This is a substep (timing adjustment routine) that maintains the synchronization of step execution timing according to the waveform, and here we will further explain 5i4 and 5i5.
It is divided into Of these, 5i4 is a routine (timing detection routine) that detects the timing of waveform rise between bit cells, and 5i5 is a routine (timing adjustment routine) that adjusts the start timing of the next step (5i+1) according to that timing. It is. 5i1, 5i2 and 5i4 are all i=
The execution time is the same for all 0 to 7, but
The execution time of 5i5 changes depending on the rising timing detected by 5i4.

Figure 7 shows details of substep (timing adjustment routine) 5i3 in Figure 6 above.
Approximately the left half of the diagram is timing detection routine 5i4
The right half is the timing adjustment routine.
Equivalent to 5i5. The waveform is sensed in steps 70, 72, 74, and 76 of the left half corresponding to the timing detection routine 5i4, and the rising timing is classified into five cases. Steps 70, 72, 74,
76 waveform sense timings are shown in Figure 6 for st1,
Shown as st2, st3, and st4. Then, the steps on the right half corresponding to timing adjustment routine 5i5.
At 80, 81, 82, 83, and 84, a delay (1/2 correction of the waveform shift time) is taken depending on each case. On this occasion,
In the actual configuration, each of the above steps 70, 71, 72,...
77, 80, 81, ...84 are each set to 2 machine cycles, and steps 71, 73, 75, 77,
Since steps 50, 51, 52, 53, and 54 are all steps whose main purpose is to obtain timing, no data processing is performed here (actually, NOP is executed twice). Therefore, in the timing adjustment routine shown in FIG. 7, when the route of steps 70-71-72...77-84 is taken, the timing adjustment time is the longest and
The timing adjustment time is the shortest when taking the route 70-80, 81...84. For example, the sixth
For the reference waveform A shown in the enlarged part of the figure, waveform B
If the waveform rise timing between bit cells rises earlier than the standard timing by a range of 2 to 6 machine cycles, then in the case of the standard timing (waveform deviation is within 2 machine cycles before and after; Route [70 within T time shown in Figure 6]
→71→72→73→74→82→83→84], [70
→71→72→81→82→83→84], and the execution time of substep 5i3 is longer by two machine cycles (T) than in the case of the standard timing. That is, half of the deviation from the standard timing is corrected.

In this way, when assembling the bit, the deviation in waveform rise timing between bit cells is corrected each time.

Therefore, the influence of noise during data demodulation is eliminated, and the frequency of occurrence of data errors is significantly reduced.

In the above embodiment, the control code output from port 2 of the one-chip microcomputer 13 is temporarily latched by the latch circuit 29, but this latch is not necessarily required. , Also, the recording/playback circuit 1
5 and 16, the configuration of the input/output interface unit 12, the configuration of the CMT type determination circuit 33, etc., are not limited to the above embodiments, and the present invention can be easily realized with other configurations. It is.

〔Effect of the invention〕

As described in detail above, according to the present invention, a cassette-type magnetic tape recording device is provided with an input/output interface unit for transmitting and receiving data with an external processing unit (CPU), and an input/output An arbitrary recording/playback position on the CMT can be set between the ace section and each recording/playback circuit provided corresponding to multiple channels on the CMT (magnetic tape) and the CMT drive control section according to instructions from the outside. A one-chip microcomputer with a position control mechanism for searching, a management mechanism for analog audio information and digital information in units of fixed storage area (fixed tape length), and a byte assembly control mechanism during data demodulation is installed. Under the control of a computer, the designation of the recording/playback position according to external instructions (positioning) and the recording/playback of analog audio/digital data are configured to allow analog audio information and digital information to be integrated. A manageable cassette type magnetic tape recording device can be realized compactly and at low cost. Furthermore, when assembling the above tool,
By providing a data demodulation control mechanism that detects deviations in waveform rise timing between bit cells and corrects some of the deviations on a bit cell basis,
It is possible to eliminate the influence of noise during data demodulation, significantly reduce the frequency of data errors, and significantly improve reliability.

[Brief explanation of the drawing]

1 and 2 are signal waveform diagrams for explaining conventional data reproducing means, respectively. FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a diagram of the signal waveform in the above embodiment. A diagram showing the microprogram structure of a 1-chip microcomputer, Figure 5 is a diagram showing the main loop structure of the READ command execution routine in the above embodiment, and Figure 6 is a diagram showing the 1 bit when assembling a byte in the above embodiment. FIG. 7 is a diagram showing the processing steps of the timing adjustment routine in the above embodiment. 11, 12...Input/output interface section, 13
...1 chip microcomputer, 14...
CMT control LSI, 15, 16...recording/playback circuit,
17, 19... Recording/playback head, 18, 20...
... Erase head, 21, 22, 31 ... Driver (DRV), 23, 24 ... Zero cross comparator, 25 ... Buffer (BUF), 26 ... Power amplifier (AMP), 27, 28 ... Exclusive OR circuit , 29...Latch circuit, 30...Decoder, 32...Phototransistor, 33...
CMT type determination circuit, 34... Solenoid driver, 35... Solenoid, 36, 37, 38,
39...Switch circuit, 40...Amplification circuit,
MIC...Microphone, SP...Speaker.

Claims (1)

[Claims] 1. A magnetic tape in which a cassette-type magnetic tape is used as a recording medium, a plurality of channels are formed on the recording medium, and digital information or analog audio information is selectively recorded in at least a first specific channel. In the recording device, the input/output interface is connected between an input/output interface unit that transmits and receives digital information to and from an external processing device, a plurality of recording/reproducing circuits corresponding to each of the channels, and a mechanism drive control unit. A means for sending a drive command to the mechanism drive control section based on control information input from the outside via an interface section, and inputting a signal of analog information to a recording/reproducing circuit corresponding to the first specific channel. means for transmitting a switching signal for selectively connecting a signal input path for digital information or a signal input path for digital information; and means for inputting a marker signal reproduced and waveform-shaped by the recording and reproducing circuit corresponding to the second specific channel during reproduction, and controlling the tape movement amount in accordance with the signal. , a one-chip microcomputer having byte assembling means for digital information reproduced and waveform-shaped by a recording/reproducing circuit corresponding to the first specific channel, and under the control of the one-chip microcomputer, An analog/digital information recording/reproducing device characterized in that analog audio information or digital information is read and written in units of areas separated by the marker signals according to external instructions. 2. The analog/digital information recording and reproducing apparatus according to claim 1, wherein when assembling the byte, a shift in waveform rise timing between bit cells is detected, and a part of the shift is corrected for each bit cell.