JPH0582209A - System malfunction preventing method in connecting cables - Google Patents

Abstract

PURPOSE:To prevent malfunction in connecting cables by transmitting the output of a level signal from a gate section to a unit under operation via plural cables. CONSTITUTION:A transmission line 750 which transmits a control signal from a control signal generation section 105 provided in an additional unit 200, turned back at a unit 100 under operation and the additional unit 200 via cables 700-1 through 700-n in sequence, is accepted between the unit 100 and the unit 200. When connection to the output end of the transmission line 750 is performed and the unit 100 under operation is correctly connected to the unit 200 via the cables 700-1 through 700-n, the output control signal from the generation section 105 input via the transmission line 750 is output. When erroneous connection occurs, a signal different from the control signal is output with a preset time delay in a delay section 110. In this way, a correctly connected main signal is output, and when erroneous connection occurs a fixed level signal is output to a gate section 130 in the unit 200. Then, transmission is performed from time gate section 130 to the unit 100 to prevent the malfunction of a system in connecting the cables.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system malfunction preventing method when a plurality of cables are connected in a system in which signals are transmitted and received between a rack in operation and an extension rack via cables.

With the progress of the information-oriented society, the signals transmitted by the network are diversifying and increasing in speed, and in order to meet the needs, recent transmission systems are increasing in capacity. For this reason, even in the past, signal processing, which could be processed by one rack, has begun to be adopted by a plurality of racks due to lack of capacity.

In operating a system using a plurality of racks,
It is desirable to be able to freely add or remove racks for the purpose of increasing the line capacity of the system. For example, if you want to increase the number of lines that can be serviced on the rack that is already in operation, remove one from the system that does not currently require a relatively large capacity and use this as an additional rack for efficient system operation. Becomes

[0004] Especially when adding a rack, various cable connections between the racks are required. Each rack has a separate C for high-grade system control and monitoring.
It is necessary to install a PU (processor), but this CP
As in this example, the communication cable between U must also be connected. CP connected when connecting this cable
In many cases, an erroneous signal (whisker, chattering, etc.) occurs in various signals between U. This erroneous signal may affect the control and monitoring of the rack during operation and cause a malfunction, or the frequent occurrence of erroneous signals may cause the CPU to exceed the processing capacity and cause a failure of the CPU.

Further, it is desirable that the number of CPU control cables for connecting the racks to be one, but due to the limitation of the number of signals and the wiring method to the connector, it is sometimes necessary to use a plurality of cables. Many.

Therefore, there is a demand for a malfunction prevention system for preventing malfunction of the system when a plurality of cables are connected.

[0007]

2. Description of the Related Art FIG. 9 is a diagram showing an example of connection of a rack with a plurality of cables. In the system described above, conventionally, the CPU often malfunctioned while all the cables were connected.

[0008] For example, as shown in FIG.
When connecting signals between the respective CPUs 3 and 4 of the rack 2 to be added thereto by the three cables A, B, and C, the cable A has interrupt signals and address signal lines from the rack 2 to be added, The cable B is provided with a select signal and other control signal lines from the rack 1 in operation, and the cable C is provided with a data line.

At this time, if the cables A, B, and C are connected in this order, CP will be generated when the cables A and B are connected.
U3 and 4 judge that they can operate each other and start communication, but since the cable C is not connected, undefined data is exchanged with each other, and the CPU 3 or (and) 4 malfunctions.

Furthermore, when connecting a plurality of cables for communication between CPUs, it is fully expected that a connection error will occur during work, and if this is detected, an alarm will be issued or the CPU will be connected until the connection is completed without error. The current situation is that sufficient measures have not been taken to prevent such malfunctions.

[0011]

As described above, in the prior art, the CPU malfunctions when a plurality of cables are connected, and C
There has been a problem that measures for preventing malfunction of the PU have not been taken sufficiently.

Therefore, an object of the present invention is to provide a malfunction prevention system for preventing malfunction of the system when a plurality of cables are connected.

[0013]

The above problems can be solved by the circuit configuration shown in FIG. 1 or 2. In FIG. 1 showing the first invention, an extension rack 200 is connected to a rack 100 in operation by a plurality of cables 700-1 to 700-n, and is being operated via a plurality of cables 700-1 to 700-n. In a system in which signals are transmitted and received between the rack 100 and the extension rack 200, the control signal output from the control signal generator 105 provided in the rack 200 is passed through the cables 700-1 to 700-n sequentially. A transmission line 750 is provided between the operating rack 100 and the additional rack 200 so that the transmission line 750 is returned between the operating rack 100 and the additional rack 200 for transmission and output.

When the rack 100 which is connected to the output end of the transmission line 750 and is in operation by a plurality of cables 700-1 to 700-n and the extension rack 200 are correctly connected, the data is input through the transmission line 750. The control signal output from the control signal generation unit 105 and the delay unit 110 that delays a signal different from the control signal for a predetermined time when the connection is incorrect, and the main signal and the output from the delay unit 110 are input. , A gate unit 130 that outputs a main signal when the rack 100 in operation and the extension rack 200 are correctly connected by a plurality of cables 700-1 to 700-n, and outputs a signal of a certain level when they are connected incorrectly. And are installed on the extension rack 200.

The output of the gate unit 130 is transmitted to the rack 100 in operation via the plurality of cables 700-1 to 700-n. Next, referring to FIG. 2 showing the second invention, an extension rack 200 is provided with a plurality of cables 700-
Multiple cables 700-1 to 700-, connected by 1 to 700-n
In a system in which signals are transmitted and received between the rack 100 in operation and the extension rack 200 via n, the control signal output from the control signal generation unit 108 provided in the rack 100 in operation is transmitted to a plurality of cables 700- A transmission line 750 is provided between the operating rack 100 and the additional rack 200, and the transmission line 750, which passes through 1 to 700-n in sequence and is returned by the operating rack 100 and the additional rack 200 for transmission and output.

Further, when the rack 100 which is connected to the output end of the transmission line 750 and is in operation by the plurality of cables 700-1 to 700-n and the extension rack 200 are properly connected, input is made via the transmission line 750. The control signal output from the control signal generation unit 108, and a delay unit 210 that delays a signal different from the control signal for a predetermined time when it is erroneously connected and outputs the main signal and the output from the delay unit 210 are input. , The gate unit 190 that outputs the main signal when the rack 100 in operation and the extension rack 200 are correctly connected by a plurality of cables 700-1 to 700-n, and outputs a signal of a certain level when they are connected incorrectly. And are installed on the rack 100 in operation.

[0017]

[Operation] Referring to FIG. 1, in the delay section 110, a rack 100 and an extension rack 200 which are in operation by a plurality of cables 700-1 to 700-n are used.
When and are correctly connected, the control signal (for example, the signal of the ground potential) output from the control signal generator 105 input through the transmission line 750 is input, and when they are connected incorrectly, a signal different from the control signal (for example, "H The "level signal" is output after being delayed by a predetermined time (for example, two clocks).

Next, for example, the main signal of the output of the CPU in the extension rack 200 and the output of the delay unit 110 are input to the gate unit 130, and the rack 100 being operated by a plurality of cables 700-1 to 700-n.
And the extension rack 200 are correctly connected, the gate unit 130
Outputs a main signal, and when it is erroneously connected, it outputs a constant level signal (for example, "H" level signal).

Then, the output of the gate unit 130 is transmitted to the rack 100 in operation via a plurality of cables 700-1 to 700-n. As a result, the gate unit 130 outputs the main signal or a signal of a certain level at a timing delayed by the delay unit 110 for a predetermined time (for example, two clocks) from the time when the plurality of cables 700-1 to 700-n are connected. Therefore, due to an erroneous signal immediately after connecting the cable, for example, the C
It is possible to prevent the PU from malfunctioning.

Further, in FIG. 2, in the delay unit 210,
When the rack 100 in operation and the extension rack 200 are correctly connected by a plurality of cables 700-1 to 700-n, the control signal of the output of the control signal generator 108 input via the transmission line 750 (for example, ground potential Signal), or a signal different from the control signal (for example, an "H" level signal) when it is erroneously connected, is delayed by a predetermined time and then output.

Next, from the extension rack 200 to a plurality of cables 700-
Input the main signal via 1 to 700-n or the output of the delay unit 210 to the gate unit 190, and connect multiple cables 700-1 to 700-n.
The gate unit 190 outputs a main signal when the rack 100 in operation and the extension rack 200 in operation are correctly connected, and outputs a constant level signal (for example, a "H" level signal) when they are incorrectly connected.

As a result, a plurality of cables 700-1 to 700-n
Since the delay unit 210 delays a predetermined time (for example, two clocks) from the time when the circuit is connected, the gate unit 190 outputs the main signal or a signal of a certain level, which is added to the CPU of the rack 100 in operation, for example. , It is possible to prevent the CPU of the rack 100 in operation from malfunctioning due to a false signal immediately after connecting the cable.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram showing a circuit configuration of a first embodiment of the first invention. FIG. 4 is a time chart for explaining the operation of the embodiment.

FIG. 5 is a diagram showing an example of incorrect connection of cables in the embodiment. FIG. 6 is a block diagram showing the configuration of the circuit of the second embodiment of the first invention. FIG. 7 is a block diagram showing the configuration of the circuit of the first embodiment of the second invention.

FIG. 8 is a block diagram showing the configuration of the circuit of the second embodiment of the second invention. The same reference numerals denote the same objects throughout the drawings. In FIG. 3, when adding the extension rack 2 to the rack 1 in operation, the connectors 8-1 to 8- of the rack 1 in operation
n (for example, n = 3) and the connectors 9-1 to 9-n of the extension rack 2 are connected by cables 7-1 to 7-n. When these connectors and cables are properly connected, C of the extension rack 2
The ground potential inside the PU board 6 is connector 9-1, cable 7-1.
, The transmission line is transmitted through the connector 8-1, is folded back inside the CPU board 5 of the rack 1 in operation, and this transmission line is expanded again through the connector 8-1, cable 7-1 and connector 9-1. Rack 2
Internally connected to connector 9-2.

In the same manner as above, the connector 9-2 and the cable
7-2, connector 8-2 to connector 8-n, cable 7-n, connector 9-n, the above ground potential is CP of extension rack 2
It is added to the inverter 10 in the U board 6.

In the inverter 10, the ground potential "0"("L")
The "level" signal is inverted and a "1"("H" level) signal is output and added to the D terminal of the flip-flop circuit (hereinafter referred to as FF) 11. This is shown in FIG. In FF11, "1" is output from the Q terminal by the clock applied to the C terminal, and FF12
Add to the D terminal of. The FF12 also outputs "1"("H" level) from the Q terminal according to the clock applied to the C terminal and branches the result, and the NAND circuit (hereinafter referred to as "NAND circuit") 13-1 ~
Add to one input terminal of 13-n. (Refer to FIG. 4.) The main signal is added from the CPU 4 of the extension rack 2 to the other input terminal of the NAND circuits 13-1 to 13-n.
Since the signal of "1"("H" level) is applied to one input terminal of the NAND circuits 13-1 to 13-n, the main signal input from the CPU 4 is input from the NAND circuits 13-1 to 13-n. Is inverted and output.
This main signal is connected to connectors 9-1 to 9-n, cable 7-
It is transmitted to the CPU 3 of the rack 1 in operation via 1 to 7-n and connectors 8-1 to 8-n.

As a result, as shown in FIG. 4, since the main signals are inverted and output from the NAND circuits 13-1 to 13-n at the timing delayed by two clocks from the time when the cable is connected, The erroneous signal immediately after connecting the cable can be masked to prevent the erroneous operation due to the erroneous signal in the CPU 3 of the rack 1 in operation.

Next, if the cables are erroneously connected, for example, as shown in FIG.
Incorrectly connect the other ends of cables 7-1 and 7-2 connected to 9-1 and 9-2 to connectors 8-1 and 8-2, and connect them to connectors 8-2 and 8-1 respectively. Connector 8-2
Since the pin numbers (2) and (3) are connected by folding back (shown by the bold line in the figure), the pin number (1) of the connector 9-1
The ground potential reaching the connector 8-2 from the cable via the cable 7-1 is not folded back and connected at the connector 8-2.

Similarly, the connector 8-1 has a pin number (1) and
Since (2) and (2) are connected in a folded manner (shown by the bold line in the figure), the ground potential that reached from the pin number (2) of connector 9-2 to connector 8-1 via cable 7-2 is
Connect it back to pin number (1) at 8-1 and connect the cable 7-
Returned to the main signal line via 2.

As a result, the ground potential ("L" level) is not applied to the inverter 10 of the extension rack 2 shown in FIG. 3, and a preset "H" level (for example, +5 V) signal is applied, so that the inverter 10 An inverted "L" level signal is output from 10 and applied to the D terminal of FF11. In the FF11, the "L" level signal is output from the Q terminal by the clock applied to the C terminal and is added to the D terminal of the FF12. In the same manner, the FF12 also outputs the "L" level signal from the Q terminal by the clock input.
Add to one input terminal of NAND circuits 13-1 to 13-n.

In the NAND circuits 13-1 to 13-n, since the "L" level signal is input to one of the input terminals as described above, the C
The output becomes "H" level regardless of the signal input from the PU4, and the CPU3 of the rack 1 in operation is the CP of the extension rack 2.
The operation is continued without being affected by the connection with U4.

Next, a second embodiment of the first invention will be described with reference to FIG. 6 is different from the circuit shown in FIG. 3 in that the FF11 and FF12 shown in FIG. 3 are replaced with a status register 14 and a write register 15, respectively.
The delay circuit function of FF11 and FF12 is performed by the status register 14 and the write register 15 by the control signal from the CPU 4 using the CPU bus. This will be described in detail below.

In FIG. 6, when the rack 1 in operation and the extension rack 2 are correctly connected by the cables 7-1 to 7-n, the inverter 10 of the extension rack 2 is grounded in the same manner as described with reference to FIG. The "L" level signal of the electric potential is input, and the inverter 10
"H" level signal output is inverted by the status register
Input to 14 and stored. The CPU 4 reads the data stored in the status register 14 through the CPU bus, but since the read signal is an "H" level signal, it reads N times (N clocks, for example, 2 clocks) and "H".
The "H" level signal is input to and stored in the write register 15 only when the level signal continues. Then, it is read at the next clock from the CPU 4 and added to one of the input terminals of the NAND circuits 13-1 to 13-n.

The main signal is applied from the CPU 4 of the extension rack 2 to the other input terminal of the NAND circuits 13-1 to 13-n, but as described above, one input terminal of the NAND circuits 13-1 to 13-n. Is "H"
NAND circuits 13-1 to 13-n are added because level signals are added.
Output the inverted main signal input from the CPU 4. Then, this main signal is transmitted to the CPU 3 of the rack 1 in operation via the connectors 9-1 to 9-n, the cables 7-1 to 7-n, and the connectors 8-1 to 8-n.

As a result, from the time when the cable is connected, N
Since the main signal is inverted and output from the NAND circuits 13-1 to 13-n at a timing delayed by a clock (for example, 2 clocks), an error signal immediately after connecting the cable causes the rack 1 in operation to operate. It is possible to prevent the CPU 3 from malfunctioning.

Next, if the cable is erroneously connected, the ground potential ("L" level) is not applied to the inverter 10 of the extension rack 2 as described with reference to FIG. 3, and the preset "H" is set.
Since a level (for example, + 5V) signal is applied, an inverted "L" level signal is output from the inverter 10 and input to the status register 14 for storage.

The CPU 4 reads the data stored in the status register 14 through the CPU bus, but since the read signal is the "L" level signal, it is immediately input to the write register 15 and stored. Then, the next clock from the CPU 4 reads from the write register 15 to read the NAND circuit.
Add to one input terminal of 13-1 to 13-n. NAND circuit 13-1 ~
In 13-n, since the "L" level signal is input to one of the input terminals, the output becomes "H" level regardless of the signal input from the CPU4, and the CPU3 of the rack 1 in operation is connected to the extension rack 2. The operation is continued without being affected by the connection with the CPU 4.

Next, the first embodiment of the second invention will be described with reference to FIG. The circuit shown in FIG. 7 corresponds to the first circuit shown in FIG.
3 is different from the invention of FIG. 3 in that the circuit provided in the extension rack 2 of FIG. 3 is provided in the operating rack 1'instead of being provided in the extension rack 2'shown in FIG. 7, and the ground potential is transmitted by the extension rack 2 '. I tried to turn the road back. This will be described in detail below.

In FIG. 7, when the rack 1'in operation and the extension rack 2'are correctly connected by the cables 7-1 to 7-n, the "L" level signal of the earth potential in the rack 1'in operation is connected. Is folded back at extension rack 2'through connector 8-1, cable 7-1 and connector 9-1 and then again connected to connector 9-1 and cable 7-1.
, And is returned to the rack 1'in operation via the connector 8-1.
Since this transmission line is connected to connector 8-2, the ground potential is connector 8-2, cable 7-2, connector
9-2 is transmitted, then the connector and cable are sequentially transmitted, and the output of connector 8-n is the inverter in the rack 1'in operation.
The signal is input to the inverter 16, inverted by the inverter 16, and the "H" level signal output is applied to the D terminal of the FF17.

In the FF17, the "H" level signal is output from the Q terminal in response to the clock applied to the C terminal, and the D signal of the FF18 is output.
Added to the terminal. Similarly, in the FF18, the "H" level signal is output from the Q terminal by the clock and the NAND circuit 19
-1 to 19-n applied to one input terminal.

A main signal is applied from the CPU 4 of the extension rack 2'to the other input terminal of the NAND circuits 19-1 to 19-n, but as described above, one input of the NAND circuits 19-1 to 19-n. "H" on the terminal
NAND circuits 19-1 to 19-n are added because level signals are added.
From CPU 4 to connectors 9-1 to 9-n, cable 7-1
.. 7-n, main signals input via connectors 8-1 to 8-n are inverted and output, and added to the CPU 3.

As a result, from the time when the cable is connected, F
NAND with timing delayed by 2 clocks by F17 and 18
Since the main signals are inverted and output from the circuits 19-1 to 19-n, it is possible to prevent the CPU 3 from malfunctioning due to a false signal immediately after the cable is connected.

Next, the case where the cable is erroneously connected will be described in the same manner as the case of the first embodiment in FIG. That is, the ground potential ("L" level) is not applied to the inverter 16 of the extension rack 1'shown in Fig. 7, and the preset "H" level is set.
Since a signal (for example + 5V) is applied,
The inverted "L" level signal is output from 16 and applied to the D terminal of FF17. In the FF17, the "L" level signal is output from the Q terminal by the clock applied to the C terminal and the D of the FF18 is output.
In addition to the terminals, the FF18 also outputs the "L" level signal from the Q terminal by the clock input in the same manner and outputs the NAND circuit 19-1 to
Add to one input terminal of 19-n.

In the NAND circuits 19-1 to 19-n, since the "L" level signal is input to one of the input terminals, the CP of the extension rack 2'is
The output becomes "H" level regardless of the signal input from U4, and the CPU3 of the rack 1'in operation is the C of the extension rack 2 '.
The operation is continued without being affected by the connection with PU4.

Next, the circuit of the second embodiment of the second invention is shown in FIG. 8. In FIG. 8, the FFs 17 and 18 of the circuit of FIG. 7 are replaced with the status register 20 and the write register 21, respectively, and FF17 , FF18, the delay circuit function is performed by the status register 20 and the write register 21 in response to a control signal from the CPU 3 using the CPU bus. Since the operation is the same as that of the second embodiment of the first invention shown in FIG. 6, the description thereof will be omitted.

As a result, when connecting the rack under operation and the extension rack, it is possible to prevent malfunction of the system when a plurality of cables are connected.

[0048]

As described above, according to the present invention, it is possible to prevent a malfunction of the system when connecting a rack in operation and an extension rack and connecting a plurality of cables.

[Brief description of drawings]

FIG. 1 is a principle diagram of the first invention,

FIG. 2 is a principle diagram of the second invention,

FIG. 3 is a block diagram showing a circuit configuration of a first embodiment of the first invention,

FIG. 4 is a time chart for explaining the operation of the embodiment,

FIG. 5 is a diagram showing an example of incorrect connection of cables in the embodiment,

FIG. 6 is a block diagram showing a circuit configuration of a second embodiment of the first invention,

FIG. 7 is a block diagram showing a circuit configuration of a first embodiment of the second invention,

FIG. 8 is a block diagram showing a circuit configuration of a second embodiment of the second invention,

FIG. 9 is a diagram showing an example of connection of a rack with a plurality of cables.

[Explanation of symbols]

100 is a rack under operation, 200 is an extension rack, 105 and 108 are control signal generators, 110 and 210 are delay units, 130 and 190 are gate units, 700-1 to 700-n are cables, and 750 is a transmission line. Show.

Claims (2)

[Claims] 1. An extension rack (200) is connected to an operating rack (100) by a plurality of cables (700-1 to 700-n), and the plurality of cables (700-1 to 700-n) are used. In a system in which signals are transmitted and received between the rack (100) in operation and the extension rack (200), the control signal output from the control signal generator (105) provided in the extension rack (200) A transmission line (750) for transmitting and outputting the data through the plurality of cables (700-1 to 700-n) in sequence through the rack (100) in operation and the extension rack (200). Received between the rack (100) and the extension rack (200), connected to the output end of the transmission line (750), and connected to the plurality of cables.
(700-1 to 700-n), the rack in operation (100) and the extension rack (20)
0) and when connected correctly, the control signal of the output of the control signal generator (105) input through the transmission line (750),
When a wrong connection is made, the delay unit (110) that outputs a signal different from the control signal after delaying for a predetermined time, the main signal and the output of the delay unit (110) are input, and the plurality of cables ( 700-1 to 700-n) outputs the main signal when the rack (100) in operation and the extension rack (200) are correctly connected, and outputs a signal of a certain level when they are erroneously connected. And a gate unit (130) for controlling the extension (200), and the output of the gate unit (130) is connected to the plurality of cables (700-1 to 70).
A system malfunction prevention method at the time of connecting a plurality of cables, characterized in that it is transmitted to the rack (100) in operation via 0-n). 2. An extension rack (200) is connected to an operating rack (100) by a plurality of cables (700-1 to 700-n), and the plurality of cables (700-1 to 700-n) are used. In the system where signals are transmitted and received between the rack (100) in operation and the extension rack (200), the output of the control signal generator (108) provided in the rack (100) in operation is A transmission line (750) for transmitting and outputting a control signal by returning the control signal through the plurality of cables (700-1 to 700-n) in the operating rack (100) and the extension rack (200). Rack in operation (10
0) and the extension rack (200), connected to the output end of the transmission line (750), and connected to the plurality of cables.
(700-1 to 700-n), the rack in operation (100) and the extension rack (20)
0) and when connected correctly, the control signal of the output of the control signal generator (108) input through the transmission line (750),
Further, when the connection is incorrect, a signal different from the control signal is delayed for a predetermined time and output, and the output of the delay unit (210) and the plurality of cables (700) from the extension rack (200). -1 to 700-n), the main signal is input, and the plurality of cables (700-1 to 700-n) are used to connect the
0) and the extension rack (200) are correctly connected to each other, the main signal is output, and when they are erroneously connected, a gate unit (190) that outputs a signal of a constant level is connected to the rack (100) in operation. The system malfunction prevention method when multiple cables are connected.