JPH0581367A - Logic simulator - Google Patents

Abstract

PURPOSE:To detect an error of a logic circuit by giving a uniform unit delay to a logical gate, inputting a clock and executing a simulation for a period of a prescribed number of unit delays, and thereafter, checking each logical value. CONSTITUTION:A logical value of each logical gate after executing a simulation for a period of N unit delays is stored in a first memory means (6). Subsequently, a logical value of each logical gate after executing a simulation for a period of N+M unit delays is stored in a second memory means (8). Next, by comparing each contents stored in a first and a second memory means by a comparing means (9), equality or inequality of each logical value after executing the simulation for a periods of N and N+M unit delays is checked. As a result, if there is a logical gate in which two logical values after the N and N+M unit delay periods, its logical gate is considered to be oscillated, and the simulation is stopped (10).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator used to improve the design quality of various logic circuits, and more particularly to a detection method when the logic value of a logic gate to be simulated is not stable, and The present invention relates to a method of collecting information about test coverage of logic simulation.

The logic simulation collects the input and output data of each gate of the logic circuit at a predetermined time interval so that the static relationship between the input and output at each time and the dynamic relationship between the input and output on the time axis. Information on both of the changes is acquired, and the correctness of the design of the logic circuit is verified and the defective point is extracted.

The simulation by the logic simulator is performed by using a simulation model in which a logic circuit to be simulated is described logically equivalently. The simulation starts by giving initial conditions such as external inputs to the simulation model, and outputs the logical value of the input and output of each logic gate at a predetermined time interval from the logic simulator (display, print, etc.) under a predetermined simulation environment. It is done by letting.

When a design error is detected by the output information from the logic simulator at each time, the logic simulation is stopped at that time.

In recent years, logic simulators having different functions little by little depending on the purpose of use have been developed. For example, there is a logic simulator or the like that executes a logic simulation by uniformly giving a unit delay to each logic gate. Such a logic simulator continues the logic simulation even if there is a gate whose logic value is not stable during the execution of the simulation unless a design error is detected by the logic value at a time point (clock cycle time) after a certain period of time.

Such a logic simulator has no problem if the logic gate to be simulated can be represented by a unit delay, but if the logic gate simulates a logic circuit in which each logic gate cannot be represented by a unit delay. Even if the logic simulation is continued while the values are not stable, the operation will be quite different from the actual circuit, and the subsequent simulation results will be meaningless at all.

Due to the recent progress in semiconductor technology,
Circuits with tens of thousands to hundreds of thousands of gates have been integrated in chip ICs, and the circuits included therein have become complicated. Therefore, it becomes difficult to simulate the operation of all the elements of the logic circuit at any time,
For this reason, it has become unavoidable to limit the simulation items to perform the simulation.

At this time, it is necessary to know the range that can be grasped by the simulation, that is, the test coverage, but the number of logical simulation items is so large that it cannot be compared with the previous one, and the designer cannot manage all the simulation items. Accurate understanding of test coverage is becoming difficult.

[0009]

2. Description of the Related Art Regarding the detection of a logic gate whose logic value is not stable, conventionally, a logic simulator is specially developed and a case where a logic simulator which uniformly gives a unit delay to each logic gate is used for simulation. Or there was a case where it was purchased and used.

When a simulation is executed using the above logic simulator, the logic value oscillates and the logic value is not stable. In the past, this unstable logic value was used as the input data for the next simulation, and the simulation was continued. Therefore, even if the simulation result detects an error in the logic circuit, the cause should be oscillation. It is very difficult to pursue up to, and in the worst case, there is a problem that an error in the logic circuit cannot be detected despite the oscillation.

On the other hand, if a simulator is purchased or developed for each circuit to be simulated, the cost will increase and the effect of the simulation will decrease. Therefore, even a logic simulator having a special function is required to have a function as a versatile logic simulator.

Regarding the test coverage, conventionally, when performing a logic simulation, the designer listed up the necessary logic simulation items, and the logic simulation was performed according to the items. Information about the test coverage of the logic simulation was not collected, but the test coverage was estimated and judged from the items of the logic simulation. Therefore, there is a problem in that the design quality cannot be improved because the logic simulation is not actually performed even if the logic simulation is intended, or the items of the logic simulation are omitted.

[0013]

First, in a conventional logic simulator for performing simulation by uniformly giving a unit delay to each gate of a logic circuit, judgment is made only by the logic value of each gate at the time of executing each simulation. However, it was difficult to detect the oscillating logic circuit.

Second, in the conventional logic simulation, since the logic simulation is performed by estimating the test coverage without collecting the information about the test coverage of the logic simulation, the design quality is deteriorated due to omission of logic simulation items. It was one of the causes.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, and to provide a logic simulator capable of easily detecting an oscillating logic circuit and easily grasping test coverage. To do.

[0016]

A logic simulator according to the present invention gives a uniform unit delay to a logic gate to be simulated and executes a simulation to input a clock signal and a logic value of the logic gate caused by the input of the clock signal. Is a logic simulator for performing the update for a period of a predetermined number of unit delays, and a first memory means for storing the logic value of each logic gate after executing the simulation for the period of N (N is a natural number) unit delays. And a second memory means for storing the logic value of each logic gate after performing a simulation of N + M (M is a natural number) unit delay, and each logic gate stored by the first and second memory means. Means for comparing logical values and N unit delay period simulation And store the result in the first memory means, then execute the simulation for the period of N + M unit delays, store the result in the second memory means, and store in the first and second memory means. The comparison means compares the logic values of the respective logic gates, and as a result, if at least one logic gate detects a mismatch of the logic values, it comprises means for controlling to stop the execution of the logic simulator. Consists of

Further, the logic simulator according to the present invention is
The first means for executing a failure simulation of a logic circuit according to input data to detect a hypothetical failure of the logic circuit, a second means for detecting and accumulating all the hypothetical failures of the logic circuit, and a first means. A third means for accumulating the detected contingencies, a means for comparing the information accumulated by the second and the third means, all contingencies accumulated in the second means, and a logic circuit And a means for collecting information on the test coverage of the logic simulation based on the result of comparison by the comparing means with the assumed fault detected as a result of the logic simulation based on the input data by the one means.

[0018]

In the logic simulator having the above-described configuration, a uniform unit delay is given to the logic gate to be simulated, a clock is input, the simulation is executed for a predetermined number of unit delays, and then the logic value of each logic gate is calculated. Find out.

First, the logic value of each logic gate after the N unit delay period simulation is executed is stored in the first memory means. Next, the logic value of each logic gate after the simulation of N + M unit delay period is executed is stored in the second memory means.

By comparing the respective contents stored in the first and second memory means with the comparing means, it is checked for each logic gate whether or not the respective logic values coincide with each other after the N and N + M unit delay period simulation is executed. ..

As a result, if there are two logic gates having different logic values after the N and N + M unit delay periods,
The logic gate is considered to be oscillating, and further simulation is useless, so the simulation is stopped.

In the logic simulator having the above-mentioned structure, the first means executes the failure simulation of the logic circuit based on the input data to detect the hypothetical failure, and stores it in the third means. On the other hand, the second means detects all contingencies and stores them.

By comparing the actually obtained contingencies stored in the third means with the total contingencies stored in the second means, the range of the faults detected by the logic simulation is obtained. .. This range is the test coverage of the logic simulation.

[0024]

EXAMPLES Examples of the present invention will be described in detail. FIG. 1 is a flow chart showing the operation of an embodiment of a logic simulator according to the present invention, and FIG. 2 is a memory map of a memory 50 of this logic simulator.

The execution sequence of the logic simulation will be described with reference to the flowchart of FIG. (1) The simulation model is stored in the memory area (hereinafter indicated by #) 1. (2) Reserve # 2, # 3, and # 4 for storing the logic values of the simulation model corresponding to each logic gate.

(3) Set the environment for executing the simulation #
The simulation environment referred to here, which is stored in 0, is the waveform of the clock signal, the simulation execution time, the maximum number of simulation clocks, and the like. Here, the clock signals as shown in FIGS. 4A and 4B are input.
The simulation execution time is shown in unit delay units. (4) Prior to executing the simulation, a logical value is set in an external input, an internal memory or the like. These settings are made by writing a logical value to each memory location, such as the corresponding external input, internal memory in # 2.

(5) The simulation is executed with the logical value of # 2, the simulation model of # 1 and the clock signal of # 0. The logic value of each logic gate is updated up to N unit delays with the input of the clock signal. (6) If the logical value of each logical gate is updated by N unit delays, the logical value at that time is stored in # 3.

(7) The simulation is executed from the logical value of # 2, the simulation model of # 1, and the clock signal of # 0. The logic value of each logic gate is updated up to N + M unit delays with the input of the clock signal. (8) If the logical value of each logical gate is updated by N + M unit delays, the logical value at that time is stored in # 4.

(9) The logic value of each logic gate is stored in the memory #
Read from 3 and # 4, and compare the respective values. (10) As a result of the comparison, if there is at least one logic gate having a different logic value, it is determined that the logic gate is not stable, and the execution of the simulation is stopped.

(11) If the logic values of all the logic gates match, it is judged that the logic gates are stable, the logic value of # 3 is moved to # 2, and the simulation is executed again. (12) The above (5) to (11) are repeated up to the maximum number of clocks.

FIG. 3 shows an example of a logic circuit to be simulated. In FIG. 3, 51, 52, and 53 are inverters. Inverters 51, 52, 53
Are connected in cascade, and the input terminal of the inverter 51 and the output terminal of the inverter 53 are connected.

FIG. 4 shows the clock signal waveform stored in # 0. The dotted line indicates the time when the logic value of each logic gate is updated. There is one unit delay between adjacent time points.

FIG. 5 shows the inverters 51, 52 and 53 when a signal X having no change in value is input to the circuit of FIG. 3 and each inverter 51, 52, 53 is delayed by one unit delay. Each output signal waveform P, Q and R is shown.

The logic simulation of the circuit of FIG. 4 will be described with reference to the above-mentioned flowchart. (1) The simulation model stored in # 1 is the signals X, P, Q, R, and Y at each point of the logic circuit of FIG.
And P is an inversion of X, Q is an inversion of P, R is an inversion of Q, Y is an inversion of R, and is the same as X. Etc. are described.

(2) For each of the signal values X, P, Q, R, Y, at present, after N unit delay has elapsed, and N + M
Memory spaces for storing logical values after the unit delay has elapsed are defined as # 2, # 3 and # 4.

(3) The simulation environment is defined as # 0. Waveforms such as the signals (a) and (b) in FIG. 4 are used as clock signals, and 45 and 46 unit delays (N = 45, M =
Set 1).

(4) Describe the external input X = 1 in the X column of # 2. (5) The simulation is executed by the simulation model, the clock signal, and the external input X,
The logical values of P, Q, R and Y are updated up to 45 unit delay. (6) After updating each logical value up to 45 unit delay, each logical value at that time is stored in # 3.

(7) The simulation is executed with the simulation model, the clock signal, and the external input X, and the logical values of P, Q, and R are updated to 46 unit delays. (8) After updating each logical value up to 46 unit delay, each logical value at that time is stored in # 4.

(9) P stored in # 3 and # 4,
Each logical value of Q and R is read out, and for each logical value, the values after the elapse of 45 unit delay and 46 unit delay are compared. (10) When all are oscillating like the waveforms of the signals P, Q, and R shown in FIG.
There will be a difference in each logical value when the unit delay elapses.

In FIG. 5, A and B are 45
And 46 unit delay has elapsed, the logic values at points A and B of the signals P, Q, and R are 1, 1, 0 and 1, 0, 0, and gates having different logic values at both time points are used. Contains. Therefore, in this case, the simulation ends.

Although a simple logic circuit as shown in FIG. 3 has been described as an example, a logic circuit which oscillates and a logic value is not determined in a logic simulation of a logic circuit composed of an enormous number of logic gates is similarly used. It can be easily detected.

FIG. 6 is a flow chart showing the structure of the method for detecting the test coverage information of the logic simulator according to the present invention. The processing procedure of test coverage detection will be described with reference to FIG.

(1) The simulation input data is stored in the file 21. (2) Store the circuit information in the file 22. (3) Logic simulation 2 based on the simulation input data of the file 21 and the circuit information of the file 22
Execute 3. Confirming the result of logic simulation 24
I do. (4) Detection of hypothetical failure from circuit information in file 22 25
I do.

(5) All detected hypothetical faults are stored in the total fault file 26. (6) When the logic simulation 23 is completed, the failure simulation 27 is executed using the simulation input data of the file 21 and the circuit information of the file 22. (7) As a result of executing the failure simulation 27, a detectable failure point is extracted 28. (8) The failure detected by executing the failure simulation is accumulated in the failure detection file 29.

(9) When the failure simulation is completed with respect to all the simulation input data, the comparison 30 of each failure location accumulated in the all failure file 26 and the failure detection file 29 is performed. (10) Extraction of undetected failure by comparison 31
I do.

FIG. 7 shows a target logic circuit in the embodiment of the test coverage detection by the logic simulator of the present invention. The logic circuit of FIG. 7 has input terminals A, B and C and output terminals X. Input terminals A and B are OR gates 4
0, and the input terminal C is connected to the inverter 41.

The output terminal of the inverter 41 is connected to the D terminal of a flip-flop (referred to as FF) 42. FF4
The Q terminal of 2 and the output terminal of the OR gate 40 are connected to the AND gate 43. The output terminal of the AND gate 43 is F
It is connected to the D terminal of F44 and the Q terminal of FF44 is connected to the output terminal X of the logic circuit.

FIG. 8 shows input terminals A and B of the logic circuit of FIG.
And input signals from C and output signals Z and F of FF42
An example of the output signal Y of F44 and the signal at the output terminal X (same as Y) is shown. The logic simulation of FIG. 7 will be described below with reference to the above flowchart.

(1) The input data A, B and C shown in FIG. 8 are stored in the file 21. (2) The circuit information as described above regarding the logic circuit is stored in the file 22. (3) The logic simulation is executed based on the data stored in the files 21 and 22, and the result is confirmed.

(4) The fault simulator detects all assumed faults based on the circuit information in the file 22, and the file 26
To store. The total contingencies are a list of all possible faults at the inputs and outputs of all gates included in the logic circuit. Table 1 shows a full contingency table stored in file 26.

[Table 1]

In Table 1, the 0 stack fault and the 1 stack fault mean that signals are logic 0 and logic 1 respectively.
It means getting stuck in. That is, each input and output has two failure states, a 0 stack failure and a 1 stack failure.

(5) When the logic simulation is completed, the failure simulation is executed. (6) Tables 2, 3, and 4 are time points t shown in FIG.
The stack faults that can be detected at 2, t3, and t6 are listed and stored in the file 29.

[Table 2]

[Table 3]

[Table 4]

(7) The contents of the file 26 (Table 1) are compared with the contents of the file 29 (Tables 2, 3, and 4) to extract stack faults for which fault simulation data cannot be detected. As described above, the test coverage of the logic simulator can be quantitatively grasped by the ratio of undetected stack faults to all hypothetical faults.

[0054]

According to the present invention, even if a logic simulator that applies a unit delay to a logic gate is used to simulate a logic circuit in which each logic gate cannot be represented by a unit delay, it is possible to ensure that the logic circuit oscillates. Can be detected. Therefore, an error in the logic circuit due to the oscillation can be detected immediately. In addition, since it is not necessary to develop or purchase a simulator that executes only logical simulation, development costs can be reduced.

Further, since the test coverage is collected based on the data of the logic simulation actually performed in the collection of the test coverage information according to the present invention, even if the logic simulation is intended, it may be omitted. It is possible to reliably prevent mistakes such as having occurred. Moreover, since the test coverage is automatically determined, the labor and cost for the designer to manage the simulation items can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart showing an oscillator circuit detection method of a logic simulator according to the present invention.

FIG. 2 is a diagram showing a memory area.

FIG. 3 is a diagram (No. 1) showing an example of detection of an oscillation logic circuit.

FIG. 4 is a diagram (No. 2) showing an example of detection of an oscillation logic circuit.

FIG. 5 is a diagram (No. 3) showing an example of detection of an oscillation logic circuit.

FIG. 6 is a flowchart showing a test coverage information collecting method.

FIG. 7 is a diagram (No. 1) illustrating an example of collecting test coverage information.

FIG. 8 is a diagram (part 2) illustrating an example of collecting test coverage information.

[Explanation of symbols]

 1-12 Flowchart processing steps 21-31 Flowchart processing steps 40 OR gate 41 Inverter 42,44 Flip-flop 43 AND gate 50 Memory 51,52,53 Inverter

Claims (2)

[Claims] 1. A uniform unit delay is given to a logic gate to be simulated, and a simulation signal is executed to input a clock signal and update the logic value of the logic gate caused by the input of the clock signal only during a predetermined number of unit delays. And a first memory means for storing the logic value of each logic gate after performing a simulation for a period of N (N is a natural number) unit delay, and N + M (M is a natural number) unit delay. A second memory means for storing the logic value of each logic gate after performing the period simulation; a means for comparing the logic value of each logic gate stored by the first and second memory means; and an N unit delay. Run a period simulation of
The result is stored in the first memory means, then the simulation is executed for the period of N + M unit delays, the result is stored in the second memory means, and the logics stored in the first and second memory means are stored. And comparing the logic values of the gates by the comparing means, and as a result, if at least one logic gate detects a mismatch of the logic values, it controls to stop the execution of the logic simulator. And a logic simulator. 2. A first means for executing a failure simulation of a logic circuit according to input data to detect a hypothetical failure of the logic circuit, and a second means for detecting and accumulating all the hypothetical failures of the logic circuit. A third means of accumulating the contingencies detected by the first means, a means of comparing the information accumulated by the second and the third means, and all contingencies accumulated by the second means And a means for collecting information on a test coverage of the logic simulation by a result of comparing the assumed failure detected as a result of the logic simulation of the logic circuit based on the input data by the first means by the comparison means. A characteristic logic simulator.