JPH0581053B2 - - Google Patents
Info
- Publication number
- JPH0581053B2 JPH0581053B2 JP60282098A JP28209885A JPH0581053B2 JP H0581053 B2 JPH0581053 B2 JP H0581053B2 JP 60282098 A JP60282098 A JP 60282098A JP 28209885 A JP28209885 A JP 28209885A JP H0581053 B2 JPH0581053 B2 JP H0581053B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- metal layer
- gate insulating
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010408 film Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 23
- 239000004642 Polyimide Substances 0.000 claims description 18
- 229920001721 polyimide Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000002243 precursor Substances 0.000 claims description 15
- 238000010030 laminating Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims description 2
- -1 Si 3 N 4 Inorganic materials 0.000 claims 1
- 230000004913 activation Effects 0.000 claims 1
- 239000011810 insulating material Substances 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は略平坦な形状を有する薄膜トランジス
タ（以下、TFTと称す。）の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TFT) having a substantially flat shape.
（従来の技術） 従来のTFTの構造を第２図に示す。(Conventional technology) Figure 2 shows the structure of a conventional TFT.
第２図ａは平面図であり、第２図ｂは第２図ａ
のＡ−A′面の断面図である。第２図ａにおいて
は基板１の表示は省略されている。 Figure 2a is a plan view, and Figure 2b is a plan view of Figure 2a.
FIG. In FIG. 2a, the display of the substrate 1 is omitted.
第２図に示す従来のTFTは次の如くして作ら
れる。まず、ガラス基板又は石英基板等の透光性
絶縁物基板１上にニクロム（NiCr）、タングステ
ン（Ｗ）、モリブデン（Mo）、あるいはクロム
（Cr）等よりなる金属層を200Å〜1000Åの厚み
で真空蒸着法またはスパツタ法により被着形成
し、所定のパターンに加工してゲート電極２を形
成する。その上にゲート絶縁膜３となるシリコン
窒化膜（SiNx）をNH3とSiH4を主成分ガスとし
てグロー放電法により0.3μm〜0.6μmの膜厚で堆
積させる。 The conventional TFT shown in FIG. 2 is manufactured as follows. First, a metal layer made of nichrome (NiCr), tungsten (W), molybdenum (Mo), or chromium (Cr), etc. is deposited with a thickness of 200 Å to 1000 Å on a transparent insulating substrate 1 such as a glass substrate or a quartz substrate. The gate electrode 2 is formed by depositing by vacuum evaporation or sputtering and processing into a predetermined pattern. Thereon, a silicon nitride film (SiNx), which will become the gate insulating film 3, is deposited to a thickness of 0.3 μm to 0.6 μm by a glow discharge method using NH 3 and SiH 4 as main component gases.
更にその上に活性層４となるアモルフアスシリ
コン膜をSiH4ガスのグロー放電法により、0.1〜
0.3μm堆積したのち、TFTとなる部分以外は加
工し除去して島状にパターニングしてゲート絶縁
膜３と活性層４を形成する。 Furthermore, an amorphous silicon film, which will become the active layer 4, is deposited on top of the active layer 4 using a glow discharge method using SiH 4 gas.
After depositing 0.3 μm, the portions other than those that will become the TFT are processed and removed and patterned into an island shape to form the gate insulating film 3 and the active layer 4.
次に真空蒸着法により0.8〜10μmの厚みのアル
ミAl層を被着形成した後、所定のパターンに加
工してドレイン電極５及びソース電極６を形成す
る。このようにしてTFTが完成する。 Next, an aluminum layer with a thickness of 0.8 to 10 μm is deposited by vacuum evaporation, and then processed into a predetermined pattern to form a drain electrode 5 and a source electrode 6. In this way, the TFT is completed.
このTFTは、その後ソース電極６に接続する
ように透明電極７を形成し、TFTと透明電極を
二次元に配置すると液晶表示装置の駆動用の
TFT二次元アレイとして利用される。 This TFT is then formed with a transparent electrode 7 to be connected to the source electrode 6, and when the TFT and transparent electrode are arranged two-dimensionally, it can be used to drive a liquid crystal display device.
Used as a TFT two-dimensional array.
（発明が解決しようとする問題点）
しかしながら、上記構成のTFTはゲート絶縁
膜３及び活性層４の膜厚0.6〜0.9μmによる段差の
ためにドレイン電極５に第２図ｂに示すように断
線部Ｂ，B′が生じやすいという欠点があつた。
これを防ぐにはドレイン電極５の膜厚を厚くす
る、あるいは電極幅を広くする等の対策が考えら
れるが、このような対策を施すとTFT素子自体
の寸法が大きくなり、TFTを二次元で高密度に
配置したTFT二次元アレイを得ることが困難に
なるという欠点があつた。(Problems to be Solved by the Invention) However, in the TFT having the above structure, the drain electrode 5 is disconnected as shown in FIG. There was a drawback that portions B and B' were likely to occur.
To prevent this, measures such as increasing the film thickness of the drain electrode 5 or widening the electrode width can be considered, but such measures will increase the dimensions of the TFT element itself, making the TFT two-dimensional. The drawback was that it was difficult to obtain a two-dimensional TFT array arranged at high density.
本発明の目的は、上記欠点を除去し、高密度な
TFT二次元アレイに適し、略平坦で高速のスイ
ツチングが可能なTFTの製造方法を提供するこ
とにある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks and to provide a high-density
The object of the present invention is to provide a method for manufacturing a TFT that is suitable for a two-dimensional TFT array, is substantially flat, and allows high-speed switching.
（問題点を解決するための手段）
上述の問題点を解決するために本発明の薄膜ト
ランジスタは、透光性の絶縁物からなる基板と、
当該基板上に所定のパターンに設けられたゲート
電極と、当該ゲート電極上に当該ゲート電極と同
一パターンに設けらたゲート絶縁膜と、前記ゲー
ト電極及い前記ゲート絶縁膜の周囲を囲み且つそ
の厚みが前記ゲート絶縁膜の厚みと少なくとも略
同一となる如く、前記基板上に設けられた中間絶
縁層と、前記ゲート絶縁膜形成位置をはさんで互
いに対向する如く前記中間絶縁層上にそれぞれ所
定のパターンに設けられたソース電極及びドレイ
ン電極と、前記ゲート絶縁膜上を含み前記ソース
電極の端部からドレイン電極の端部にわたつて設
けられた活性層とを具備するようにしたものであ
る。(Means for Solving the Problems) In order to solve the above-mentioned problems, the thin film transistor of the present invention includes a substrate made of a light-transmitting insulator,
a gate electrode provided in a predetermined pattern on the substrate; a gate insulating film provided on the gate electrode in the same pattern as the gate electrode; an intermediate insulating layer provided on the substrate so that the thickness thereof is at least substantially the same as the thickness of the gate insulating film; A source electrode and a drain electrode provided in a pattern, and an active layer provided over the gate insulating film and extending from an end of the source electrode to an end of the drain electrode. .
上述の問題点を解決するために、本発明の薄
膜トランジスタの製造方法は絶縁物からなる基板
上に第１の金属層、当該第１の金属層の膜厚より
厚くした絶縁膜層、レジスト層を順次積層する工
程とフオトリソ・エツチングにより前記第１の金
属層、前記絶縁膜層を所定の同一形状にパターン
化して積層されたゲート電極及びゲート絶縁膜を
形成し且つ当該ゲート絶縁膜上にのみレジストを
残す工程と、前記基板上全面にわたつて前記ゲー
ト絶縁膜と少なくとも略同一の厚みを有するポリ
イミド前駆体を積層する工程と、前記ポリイミド
前駆体上全面にわたつて第２の金属層を積層する
工程と、リフトオフにより前記ゲート絶縁膜上に
存在する前記レジスト、前記ポリイミド前駆体、
及び前記第２金属層を除去する工程と、前記ポリ
イミド前駆体を焼成し中間絶縁層を形成する工程
と、前記中間絶縁層上の前記第２の金属層を所定
の形状にパターン化してソース電極及びドレイン
電極を形成する工程と、前記ゲート絶縁膜の上面
並びに前記ソース電極、前記ドレイン電極の互い
に対向する各端部の上面を含み前記ソース電極の
端部からドレイン電極の端部にわたつて活性層を
形成する工程とを具備するようにしたものであ
る。 In order to solve the above-mentioned problems, the method for manufacturing a thin film transistor of the present invention includes forming a first metal layer, an insulating film layer thicker than the first metal layer, and a resist layer on a substrate made of an insulator. The first metal layer and the insulating film layer are patterned into the same predetermined shape by sequential lamination process and photolithography etching to form a laminated gate electrode and gate insulating film, and a resist is applied only on the gate insulating film. a step of laminating a polyimide precursor having at least substantially the same thickness as the gate insulating film over the entire surface of the substrate; and laminating a second metal layer over the entire surface of the polyimide precursor. the resist and the polyimide precursor present on the gate insulating film by lift-off;
and removing the second metal layer, firing the polyimide precursor to form an intermediate insulating layer, and patterning the second metal layer on the intermediate insulating layer into a predetermined shape to form a source electrode. and a step of forming a drain electrode, and a step of forming an active layer from an end of the source electrode to an end of the drain electrode, including the upper surface of the gate insulating film and the upper surfaces of the mutually opposing ends of the source electrode and the drain electrode. The method includes a step of forming a layer.
また、本発明の薄膜トランジスタの他の製造方
法は、絶縁物からなる基板上に第１の金属層、当
該第１の金属層の膜厚より厚くした絶縁膜層、レ
ジスタ層を順次積層する工程とフオトリン・エツ
チングにより前記第１の金属層、前記絶縁膜層を
所定の同一形状にパターン化して積層されたゲー
ト電極及びゲート絶縁膜を形成し且つ当該ゲート
絶縁膜上にのみレジストを残す工程と、前記基板
上全面にわたつて前記ゲート絶縁膜と少なくとも
略同一の厚みを有するSiO、SiO2、Si3N4、ある
いはＡ2O3のうちいずれかからなる中間絶縁層
を積層する工程と、前記中間絶縁層全面にわたつ
て第２の金属層を積層する工程と、リフトオフに
より前記ゲート絶縁膜上に存在する前記レジス
ト、前記中間絶縁層、及び前記第２の金属層を除
去する工程と、前記中間絶縁層上の前記第２の金
属層を所定の形状にパターン化してソース電極及
びドレイン電極を形成する工程と、前記ゲート絶
縁膜の上面並びに前記ソース電極、前記ドレイン
電極の互いに対向する各端部の上面を含み前記ソ
ース電極の端部からドレイン電極の端部にわたつ
て活性層を形成する工程とを具備するようにした
ものである。 Another method for manufacturing a thin film transistor of the present invention includes the steps of sequentially laminating a first metal layer, an insulating film layer thicker than the first metal layer, and a resistor layer on a substrate made of an insulator. forming a stacked gate electrode and gate insulating film by patterning the first metal layer and the insulating film layer into the same predetermined shape by photo-etching, and leaving a resist only on the gate insulating film; a step of laminating an intermediate insulating layer made of any one of SiO, SiO 2 , Si 3 N 4 , or A 2 O 3 and having at least approximately the same thickness as the gate insulating film over the entire surface of the substrate; a step of laminating a second metal layer over the entire surface of the intermediate insulating layer; a step of removing the resist, the intermediate insulating layer, and the second metal layer existing on the gate insulating film by lift-off; patterning the second metal layer on the intermediate insulating layer into a predetermined shape to form a source electrode and a drain electrode; forming an active layer from an end of the source electrode to an end of the drain electrode, including the top surface of the source electrode.
（作用）
本発明によれば基板上に積層されたゲート電極
及びゲート絶縁膜の周囲を中間絶縁層で囲み、こ
の中間絶縁層の上にソース電極、ドレイン電極を
形成し、ゲート絶縁膜の上面並びに前記ソース電
極、前記ドレイン電極の互いに対向する各端部の
上面を含みソース電極の端部からドレイン電極の
端部にわたつて活性層を設けた構成となるので、
略平坦なTFTとなる。またこのTFTはゲート電
極とソース・ドレイン電極との重なる部分がない
セルフアラインのTFTであり、ゲート電極とソ
ース電極、ドレイン電極との間の容量が微少とな
るため高速のスイツチングが可能である。(Function) According to the present invention, a gate electrode and a gate insulating film stacked on a substrate are surrounded by an intermediate insulating layer, a source electrode and a drain electrode are formed on the intermediate insulating layer, and the upper surface of the gate insulating film is In addition, since the active layer is provided from the end of the source electrode to the end of the drain electrode, including the upper surface of each end of the source electrode and the drain electrode that are opposite to each other,
This results in a substantially flat TFT. Furthermore, this TFT is a self-aligned TFT in which the gate electrode and the source/drain electrodes do not overlap, and the capacitance between the gate electrode and the source/drain electrodes is minimal, allowing high-speed switching.
（実施例）
以下、本発明の一実施例を第１図ａ〜ｃの各工
程図に基づき説明する。(Example) Hereinafter, an example of the present invention will be described based on each process diagram of FIGS. 1a to 1c.
まず、ガラス基板または石英基板等の透光性絶
縁物基板１０上に、ニクロム（NiCr）、クロム
（Cr）、あるいはタングステン（Ｗ）よりなる第
１の金属層１１を200〜1000Åの厚みで真空蒸着
法またはスパツタ法により被着する。 First, a first metal layer 11 made of nichrome (NiCr), chromium (Cr), or tungsten (W) is deposited on a transparent insulating substrate 10 such as a glass substrate or a quartz substrate to a thickness of 200 to 1000 Å under vacuum. Deposited by vapor deposition or sputtering method.
次にシリコン窒化膜１２を0.3μm〜0.6μmの厚
みでグロー放電法により堆積する。そしてこの上
に1.0〜2.0μmの厚みのレジスト層１３を形成した
後、フオトリソ・エツチングにより前述の第１の
金属層及びシリコン窒化膜を順次同一パターンに
加工してゲート電極１１及びゲート絶縁膜１２を
形成する。（第１図ａ）
次にフオトリソ・エツチング後に残つたレジス
ト１３をそのままにして基板１０全面にわたつて
ポリイミド前駆体１４をスピナ法あるいはスプレ
ー法等により塗布する。このときのポリイミド前
駆体１４の厚みはゲート絶縁膜と同程度の厚み乃
至ゲート電極１１とゲート絶縁膜とを合わせた厚
みと同程度の厚みとする。続いて、このポリイミ
ド前駆体１４の上面全面にわたつて真空蒸着によ
り0.2〜0.5μmの厚みのAlあるいはNiCr−Auから
なる第２の金属層１５を形成する。（第１図ｂ）
次いで、アセトン等の有機溶剤を用いてレジス
トの除去すなわちリフトオフを行なうことにより
前述のゲート絶縁膜１２上にあるレジスト１３、
ポリイミド前駆体１４、第２の金属層１５を除去
する。 Next, a silicon nitride film 12 is deposited to a thickness of 0.3 μm to 0.6 μm by a glow discharge method. After forming a resist layer 13 with a thickness of 1.0 to 2.0 μm thereon, the first metal layer and silicon nitride film are sequentially processed into the same pattern by photolithography and etching to form the gate electrode 11 and the gate insulating film 12. form. (FIG. 1a) Next, a polyimide precursor 14 is applied over the entire surface of the substrate 10 by a spinner method or a spray method, leaving the resist 13 remaining after photolithography and etching as it is. The thickness of the polyimide precursor 14 at this time is approximately the same as the gate insulating film or the combined thickness of the gate electrode 11 and the gate insulating film. Subsequently, a second metal layer 15 made of Al or NiCr-Au and having a thickness of 0.2 to 0.5 μm is formed over the entire upper surface of the polyimide precursor 14 by vacuum evaporation. (FIG. 1b) Next, the resist 13 on the gate insulating film 12 is removed by removing or lifting off the resist using an organic solvent such as acetone.
The polyimide precursor 14 and second metal layer 15 are removed.
次に250〜300℃の不活性ガス雰囲気中で１〜２
時間程度熱処理することで、ポリイミド前駆体を
ポリイミド化して硬化させる。これにより中間絶
縁層１６が形成される。 Next, 1-2 times in an inert gas atmosphere at 250-300℃
The polyimide precursor is converted into polyimide and cured by heat treatment for about a period of time. As a result, an intermediate insulating layer 16 is formed.
更に、この中間絶縁層１６上の第２の金属層１
５をフオトリソ・エツチングにより所定のパター
ンに加工してソース電極１７及びドレイン電極１
８を形成する。そしてこれらの上にSiH4を主成
分ガスとして用いたグロー放電法により0.1〜
0.3μmの厚みのアモルフアスシリコン層を形成し
た後、フオトリソエツチングによりこのアモルフ
アスシリコン層がゲート絶縁膜１２上の全面及び
ソース電極１７、ドレイン電極１８の各端部上に
存在する如く所定のパターンに加工してアモルフ
アスシリコンの活性層１９を形成する。（第１図
ｃ）
以上の如くしてTFTが完成する。 Furthermore, the second metal layer 1 on this intermediate insulating layer 16
5 into a predetermined pattern by photolithography and etching to form a source electrode 17 and a drain electrode 1.
form 8. Then, on top of these , 0.1~
After forming an amorphous silicon layer with a thickness of 0.3 μm, a predetermined area is formed by photolithography so that this amorphous silicon layer is present on the entire surface of the gate insulating film 12 and on each end of the source electrode 17 and drain electrode 18. An active layer 19 of amorphous silicon is formed by processing into a pattern. (Figure 1c) The TFT is completed as described above.
このようにしてできあがつたTFTの構成を第
３図に示す。第３図ａは平面図であり基板１０は
省略されている。第３図ｂは第３図ａのＣ−C′断
面図であり、第３図ｃは第３図ａのＤ−D′断面
図である。第３図ａ，ｂに示す如くソース電極１
７と接続するように透明電極２０を設け、TFT
と透明電極２０を２次元に配置することにより液
晶表示装置の駆動等に用いられるTFT二次元ア
レイが構成される。また第３図ｂ，ｃから明らか
なように段差の小さい略平坦なTFTを構成する
ことが可能となる。なお、前述の実施例では中間
絶縁層１６としてポリイミドを用いた場合を示し
たが、これに代えて真空蒸着法、スパツタ法、あ
るいはグロー放電法等で形成されたシリコン酸化
膜（SiO、SiO2）シリコン窒化膜（Si3N4）、ある
いはアルミナ膜（Al2O3）を用いてもよい。 The structure of the TFT thus completed is shown in Figure 3. FIG. 3a is a plan view, and the substrate 10 is omitted. FIG. 3b is a cross-sectional view taken along the line C-C' in FIG. 3a, and FIG. 3c is a cross-sectional view taken along the line D-D' in FIG. 3a. Source electrode 1 as shown in Figure 3a and b
A transparent electrode 20 is provided to connect with the TFT
By two-dimensionally arranging the transparent electrodes 20 and 20, a two-dimensional TFT array used for driving a liquid crystal display device, etc. is constructed. Furthermore, as is clear from FIGS. 3b and 3c, it is possible to construct a substantially flat TFT with small steps. In the above-mentioned embodiment, polyimide was used as the intermediate insulating layer 16, but instead of this, a silicon oxide film (SiO, SiO 2 ) A silicon nitride film (Si 3 N 4 ) or an alumina film (Al 2 O 3 ) may be used.
（発明の効果）
以上のように、本発明によれば基板上に積層さ
れたゲート電極及びゲート絶縁膜の周囲を中間絶
縁層で囲み、この中間絶縁層の上にソース電極、
ドレイン電極を形成した後、ゲート絶縁膜の上面
並びにソース電極、ドレイン電極の互いに対向す
る各端部の上面を含みソース電極の端部からドレ
イン電極の端部にわたつて活性層を形成している
ため、段差の少ない略平坦なTFTを形成するこ
とが可能となり、ドレイン電極の断線等の間題が
生じることがなく、またソース電極、ドレイン電
極と活性層との間の良好な接続を行うことができ
る。(Effects of the Invention) As described above, according to the present invention, a gate electrode and a gate insulating film stacked on a substrate are surrounded by an intermediate insulating layer, and a source electrode and a gate insulating film are placed on the intermediate insulating layer.
After forming the drain electrode, an active layer is formed from the end of the source electrode to the end of the drain electrode, including the upper surface of the gate insulating film and the upper surfaces of the mutually opposing ends of the source electrode and the drain electrode. Therefore, it is possible to form a substantially flat TFT with few steps, and problems such as disconnection of the drain electrode do not occur, and good connections can be made between the source electrode, drain electrode, and active layer. I can do it.
さらに本発明によればゲート電極とソース・ド
レイン電極との重なる部分がないのでセルフアラ
インのTFTとなる。またゲート電極とソース電
極、ドレイン電極との間の容量も微少となるため
高速のスイツチングが可能なTFTを実現するこ
とができる。 Furthermore, according to the present invention, there is no overlap between the gate electrode and the source/drain electrodes, resulting in a self-aligned TFT. Furthermore, since the capacitance between the gate electrode, source electrode, and drain electrode becomes extremely small, a TFT capable of high-speed switching can be realized.
第１図ａ〜ｃは本発明の一実施例の工程図、第
２図ａは従来のTFTの平面図、第２図ｂは第２
図ａのＡ−A′断面図、第３図ａは本発明の一実
施例の構成を示す平面図、第３図ｂは第３図ａの
Ｃ−Ｃ断面図、第３図ｃは第３図ａのＤ−D′断
面図である。
１０…基板、１１…ゲート電極、１２…ゲート
絶縁膜、１４…ポリイミド前駆体、１５…第２の
金属層、１６…中間絶縁層（ポリイミド）、１７
…ソース電極、１８…ドレイン電極、１９…活性
層、２０…透明電極。
Figures 1 a to c are process diagrams of one embodiment of the present invention, Figure 2 a is a plan view of a conventional TFT, and Figure 2 b is a second
3a is a plan view showing the configuration of an embodiment of the present invention, FIG. 3b is a sectional view taken along C-C in FIG. 3a, and FIG. FIG. 3 is a sectional view taken along line D-D' in FIG. 3a. DESCRIPTION OF SYMBOLS 10... Substrate, 11... Gate electrode, 12... Gate insulating film, 14... Polyimide precursor, 15... Second metal layer, 16... Intermediate insulating layer (polyimide), 17
... Source electrode, 18... Drain electrode, 19... Active layer, 20... Transparent electrode.
Claims (1)
第１の金属層の膜厚より厚くした絶縁膜層、レジ
スト層を順次積層する工程と、 フオトリソ・エツチングにより前記第１の金属
層、前記絶縁膜層を所定の同一形状にパターン化
して積層されたゲート電極及びゲート絶縁膜を形
成し且つ当該ゲート絶縁膜上にのみレジストを残
す工程と、 前記基板上全面にわたつて前記ゲート絶縁膜と
少なくとも略同一の厚みを有するポリイミド前駆
体を積層する工程と、 前記ポリイミド前駆体上全面にわたつて第２の
金属層を積層する工程と、 リフトオフにより前記ゲート絶縁膜上に存在す
る前記レジスト、前記ポリイミド前駆体、及び前
記第２の金属層を除去する工程と、 前記ポリイミド前駆体を焼成し中間絶縁層を形
成する工程と、 前記中間絶縁層上の前記第２の金属層を所定の
形状にパターン化してソース電極及びドレイン電
極を形成する工程と、 前記ゲート絶縁膜の上面並びに前記ソース電
極、前記ドレイン電極の互いに対向する各端部の
上面を含み前記ソース電極の端部から前記ドレイ
ン電極の端部にわたつて活性化を形成する工程と
を具備することを特徴とする薄膜トランジスタの
製造方法。 ２ 前記ポリイミド前駆体の厚みが前記ゲート電
極の厚みと前記ゲート絶縁膜の厚みとを合わせた
厚みと略同一であることを特徴とする特許請求の
範囲第１項記載の薄膜トランジスタの製造方法。 ３ 前記活性層がアモルフアスシリコンからなる
ことを特徴とする特許請求の範囲第１項または第
２項記載の薄膜トランジスタの製造方法。 ４ 絶縁物からなる基板上に第１の金属層、当該
第１の金属層の膜厚より厚くした絶縁膜層、レジ
スト層を順次積層する工程と、 フオトリソ・エツチングにより前記第１の金属
層、前記絶縁膜層を所定の同一形状にパターン化
して積層されたゲート電極及びゲート絶縁膜を形
成し且つ当該ゲート絶縁膜上にのみレジストを残
す工程と、 前記基板上全面にわたつて前記ゲート絶縁膜と
少なくとも略同一の厚みを有する中間絶縁層を積
層する工程と、 前記中間絶縁層上全面にわたつて第２の金属層
を積層する工程と、 リフトオフにより前記ゲート絶縁膜上に存在す
る前記レジスト、前記中間絶縁層、及び前記第２
の金属層を除去する工程と、 前記中間絶縁層上の前記第２の金属層を所定の
形状にパターン化してソース電極及びドレイン電
極を形成する工程と、 前記ゲート絶縁膜の上面並びに前記ソース電
極、前記ドレイン電極の互いに対向する各端部の
上面を含み前記ソース電極の端部から前記ドレイ
ン電極の端部にわたつて活性層を形成する工程と
を具備することを特徴とする薄膜トランジスタの
製造方法。 ５ 前記中間絶縁層の厚みが前記ゲート電極の厚
みと前記ゲート絶縁膜の厚みとを合わせた厚みと
略同一であることを特徴とする特許請求の範囲第
４項記載の薄膜トランジスタの製造方法。 ６ 前記中間絶縁層がSiO、SiO2、Si3N4、ある
いはAl2O3のうちのいずれかからなり、前記活性
層がアモルフアスシリコンからなることを特徴と
する特許請求の範囲第４項または第５項記載の薄
膜トランジスタの製造方法。[Claims] 1. A step of sequentially laminating a first metal layer, an insulating film layer thicker than the first metal layer, and a resist layer on a substrate made of an insulating material, and the step of laminating the above-mentioned layer by photolithography etching. forming a stacked gate electrode and gate insulating film by patterning the first metal layer and the insulating film layer into the same predetermined shape, and leaving a resist only on the gate insulating film; and covering the entire surface of the substrate. a step of laminating a polyimide precursor having at least approximately the same thickness as the gate insulating film; a step of laminating a second metal layer over the entire surface of the polyimide precursor; and a step of depositing a second metal layer over the gate insulating film by lift-off. removing the resist, the polyimide precursor, and the second metal layer present on the intermediate insulating layer; firing the polyimide precursor to form an intermediate insulating layer; and removing the second metal layer on the intermediate insulating layer. forming a source electrode and a drain electrode by patterning a metal layer into a predetermined shape; A method for manufacturing a thin film transistor, comprising the step of forming activation from an end to an end of the drain electrode. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the thickness of the polyimide precursor is approximately the same as the combined thickness of the gate electrode and the gate insulating film. 3. The method for manufacturing a thin film transistor according to claim 1 or 2, wherein the active layer is made of amorphous silicon. 4. A step of sequentially laminating a first metal layer, an insulating film layer thicker than the first metal layer, and a resist layer on a substrate made of an insulator, and photolithography etching the first metal layer, patterning the insulating film layer into a predetermined uniform shape to form a stacked gate electrode and gate insulating film, and leaving a resist only on the gate insulating film; and forming the gate insulating film over the entire surface of the substrate. a step of laminating an intermediate insulating layer having at least approximately the same thickness as the intermediate insulating layer; a step of laminating a second metal layer over the entire surface of the intermediate insulating layer; and a step of depositing the resist present on the gate insulating film by lift-off. the intermediate insulating layer; and the second
a step of patterning the second metal layer on the intermediate insulating layer into a predetermined shape to form a source electrode and a drain electrode; and a step of removing the upper surface of the gate insulating film and the source electrode. , forming an active layer from an end of the source electrode to an end of the drain electrode, including the upper surface of each opposing end of the drain electrode. . 5. The method of manufacturing a thin film transistor according to claim 4, wherein the thickness of the intermediate insulating layer is approximately the same as the combined thickness of the gate electrode and the gate insulating film. 6. Claim 4, wherein the intermediate insulating layer is made of any one of SiO, SiO 2 , Si 3 N 4 , or Al 2 O 3 and the active layer is made of amorphous silicon. Alternatively, the method for manufacturing a thin film transistor according to item 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282098A JPS62141777A (en) | 1985-12-17 | 1985-12-17 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282098A JPS62141777A (en) | 1985-12-17 | 1985-12-17 | Thin film transistor and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62141777A JPS62141777A (en) | 1987-06-25 |
| JPH0581053B2 true JPH0581053B2 (en) | 1993-11-11 |
Family
ID=17648095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60282098A Granted JPS62141777A (en) | 1985-12-17 | 1985-12-17 | Thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62141777A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6490560A (en) * | 1987-10-01 | 1989-04-07 | Casio Computer Co Ltd | Thin-film transistor |
| JP5725614B2 (en) | 2011-08-04 | 2015-05-27 | 国立大学法人大阪大学 | Organic transistor and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132072A (en) * | 1979-03-31 | 1980-10-14 | Toshiba Corp | Mos semiconductor device |
| JPS5833782A (en) * | 1981-08-20 | 1983-02-28 | Fujitsu Ltd | Read error decreasing system |
| JPS59172773A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Thin film transistor element and manufacture thereof |
-
1985
- 1985-12-17 JP JP60282098A patent/JPS62141777A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132072A (en) * | 1979-03-31 | 1980-10-14 | Toshiba Corp | Mos semiconductor device |
| JPS5833782A (en) * | 1981-08-20 | 1983-02-28 | Fujitsu Ltd | Read error decreasing system |
| JPS59172773A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | Thin film transistor element and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62141777A (en) | 1987-06-25 |
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