JPH0580527A - Production of semiconductor device relating to interference exposure - Google Patents

Abstract

PURPOSE:To shift phases exactly by a half period each by first forming grid- shaped mask patterns over the entire length, then partially forming complementary patterns, thereby obtaining the mask patterns. CONSTITUTION:The 1st mask 2 which is the periodic patterns are formed by an interference exposing method on a substrate 1 which is a semiconductor and the substrate is partly coated with coating materials 3. The opened parts of the 1st mask 2 are selectively etched and periodic ruggedness is formed in the substrate regions not coated with the coating materials when the substrate 1 is etched. The coating materials are then removed and a dielectric layer is deposited on the surface. The parts between the patterns of the 1st mask 2 are filled and the 2nd mask 4 is formed by etching the entire surface. In succession, the substrate 1 on the side already formed with the ruggedness is coated with the coating materials 3 and the substrate 1 is etched by using the 2nd mask 4 as an etching mask. The corrugations completely inverted with the phases on both sides of the inversion boundaries are obtd. by removing the coating materials 3 and the 2nd mask 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a periodic uneven shape on a surface of a semiconductor substrate, and in particular, in combination with an interference exposure method, forms a periodic uneven pattern in which the phase is partially inverted. Involved in how to do.

Among semiconductor lasers, a DFB laser is provided with a grating waveguide for oscillating a specific wavelength. The diffraction grating (called corrugation) has a fine period of 0.2 μm, which cannot be formed by ordinary photolithography. Therefore, a resist pattern with a predetermined period is formed by the interference exposure method. With this as a mask, a compound semiconductor layer such as InP is formed by selective etching.

On the other hand, since the corrugation of the DFB laser has a structure in which the phase of the concavo-convex is shifted from the center of the corrugation, it is not possible to form the entire corrugation by a single interference exposure. is there.

[0004]

2. Description of the Related Art A conventional technique for forming a corrugation of this type using an interference exposure method is to intervene a dielectric in the optical path to shift the position of interference fringes due to the difference in refractive index. The inventions have been previously filed as Japanese Patent Application Nos. 1-23460 and 2-76421.

[0005]

In the corrugation of a DFB laser, the above-mentioned phase shift amount is often set to half the period of the diffraction grating, so that the diffraction grating that surely realizes such a phase shift amount. If the method for forming the optical semiconductor element is provided, it will greatly contribute to the development of the optical semiconductor element manufacturing technology and the optical semiconductor element utilization technology such as optical communication.

An object of the present invention is to provide a method for forming a corrugation having two regions whose phases are shifted by a half cycle by a single interference exposure, and yet another object is to provide an excellent wavelength characteristic. To provide a method of forming a semiconductor laser having

[0007]

In order to achieve the above object, in the formation of corrugations included in the method for manufacturing a semiconductor device of the present invention, the mask layer is formed over the entire length of the corrugations by a single interference exposure process. A grid pattern is formed on half of the corrugation, and half of the corrugation is formed by selective etching using this mask pattern.In other parts, this mask pattern is used to form a complementary mask pattern in a self-aligned manner. Selective etching is performed using the complementary mask pattern to form the other half of the corrugation. Incidentally, what is referred to as a mask pattern in this specification is a pattern of a selective etching mask, not a selective exposure pattern such as a photomask.

[0008]

According to the present invention, first, a mask pattern having a consistent periodicity over the entire length is formed, and in the region where the phase is inverted, the mask pattern of the complementary grating is self-aligned. Because it is formed
The periodicity of both mask patterns is continuous, and only the phase is completely deviated by a half cycle. Therefore, in the DFB laser in which the corrugation is formed by using these both patterns, single mode oscillation is realized, and a semiconductor laser having excellent wavelength characteristics can be obtained.

FIG. 1 is a principle process chart for explaining this situation. Hereinafter, the principle steps of the present invention will be described with reference to FIG. Substrate 1 which is a semiconductor such as InP
Then, the first mask 2 having a periodic pattern is formed by the interference exposure method. This state is shown in FIG. 9A, and the first mask is, for example, a positive resist. As shown in FIG. 6B, when a part of the substrate is covered with the covering material 3 and the substrate is etched, the open portion of the first mask is selectively etched and the substrate area not covered with the covering material is formed. Periodic irregularities are formed. For example, a negative resist can be used as the coating material.

By removing the coating material, depositing a dielectric layer by a method such as a CVD method, and then etching the entire surface by a processing method in which the dielectric layer is preferentially etched,
As shown in (c), the second mask 4 is formed by filling the space between the patterns of the first mask. Silicon dioxide or the like is suitable as the dielectric material. The first mask pattern is removed since it is no longer necessary.

Then, as shown in FIG. 1C, the substrate on the side where the irregularities have been already formed is covered with the coating material 3, and the second mask 4 is etched as shown in FIG. The substrate is etched as a mask. The coating can be the same as that used in the previous step, and can be any material that is etch resistant.

By removing the covering material and the second mask,
As shown in (f), a corrugation in which the phase is completely inverted across the inversion boundary is obtained. In the above process,
The timing of removing the first mask of the used portion and the selection of not forming the second mask of the unnecessary portion can be freely selected.

Further, according to the present invention, since the etching process of the substrate by the mask pattern formed first can be carried out at an appropriate time during the complementary mask pattern forming process, it is necessary to select the processing method and its execution conditions. There is freedom.

[0014]

The basic processing of the present invention is as described above, but when actually applied to the formation of a semiconductor laser, the processing method and the processing sequence are selected. Hereinafter, a plurality of embodiments of the present invention will be described.

FIG. 2 is a diagram schematically showing a process of a first embodiment corresponding to claim 2. The first embodiment will be described below with reference to FIG. In this embodiment, first, one substrate surface at the phase inversion boundary of the grating is etched to form a step having a height G. G is the depth of corrugation to be formed, and the material of the substrate 1 is InP, for example. Apply a positive photoresist to this substrate surface,
Stripe-shaped mask pattern with a period of 0.2 μm by interference exposure
Form 2. This state is shown in FIG. Although the edge of the mask pattern exactly coincides with the position of the step in the figure, this is not an essential requirement, and the position of the step may be slightly deviated.

Here, selective etching is performed on the entire lattice formation region by using a photoresist mask pattern.
This etching treatment is preferably anisotropic, and dry etching such as reactive ion etching (RIE) is suitable. The depth of the groove formed by this etching is also G. This state is shown in (b).

Next, the groove is formed in the silicon dioxide (SiO ₂ )
And the like with a dielectric material 14. In the actual process, after depositing the SiO ₂ layer on the entire surface of the substrate, the entire surface is etched by SiO 2.
By reducing the thickness of the _two layers, SiO ₂ is left in the trench. This becomes a second mask complementary to the first mask pattern. Filler materials that can be used here include resist materials having different characteristics in addition to dielectric materials such as silicon nitride.

Subsequently, the grid pattern 12 of the positive type resist formed first is completely removed, the region with the lower step is covered with a coating material 13 such as photoresist, and the substrate is re-RIEd.
Apply processing. In this process, selective etching is performed using the pattern of SiO ₂ as a mask. By setting the etching amount at that time to 2 G, grooves having the same depth as the formed lattice are provided.

By the above processing, a diffraction grating having a region in which the phase is completely inverted is formed. FIG. 3 is a diagram schematically showing the process of the second embodiment of the present invention. The second embodiment will be described below with reference to FIG.

A SiO ₂ layer having a thickness of 0.5 to 0.8 μm is deposited and formed on the surface of the InP substrate 1 by a method such as CVD, and the SiO ₂ layer having a period of 0.2 μm is formed by photolithography using interference exposure. The grid pattern is 22. This state is shown in FIG.

One side of the phase inversion boundary is covered with a resist 13, and the substrate is subjected to selective etching using the SiO ₂ lattice pattern 22 as a mask to form a groove having a depth G (see the same figure).
(b)). Next, when the resist is removed and an InGaAs layer is deposited and grown by MOVPE while leaving the SiO ₂ lattice pattern, the growth does not grow on the SiO ₂ but only on the InP substrate surface (see FIG. )). The crystal growth may be epitaxial growth or may be growth of a polycrystalline layer.

When the thickness of the InGaAs layer becomes 1/2 or more of G, epitaxial growth is terminated and SiO ₂
Remove the grid pattern. The second lattice pattern 15 formed of the InGaAs layer is left on the substrate (see the same figure).
(d)). The value of 1/2 is determined because the selection ratio in the subsequent etching process is 2, and the selection ratio is n.
If it is twice, it means 1 / n or more.

As shown in FIG. 2E, the region which has been selectively etched is covered with a photoresist 13 or the like, and an RIE process using a methane or ethane gas is performed. As described above, since InP is etched at a speed twice as fast as that of InGaAs, the InGaAs lattice pattern 15 remains until the groove having the depth G is formed in the InP substrate.
Only selective etching is carried out ((f) of the same figure).

The photoresist 13 is removed and H ₂ SO ₄ + H
_When treated with a ₂ O ₂ -based etching solution, InGaAs is removed and a corrugation in which the phase is partially inverted is completed as shown in FIG.

FIG. 4 is a diagram schematically showing the steps of the third embodiment of the present invention. The third embodiment will be described below with reference to FIG. In this embodiment, first, AlGaAs or AlInA is formed on one side of the phase inversion boundary of the InP substrate.
A compound semiconductor layer 16 having Al as a constituent element such as s is formed. This can be formed by etching away the unnecessary side after the entire surface growth, but can also be formed by selective growth. In this embodiment, it is AlGaAs.

Next, a grid pattern 12 of positive photoresist is formed on the entire surface of the corrugated region by the same method as that of the above-described embodiment (FIG. 9 (a)). The surface of the substrate on which the Al-based semiconductor layer is provided is covered with a resist 13 or the like, and selective etching is performed by RIE to form a groove having a depth G in the substrate.
(Figure (b)).

When the resist 13 is removed and the substrate is subjected to oxygen plasma treatment, the Al in the AlGaAs layer is rapidly oxidized, and an oxide layer 17 mainly composed of alumina is formed (FIG. 2 (b)). ). In this process, InP on the substrate is hardly oxidized. When the photoresist pattern is removed, a lattice pattern of the oxide layer 17, which is the second mask pattern, is obtained as shown in FIG. As will be readily appreciated, this pattern is complementary to the pattern 12 of the original photoresist.

The region where the grid-like grooves are already formed is covered with a covering material such as a resist 13 (FIG. 7E), and selective etching is performed using the oxide layer 17 as a mask. Grooves are also formed in a grid pattern in the region ((f) in the figure). Needless to say, the depth of these grooves is G.

By removing the resist, the oxide layer and the Al-based semiconductor layer, a corrugation including a phase inversion region is formed on the substrate as shown in FIG.

[0030]

As is apparent from the above description, according to the present invention, a grid-shaped mask pattern is first formed over the entire length, and a pattern complementary to it is partially formed as a mask pattern. The phase inversion is performed in a self-aligned manner, and the phase shift is exactly half a period.

As a result, by applying the method of the present invention to the manufacture of a DFB laser, it becomes possible to form a semiconductor laser having excellent wavelength characteristics.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle process of the present invention.

FIG. 2 is a schematic diagram showing a process of the first embodiment.

FIG. 3 is a schematic diagram showing a process of a second embodiment.

FIG. 4 is a schematic diagram showing a process of a third embodiment.

[Explanation of symbols]

1 Substrate (InP) 2 First Mask 3 Covering Material 4 Second Mask 12 Photoresist 13 Resist 14 Dielectric 15 InGaAs 16 AlGaAs 17 Oxide Layer 22 SiO ₂

Claims (8)

[Claims] 1. A first selective etching mask pattern made of a first material and having a periodic structure on a semiconductor substrate (1).
Forming step (2) by an interference exposure method, performing a selective etching on a part of the substrate using the mask pattern, and complementing the pattern on another part of the substrate using the mask pattern A second selective etching mask pattern (4) made of a second material, and after removing the first mask pattern, the second mask pattern is used to remove another substrate of the substrate. A method of manufacturing a semiconductor device, comprising a step of selectively etching a part of the semiconductor device. 2. A step having the same height as a depth G of the unevenness when forming a shape having unevenness of a constant cycle on the surface of the semiconductor substrate and partially inverting the unevenness while continuing the cycle. On the surface of the substrate (1), a resist layer serving as a first mask is deposited on the substrate surface, and a resist pattern having a constant period is formed on both sides of the step by an interference exposure method. A process of selectively etching the substrate by the depth G using the periodic resist pattern as a mask, depositing a mask material layer on the surface of the substrate, and uniformly reducing the thickness of the mask material layer. A second mask pattern (14) is formed by filling the concave portion of the substrate which has been subjected to the selective etching with the mask material layer, and the lower side region of the substrate is covered with the step as a boundary. Layer (1
A method of manufacturing a semiconductor device, which is characterized in that the substrate is covered with 3) and the substrate is selectively etched to a depth of 2 G using the second mask pattern as a mask. 3. A silicon dioxide layer is formed on the surface of the substrate (1) when forming a shape having irregularities of a certain period on the surface of a semiconductor substrate and partially inverting the irregularity while continuing the period. After deposition, a first mask pattern (22) of a silicon dioxide layer having the same period as the concave and convex period is formed by a photolithography process using an interference exposure method, and the first mask pattern (22) of the concave and convex on one side is formed. A coating layer (1
After coating with 3), the first mask pattern is used as a mask to selectively etch the surface of the substrate on the other side to a depth of G to remove the coating material layer, and then to expose the substrate to the exposed surface of the substrate. Means that after selectively epitaxially growing semiconductor layers having different etching characteristics, the first mask pattern is removed to form a second mask pattern (15) composed of semiconductor layers having different etching characteristics, After covering the surface of the substrate on one side of the concave-convex inversion boundary, which has been subjected to the selective etching of the depth G, with a coating material layer (13), the second mask pattern is used as a mask for the other side of the substrate. A method of manufacturing a semiconductor device, characterized in that selective etching with a depth G is performed on the side of the semiconductor device. 4. Reversing the irregularities on the surface of the substrate (1) when forming a shape having irregularities of a certain period on the surface of a semiconductor substrate and partially inverting the irregularity while continuing the period. After depositing and forming a compound semiconductor layer (16) containing aluminum as one of the constituent elements on one side of the boundary, a resist layer is applied to the substrate surface, and the resist layer is formed by the interference exposure method in the same period as the uneven period. To form a first mask pattern (12) having a coating layer (13) on one side of the inversion boundary and on which the compound semiconductor layer is deposited and formed. After selectively etching the surface of the substrate to a depth of G using the first mask pattern as a mask, the coating material layer is removed and the surface of the substrate is treated with oxygen plasma to expose the exposed surface of the compound semiconductor layer. A second mass consisting of an oxide layer by oxidizing Pattern (17) is formed, the first mask pattern is removed, and a portion of the substrate surface where the compound semiconductor layer is not formed is covered with a coating material layer (1
After coating with 3), the compound semiconductor layer and the substrate are selectively etched by using the second mask pattern as a mask, and the substrate is subjected to selective etching with a depth G. Method of manufacturing semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the resist layer on which the first mask pattern is formed is a novolac-based positive resist, and the first resist pattern is partially formed. A method for manufacturing a semiconductor device, wherein the coating material to be coated is a negative cyclized rubber-based resist. 6. The anisotropic dry etching is performed for the selective etching of the mask layer or the selective etching of the substrate at the time of forming the mask pattern included in the method for manufacturing a semiconductor device according to claim 2. And a method for manufacturing a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the anisotropic dry etching is reactive ion etching. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the manufactured semiconductor device is a DFB laser.