JPH0579664U - Pulse output circuit in microcomputer - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a pulse output circuit in a microcomputer capable of easily obtaining 6 + 2 pulse outputs from the pulse output function grouped into 4 + 4 lines. [Structure] For the two wires (11b) of one group, the signal source for controlling the timing of pulse output should be the same as the own group (10 timer 2 overflow) or the other group (8 timer 1 overflow). A register (12) for selecting whether to perform or not is provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 This invention relates to a pulse output circuit in a microcomputer.

[0002]

[Prior Art]

 FIG. 2 is a circuit diagram showing a conventional pulse output circuit in a microcomputer. In the figure, 1 is a CPU, 2 is an address bus, 3 is a data bus, 4 is a first latch, and 5 is a second latch. , 6 is an output buffer to the port output, 7 is a timer 1 and 8 is a timer 1 overflow signal, 9 is a timer 2 and 10 is a timer 2 overflow signal, 11 is data from the first latch to the second latch This is a gate that turns on when transferring.

Next, the operation will be described. In FIG. 2, first, data of HIGH "1" or LOW "0" output from the CPU 1 to the first latch 4 is written through the address bus 2 and the data bus 3. Set the HIGH / LOW output pulse width to timer 1 of 7 in advance and start counting. Every time the timer 1 overflows, an overflow signal 8 is output, and this signal transfers data from the first latch 4 to the second latch 5 and determines the port output. The data written in the first latch just before the overflow of timer 1 is output as the polarity of the port output at the timing of the overflow of timer 1, so the real-time port (hereinafter referred to as RTP) output function. It is effective for pulse motor drive control.

In the two-phase stepping motor, motor control is performed by using 4-bit RTP pulse output. Brushless motors require 6-bit RTP pulses because they are controlled by three-phase (U, V, W phase) pulses that are 120 ° out of phase. However, in the conventional RTP output function, 4 bits are set as one group, and the output timing control is performed by one timer for each group. In FIG. 2, when the six bits from bit 0 to bit 5 are used to control the brushless motor, timer 1 is 7 for bits 0 to 3, timer 2 is 9 for bits 4 and 5, And two separate timers control the output. The CPU operates so that these two timers operate in exactly the same way.

[0005]

[Problems to be solved by the device]

 Since the conventional pulse output circuit in the microcomputer is configured as described above, one timer is assigned with 4 bits as one group and the pulse is output in synchronization with its overflow. In case of needing, the problem is that two timers must be controlled in exactly the same way, for example, operating two groups (8 bits) of RTP and using 6 bits of them. There was a point.

The present invention has been made to solve the above-mentioned problems, and it is possible to easily select 4 bits or 6 bits for RTP output by register setting, and when 6 bits are selected. Aims to control selected 6 bits as one group with one timer.

[0007]

[Means for Solving the Problems]

 The pulse output circuit in the microcomputer according to the present invention has a control timer in which the timer 1 controls 4 bits and the timer 2 controls 4 bits, and the timer 1 controls 6 bits, depending on the contents of the newly set bit number selection register. -It is equipped with a means to automatically switch between the case where the timer 2 controls 2 bits.

[0008]

[Action]

 In the pulse output circuit in the microcomputer according to the present invention, for bits 4 and 5, the input source of the overflow signal for operating the data transfer from the first latch to the second latch is set to the contents of the new bit number selection register. Thus, by switching to timer 2 for 4-bit / 4-bit and timer 1 for 6-bit / 2-bit, one timer 1 can operate 6-bit RTP output.

[0009]

【Example】

 Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a pulse output circuit in a microcomputer according to a first embodiment of the present invention. In the figure, 12 is an RTP bit number selection register, 13 is a control timer switching circuit, and others are the same as those of the conventional FIG. Indicates the same or a corresponding portion. Next, the operation will be described. A timer overflow signal is applied to gate 11 to control the transfer of the RTP output data from the first latch 4 to the second latch 5. In the lower 4 bits, the overflow signal 8 of the timer 1 is inputted to the gate 11a as a control signal as in the conventional case, and the overflow signal of the timer 2 is put in the gate 11c of the upper 2 bits. The RTP bit number selection register 12 selects either the overflow of timer 1 or the overflow of timer 2 for the control signal of the gate 11b for the two bits 4 and 5 between them. When the register 12 is "0", the overflow signal of the timer 2 is selected by the switching circuit of 13 and enters the gate 11b, and the bits 4 and 5 become the group of the higher 2 bits, and the 4-bit / 4-bit RTP is selected. Be done. When the register 12 is "1", the overflow signal of the timer 1 is selected by the switching circuit of 13 and goes to the gate 11b. Bits 4 and 5 enter the lower 4 bits group, and 6 bits / 2 bits. RTP is selected. In this case, only timer 1 needs to be operated to perform 6-bit control, and timer 2 can be used for other purposes when the remaining 2-bit RTP is unnecessary. Also, by setting the selection register as to whether or not to output the output of the RTP to the port for the remaining 2 bits, the port of the remaining 2 bits can be effectively used as a normal input / output port.

Example 2. An operation in which the control timer switching circuit 13 of the first embodiment is replaced with an AND-OR (FIG. 313d) can also be expected to have the same operation as that of the first embodiment.

Example 3. In the first embodiment, the grouping of 4-bit and 4-bit groups and the grouping of 6-bit and 2-bit groups has been described, but the present invention is not limited to this, and groups of i-bit and j-bit and (i + k) -bit ( Similar effects can be expected in various combinations such as a group of (j−k) bits (i, j, and k are arbitrary).

[0012]

[Effect of the device]

 As described above, according to the present invention, two timers have conventionally obtained 6-bit RTP output, but by providing a new RTP bit number selection register, one timer can obtain the same function. As a result, the burden of CPU timer operation is halved, and the remaining timers can be used for other purposes. The remaining 2-bit port can also be used for other purposes as a normal input / output port.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a pulse output circuit in a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional pulse output circuit in a microcomputer.

FIG. 3 is a detailed diagram of a control timer switching circuit 13.

[Explanation of symbols]

1 CPU 2 Address Bus 3 Data Bus 4 RTP Data Register First Latch 5 Second Latch 6 Output Buffer to Port 7 Timer 1 8 Timer 1 Overflow Signal 9 Timer 2 10 Timer 2 Overflow Signal 11 First Latch Gate that turns on at the timing of data transfer from the memory to the second latch 12 RTP bit number selection register 13 Control timer switching circuit

Claims (1)

[Scope of utility model registration request] 1. A central processing unit (hereinafter referred to as CPU) that executes various calculations and controls read / write to various memories such as ROM and RAM and various registers, and data between each memory, registers and CPU. In a microcomputer having an address bus and a data bus for transfer,
A plurality of timers for counting by an operation from the CPU, an n-bit first data register in which polarity data is set for each bit by the CPU, and an n for receiving and holding data from the first data register. ON / OFF by a bit second data register, n output buffers that output a pulse to a port according to the polarity of the data of the second register, and an overflow signal generated by the count of the arbitrary timer. A pulse generation circuit comprising n gates for transferring data from the first data register controlled to the second data register and a bit number selection register for determining the number of bits whose polarity is changed at the same time, Bits that change at the same time are grouped into i and j bits, and separate timers (timer I and timer I and Overflow signal timer J),
When the gate connecting the first data register and the second data register is operated to control the output timing of an arbitrary pulse, k in group j is controlled by either timer I or timer J It is possible to select which of the timers is to be selected by the bit number selection register, thereby grouping i and j and (i + k) and (j-
k) A pulse output circuit in a microcomputer, which obtains a plurality of pulse outputs grouped into pieces.