JPH0579646U - Microprocessor - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain a microprocessor that can trace instruction addresses in the same operation without slowing down the execution speed during normal operation. [Structure] A trace memory that inputs the value of the instruction counter at the final stage, a counter that indicates the address of the trace memory, a data input register that selects and inputs the trace memory and the output of the counter, and a data input register Configured from a register file to input the value of. [Effect] Instruction address values from the current time to the past are stored in the trace memory during normal operation, and those values can be read into the register file by input / output instructions during debugging, so instructions can be used without changing the operation during normal operation. The address trace can be known, which has the effect of facilitating debugging.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a debug function of a pipeline type microprocessor, and particularly to an instruction address trace function therein.

[0002]

[Prior Art]

 When debugging a system using a microprocessor, it is effective to trace the contents of an instruction counter (hereinafter abbreviated as IC), that is, the instruction address to be executed next. However, in a pipeline-type microprocessor, instruction execution is completed at the final stage, so that the instruction address to be executed next is stored in the final stage IC, so that when the instruction code is fetched into the microprocessor. Even if the instruction address is observed at, this does not match the trace of the actually executed instruction address. Therefore, the conventional microprocessor has a trace interrupt function to trace the instruction address. FIG. 3 is a block diagram showing a portion related to execution of a trace interrupt in a conventional microprocessor. In the figure, 1 is a microprocessor, 2 is a main memory, 3 and 4 are a microprocessor 1 and a main memory 2, respectively. Address bus and data bus, 5 is a first-stage IC that holds the address of the instruction to be fetched next, 6 is a plurality of intermediate-stage ICs that receive the value of the first-stage IC 5, and 7 is the value of the intermediate-stage IC 6. Is a final stage IC, 8 is a data input register (hereinafter referred to as DIR) which receives the value of the data bus 4, 9 is a register file which receives the value of DIR8, 10 is the final stage IC7 or register file Data output register (hereinafter referred to as DOR) that receives the value of file 9 as an input and outputs data bus 4 as an output, 11 is an address generator, and 12 is an adder A selector for selecting the memory generating unit 11 and the first-stage IC 5 and outputting it to the address bus 3, and a control unit 13 for controlling the data transfer between the blocks 5 to 12 described above. It is built in the processor 1.

Next, the operation of this conventional example will be described. During normal operation, the first-stage IC 5 outputs the address of the instruction to be fetched next from the address bus 3, and the instruction is fetched from the main memory 2 to the microprocessor 1. As the instruction is processed in each stage of the pipeline, the instruction address corresponding to the instruction is also transferred from the first-stage IC5 through the intermediate-stage IC6, and is input to the last-stage IC7 when the instruction is actually executed. It Each time the instruction execution is completed, the contents of the final stage IC 7 are updated to the next instruction address. Addresses other than these instructions are generated by the address generator 11, selected by the selector 12, and output. On the other hand, at the time of debugging, the control circuit 13 is set so that an interrupt occurs for each instruction. In this case, when one instruction is completed at the final stage, the control circuit 13 stores the value of the final stage IC 7 at a specific address of the main memory 2 via the DOR 10 and the data bus 4 as an interrupt process. After the interrupt processing, the microprocessor 1 executes the next instruction from the first processing of the pipeline by programming so as to branch to the next instruction address indicated by the final stage IC7. As a result, the executed instruction address is stored in the main memory 2 and the trace can be known.

[0004]

[Problems to be solved by the device]

 As described above, in the conventional microprocessor, in order to trace and know the instruction address, an interrupt is generated for each instruction, the contents of the final stage IC are stored in the memory by the interrupt processing, and the processing of the next instruction is started. Since it starts again from the beginning, it will be significantly slower than the execution speed during normal operation. Especially in the case of real-time processing, the same amount of processing as in normal operation cannot be performed, which is inconvenient. In addition, the internal operation of the microprocessor differs between during debugging and during normal operation, which is also inconvenient when debugging the microprocessor itself.

The present invention has been made to solve the above problems, and an object thereof is to obtain a microprocessor capable of tracing an instruction address in the same operation without reducing the execution speed during normal operation.

[0006]

[Means for Solving the Problems]

 The microprocessor of the present invention comprises a counter indicating the address of the trace memory and the trace memory which receives the value of the final stage IC, and a selector which selects the output of the trace memory and the counter and outputs it to the data input register. And a register file for inputting the value of the data input register.

Further, a microprocessor according to another embodiment of the present invention selects a trace memory which receives the value of the final stage IC, a counter which indicates the address of the trace memory, and an output of the trace memory. A selector that outputs the data to the data input register and a register file that inputs the value of the data input register are provided.

[0008]

[Action]

 During normal operation, the microprocessor of the present invention stores the instruction address in the final stage IC in the trace memory at the address indicated by the counter at every instruction execution, and at the time of debugging, first, the counter value is input / output instruction. To the register file via the data input register, and with this input / output instruction, the instruction address can be traced back from the address indicated by the counter, and the register address can be registered from the trace memory via the data input register. Since it can be read to a file, it is possible to know past instruction addresses.

In addition, the microprocessor according to another embodiment of the present invention stores the instruction address in the final stage IC in the trace memory at the address indicated by the counter every time the instruction is executed at the time of normal operation, and at the time of debugging. , First, count down the counter value with an input / output instruction, and read the instruction address at the address indicated by the counter from the trace memory to the register file via the data input register. Know the past instruction address. You can

[0010]

【Example】

 Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numerals 1 to 13 are the same as or equivalent to the above-mentioned conventional example, 14 is a counter, and 15 is a trace memory in which the value of the final stage IC 7 is input as data. , 16 is a selector for selecting the output of the data bus 4, the counter 14 and the trace memory 5 and outputting the same to the DIR 8, and 17 is the selector for selecting the output of the counter 14 and the address generating unit 11 to the trace memory 15. It is a selector that outputs the address.

Next, the operation of the embodiment will be described. In the normal operation, the instruction address is transferred from the first stage IC5 to the last stage IC7 as in the conventional example. When the instruction execution at the final stage is completed, the value of the final stage IC 7 is stored in the trace memory 15 at the address indicated by the counter 14, and the counter 14 is incremented by 1. Instead, the next instruction address enters the final stage IC7. When the trace memory 15 becomes full by repeating this operation, the value of the counter 14 returns to 0 and the previously stored address is overwritten. On the other hand, at the time of debugging, the control unit 13 is set so as to prohibit the storage in the trace memory 15, and the contents of the trace memory 15 are read out to the register file 9 by the program using the input / output instruction. Get to know the trace. Specifically, first, an input / output instruction for the counter 14 is executed, and the value of the counter 14 (hereinafter, this value is referred to as A) is input to the register file 9 via the selector 16 and the DIR 8. Next, when (A-1) is stored in the register file 9 by the subtraction instruction, and the input / output instruction to / from the trace memory 15 is executed using this value, the address generator 11 generates it according to this input / output instruction. The value (A-1) is selected by the selector 17 and input to the trace memory 15, and the instruction address at the address (A-1), that is, the last executed instruction address is stored in the register file 9 via the selector 16 and the DIR 8. Read out. Further, by repeating the steps from (A-2) to read the address from the trace memory 15 to the register file 9 in the same procedure, it is possible to know the trace result only for the amount stored in the trace memory 15. You can

Example 2. FIG. 2 is a block diagram showing another embodiment, in which 1 to 13 are the same or corresponding parts as those in the conventional example, and 14 to 16 are the same parts as in the first embodiment.

In the second embodiment shown in FIG. 2, first, during normal operation, the same operation as in the first embodiment is performed. In order to know the past instruction address stored in the trace memory 15, the counter 14 is counted down by 1 by executing a specific input / output instruction, and at the same time, the address of the value is read from the trace memory 15. The instruction address, that is, the last executed instruction address is read out to the register file 9 via the selector 16 and the DIR 8. If this input / output instruction execution is further repeated, past address values are sequentially read from the trace memory 15 to the register file 9.

[0014]

[Effect of the device]

 As described above, the microprocessor of the present invention is configured to store the instruction address executed during normal operation in the trace memory and read the counter value and the contents of any address in the trace memory during debugging. The effect is that the instruction address trace during normal operation can be obtained without slowing down.

Further, according to another embodiment of the present invention, the contents of the trace memory can be sequentially read only backward, but the same effect can be obtained by one input / output instruction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of Codes] 1 Microprocessor 2 Main Memory 3 Address Bus 4 Data Bus 5 First Stage IC 6 Intermediate Stage IC 7 Last Stage IC 8 Data Input Register 9 Register File 10 Data Output Register 11 Address Generation Unit 12 Selector 13 Control Part 14 Counter 15 Trace memory 16 Selector 17 Selector

Claims (1)

[Scope of utility model registration request] 1. In a pipeline type microprocessor, an initial stage instruction counter for calculating an address of a next instruction, an intermediate stage instruction counter for transferring each instruction address of the pipeline, and an intermediate stage register are used. A final stage instruction counter that inputs the transferred instruction address, a trace memory that inputs the output of the final stage instruction counter, and a counter that indicates the address of the trace memory,
It has a data input register, a selector for selecting the output of the trace memory, the output of the counter and the data input from the outside and outputting to the data input register, and a register file having the output of the data input register as the input. A microprocessor characterized in that.