JPH0578943B2 - - Google Patents
Info
- Publication number
- JPH0578943B2 JPH0578943B2 JP60288728A JP28872885A JPH0578943B2 JP H0578943 B2 JPH0578943 B2 JP H0578943B2 JP 60288728 A JP60288728 A JP 60288728A JP 28872885 A JP28872885 A JP 28872885A JP H0578943 B2 JPH0578943 B2 JP H0578943B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- series
- series resistance
- resistance
- ref
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Description
【発明の詳細な説明】
（技術分野）
本発明は半導体基板上に直列抵抗型分圧回路を
使用するデイジタルアナログ変換部を有する集積
回路に関し、とくに逐次比較型アナログ・デイジ
タル変換機能を有する集積回路に関するものであ
る。Detailed Description of the Invention (Technical Field) The present invention relates to an integrated circuit having a digital-to-analog converter using a series resistor type voltage divider circuit on a semiconductor substrate, and particularly relates to an integrated circuit having a successive approximation type analog-to-digital conversion function. It is related to.
（従来技術）
従来のアナログ・デイジタル変換器（以下、
Ａ／Ｄ変換器と記す）の回路例として、分解能
4bitのＡ／Ｄ変換器を第１図に示し、以下にその
動作を説明する。デイジタル信号に変換されるべ
きアナログ信号は入力端子１から入力される。入
力されたアナログ信号に対してサンプリング回路
２でアナログ信号のレベルVALをサンプリング
し、コンパレータ３に入力する。一方、変換制御
回路４からデイジタル信号Ｄ３，Ｄ２，Ｄ１，Ｄ
０が出力され、デイジタル・アナログ変換器（以
下Ｄ／Ａ変換器と記す）に入力される。Ｄ／Ａ変
換器内では、デイジタル信号Ｄ３，Ｄ２，Ｄ１，
Ｄ０のＨのレベルになつた信号線に接続されたゲ
ートが開きラダー抵抗の分圧で求まる電圧レベル
が５に出力され、コンパレータ３に比較の基準電
圧VD/Aとして入力される。コンパレータ３では
VALがVD/Aよりも高いか低いか比較し、判断信号
５をＡ／Ｄ変換制御回路４に入力する。(Prior art) Conventional analog-to-digital converter (hereinafter referred to as
As an example of a circuit of an A/D converter), the resolution
A 4-bit A/D converter is shown in FIG. 1, and its operation will be explained below. An analog signal to be converted into a digital signal is input from input terminal 1. A sampling circuit 2 samples the analog signal level V AL with respect to the input analog signal and inputs it to a comparator 3. On the other hand, digital signals D3, D2, D1, D are output from the conversion control circuit 4.
0 is output and input to a digital-to-analog converter (hereinafter referred to as a D/A converter). Inside the D/A converter, digital signals D3, D2, D1,
The gate connected to the signal line that has reached the H level of D0 is opened, and the voltage level determined by the voltage division of the ladder resistor is outputted to 5 and inputted to the comparator 3 as the reference voltage V D/A for comparison. In comparator 3
A comparison is made as to whether V AL is higher or lower than V D/A , and a judgment signal 5 is input to the A/D conversion control circuit 4 .
Ａ／Ｄ変換制御回路４では判断信号５によつて
Ｄ３，Ｄ２，Ｄ１，Ｄ０を変化させる。VD/AはＤ
３，Ｄ２，Ｄ１，Ｄ０の値に応じて変化し、Ｄ
３，Ｄ２，Ｄ１，Ｄ０の値が決まるまでVALとの
比較を繰り返す。Ｄ３，Ｄ２，Ｄ１，Ｄ０の値を
決める方法としては周知のバイナリサーチ法など
がある。 The A/D conversion control circuit 4 changes D3, D2, D1, and D0 according to the judgment signal 5. V D/A is D
3, changes depending on the values of D2, D1, D0, and D
3. Repeat the comparison with V AL until the values of D2, D1, and D0 are determined. As a method for determining the values of D3, D2, D1, and D0, there is a well-known binary search method.
図からわかるように、最後に決まつたＤ３，Ｄ
２，Ｄ１，Ｄ０に対応してVD/AとVALとの差は最
大1/16Vrefである。これ以下の値は切り上げか切
り捨される。もし1/16Vref以下のレベルまで判断
したい場合には直列抵抗型分圧回路の分圧抵抗の
数を分解能に対応した数に増さなければならず、
また選択回路も多くなり特に集積回路の場合はレ
イアウト面積を大きくしなければならないという
欠点が生じる。 As you can see from the figure, the last determined D3, D
2, D1, and D0, the maximum difference between V D/A and V AL is 1/16V ref . Values below this will be rounded up or down. If you want to judge levels below 1/16V ref , you must increase the number of voltage dividing resistors in the series resistor type voltage dividing circuit to the number corresponding to the resolution.
Furthermore, the number of selection circuits increases, and especially in the case of an integrated circuit, the layout area must be increased, which is a drawback.
（発明の目的）
本発明の目的は、Ａ／Ｄ変換部の直列抵抗型分
圧回路のレイアウト面積を差程大きくせずにＡ／
Ｄ変換器の分解能が向上する回路を提供すること
にある。(Object of the Invention) An object of the present invention is to provide an A/D converter without significantly increasing the layout area of the series resistor type voltage divider circuit of the A/D converter.
An object of the present invention is to provide a circuit that improves the resolution of a D converter.
（発明の構成）
このような目的を達成するために、本発明で
は、アナログデイジタル変換部における直列抵抗
型分圧回路を、ｎ個の直列接続された抵抗群でな
る第１の直列抵抗回路と、ｍ個の直列接続された
微調整抵抗群でなり前記第１の直列抵抗回路の一
端に接続された第２の直列抵抗回路と、ｍ個の直
列接続された微調整抵抗群でなり前記第１の直列
抵抗回路の他端に接続された第３の直列抵抗回路
と、前記第１の直列抵抗回路における複数の抵抗
接続点のうち一つの接続点を選択して出力する第
１の選択回路と、前記第２の直列抵抗回路におけ
る複数の抵抗接続点のうちの一つの接続点を一方
の電源端子に接続し前記第３の直列抵抗回路にお
ける複数の抵抗接続点のうちの一つの接続点を他
方の電源端子に接続する第２の選択回路とを有し
て構成したことを特徴とする。(Structure of the Invention) In order to achieve such an object, the present invention replaces the series resistance type voltage divider circuit in the analog-to-digital converter with a first series resistance circuit consisting of a group of n series-connected resistances. , a second series resistance circuit comprising m fine adjustment resistance groups connected in series and connected to one end of the first series resistance circuit; and a second series resistance circuit comprising m fine adjustment resistance groups connected in series. a third series resistance circuit connected to the other end of the first series resistance circuit; and a first selection circuit that selects and outputs one of the plurality of resistance connection points in the first series resistance circuit. and one connection point among the plurality of resistance connection points in the second series resistance circuit is connected to one power supply terminal, and one connection point among the plurality of resistance connection points in the third series resistance circuit is connected to one of the plurality of resistance connection points in the third series resistance circuit. and a second selection circuit connected to the other power supply terminal.
（実施例の説明）
以下、本発明の実施例について図面を参照しな
がら詳しく説明する。第２図は本発明の一実施例
を示したものである。アナログ信号値のサンプリ
ングレベルが第３図のように直列抵抗画型分圧回
路の出力レベルの間のレベルにあるとする。第２
図の第１のＡ／Ｄ変換制御回路９でＤ３〜Ｄ０ま
での値を決定する。このときCSWはＨレベルで
ある。この場合、9/16VrefつまりＤ３〜Ｄ０が
1000になつたとする。次に、Ａ／Ｄ変換器の制御
を第２の制御回路１０に移す。このときCSW＝
Ｌレベルになるようにする。初めにDS０のみ１
にすると第２図の直列抵抗分圧回路の出力１１は
９／１６Vrefから（８＋1/4）Vref／16に変化する。
制御回路１０はVsan＞（８＋1/4）Vref／16なの
で、次にDS１のみ１にする。出力１１は（８＋
１／４）Vref／16から（８＋2/4）Vref／16に変化す
る。制御回路１０はまだVsan＞（８＋2/4）Vref／
16なので、さらにDS２のみ１になるように動作
する。出力１１は（８＋3/4）Vref／16に変化す
る。この時点でVsan＞（８＋3/4）Vref／16となり
DS３〜DS０は0010に決定される。この場合の
Vsanと直列抵抗型分圧回路の出力レベルの誤差
は、（８＋2/4）Vref／16＜Vsan＜（８＋3/4）
Vref／16なので最大（８＋3/4）Vref／16−（８＋
２／４）Vref／16＝1/4Vref／16＝1/64Vrefとなり、
従来の誤差Vref／16に対して誤差1/64Vrefの高分
解能を有することがわかる。第１図と第２図を比
較すると、第２図では電源側のＲ／４の微調整抵
抗群とトランジスタ、接地側のＲ／４の微調整抵
抗群とトランジスタ、および制御回路１０が付加
されるが、誤差1/64Vrefまで分解能を上げる為に
抵抗Ｒを増しＤ３〜Ｄ１側の選択回路を増す事を
考えれば、第２図の回路ほうがレイアウト面積を
縮小することができることは容易にわかる。(Description of Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 shows an embodiment of the present invention. Assume that the sampling level of the analog signal value is between the output levels of the series resistor voltage divider circuit as shown in FIG. Second
The first A/D conversion control circuit 9 shown in the figure determines the values D3 to D0. At this time, CSW is at H level. In this case, 9/16V ref or D3~D0 is
Suppose it reaches 1000. Next, control of the A/D converter is transferred to the second control circuit 10. At this time, CSW=
Make it L level. First DS0 only 1
Then, the output 11 of the series resistor voltage divider circuit in FIG. 2 changes from 9/16V ref to (8+1/4)V ref /16.
Since V san > (8+1/4) V ref /16, the control circuit 10 next sets only DS1 to 1. Output 11 is (8+
1/4) V ref /16 to (8+2/4) V ref /16. The control circuit 10 still has V san > (8+2/4) V ref /
Since it is 16, it operates so that only DS2 becomes 1. Output 11 changes to (8+3/4)V ref /16. At this point, V san > (8 + 3/4) V ref /16.
DS3 to DS0 are determined to be 0010. In this case
The error between V san and the output level of the series resistor voltage divider is (8 + 2/4) V ref /16 < V san < (8 + 3/4)
Since V ref /16, the maximum (8 + 3/4) V ref /16 - (8 +
2/4) V ref /16 = 1/4V ref /16 = 1/64V ref ,
It can be seen that it has a high resolution with an error of 1/64V ref compared to the conventional error V ref /16. Comparing Fig. 1 and Fig. 2, in Fig. 2, a group of R/4 fine adjustment resistors and transistors on the power supply side, a group of R/4 fine adjustment resistors and transistors on the ground side, and a control circuit 10 are added. However, if you consider increasing the resistance R and increasing the selection circuit on the D3 to D1 side in order to increase the resolution to an error of 1/64V ref , it is easy to see that the circuit in Figure 2 can reduce the layout area. .
また、第４，５図のように回路でも前記説明の
動作が可能な事は容易にわかる。第４図は接地側
の抵抗を並列に接続したときの例である。R1〜
Riまでのどの抵抗を並列に接続するか第２の選択
回路１２で選択してやりさらに選択回路１２で電
源Vref側の抵抗R10〜Riまでの抵抗を直列抵抗の
全体の合成抵抗が変化しないように選択してやれ
ばよい。第５図は電源例を並列に接地側を直列に
した場合の例である。これらにおいても、同様の
効果を有するものである。 Furthermore, it is easy to see that the operation described above is also possible with the circuits shown in FIGS. 4 and 5. FIG. 4 is an example when the ground side resistors are connected in parallel. R1 ~
The second selection circuit 12 selects which resistors up to R i are connected in parallel, and the selection circuit 12 changes the total combined resistance of the series resistors from R 10 to R i on the power supply V ref side. You can choose not to do so. FIG. 5 shows an example in which the power supplies are connected in parallel and the ground side is connected in series. These also have similar effects.
第１図は従来のＡ／Ｄ変換器の回路図である。
第２図は本発明の一実施例によるＡ／Ｄ変換器の
回路図である。第３図は特性図である。
６……アナログ信号、７……サンプリング回
路、８……比較器。
第４図および第５図は夫々本発明の他の実施例
の回路図である。
１３……第１の選択回路、１４……第２の選択
回路、１５……第１の選択回路。
FIG. 1 is a circuit diagram of a conventional A/D converter.
FIG. 2 is a circuit diagram of an A/D converter according to an embodiment of the present invention. FIG. 3 is a characteristic diagram. 6...Analog signal, 7...Sampling circuit, 8...Comparator. 4 and 5 are circuit diagrams of other embodiments of the present invention, respectively. 13...first selection circuit, 14...second selection circuit, 15...first selection circuit.
Claims (1)
アナログデイジタル変換部を具備した集積回路に
おいて、前記直列抵抗型分圧回路は、ｎ個の直列
接続された抵抗群でなる第１の直列抵抗回路と、
ｍ個の直列接続された微調整抵抗群でなり前記第
１の直列抵抗回路の一端に接続された第２の直列
抵抗回路と、ｍ個の直列接続された微調整抵抗群
でなり前記第１の直列抵抗回路の他端に接続され
た第３の直列抵抗回路と、前記第１の直列抵抗回
路における複数の抵抗接続点のうちの一つの接続
点を選択して出力する第１の選択と、前記第２の
直列抵抗回路における複数の抵抗接続点のうちの
一つの接続点を一方の電源端子に接続し前記第３
の直列抵抗回路における複数の抵抗接続点のうち
一つの接続点を他方の電源端子に接続する第２の
選択回路とを有することを特徴とする集積回路。1. In an integrated circuit equipped with an analog-to-digital converter having a series resistance type voltage divider circuit on a semiconductor substrate, the series resistance type voltage divider circuit is a first series resistance circuit including a group of n resistors connected in series. and,
a second series resistance circuit comprising m fine adjustment resistance groups connected in series and connected to one end of the first series resistance circuit; and a second series resistance circuit comprising m fine adjustment resistance groups connected in series and connected to one end of the first series resistance circuit; a third series resistance circuit connected to the other end of the series resistance circuit; and a first selection for selecting and outputting one connection point from among the plurality of resistance connection points in the first series resistance circuit. , one connection point among the plurality of resistance connection points in the second series resistance circuit is connected to one power supply terminal;
and a second selection circuit that connects one of the plurality of resistance connection points in the series resistance circuit to the other power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288728A JPS62145857A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288728A JPS62145857A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62145857A JPS62145857A (en) | 1987-06-29 |
| JPH0578943B2 true JPH0578943B2 (en) | 1993-10-29 |
Family
ID=17733916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60288728A Granted JPS62145857A (en) | 1985-12-20 | 1985-12-20 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62145857A (en) |
-
1985
- 1985-12-20 JP JP60288728A patent/JPS62145857A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62145857A (en) | 1987-06-29 |
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