JPH0576268B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an inverter device that sends out an output voltage that is pulse width modulated (PWM) for the purpose of harmonic reduction and that is intermittent at a high frequency for the purpose of voltage regulation.

Prior Art The above-mentioned inverter device has been proposed by the applicant of the present invention, for example, in Japanese Patent Application Laid-Open No. 150973/1983. However, no method has yet been proposed for easily achieving intermittent output voltage, ie, second pulse width modulation.

OBJECT OF THE INVENTION Therefore, an object of the present invention is to provide an inverter device that can easily adjust voltage.

Structure of the Invention To achieve the above object, the present invention includes an inverter that converts direct current to alternating current by on/off operations of switching elements, an oscillator that generates a predetermined frequency signal, and a digital converter that converts the output frequency of the oscillator into a digital signal. a variable frequency divider that divides and outputs the frequency at a frequency division ratio determined by a signal; and harmonic component reduction of a frequency corresponding to the output frequency of the variable frequency divider in order to control the switching element of the inverter. a fundamental wave generation circuit that generates a fundamental wave for use in the inverter; a frequency control digital counter that generates a digital signal for changing the frequency division ratio of the variable frequency divider; a starting frequency setting circuit that presets the starting frequency to a starting frequency (fs); a starting digital counter that starts counting clock signals in synchronization with the starting of the load of the inverter to generate a starting digital signal (DC); A logical triangular wave (D _B ) obtained by the digital output gradually increasing from the minimum value to the maximum value, and then gradually decreasing from the maximum value to the minimum value at the repetition frequency of the fundamental wave a logic triangular wave generating circuit that generates at a repetition frequency sufficiently higher than the starting digital counter, the starting digital signal (Dc) generated from the starting digital counter, and the logical triangular wave (D _B ) supplied from the logical triangular wave generating circuit. A starting digital comparator that performs digital comparison and generates a high-level output during a period in which the logical triangular wave (D _B ) is smaller or larger than the starting digital signal (Dc); The frequency control digital counter detects the completion of the start-up period of the load in response to reaching the specified value, and uses the detection signal to release the preset state of the frequency control digital counter and start clock counting. A start-up completion detection circuit that controls a counter digitally compares the logic triangular wave (D _B ) with a reference digital signal (D _A ) consisting of the output of the digital counter for frequency control or its correction signal, and the reference digital signal ( Logic triangular wave (D _B ) than D _A )
a digital comparator for main intermittent control that generates a high-level output during a period when the start-up period is small or large; a selection circuit that sends out the output of the control digital comparator;
In response to the output of the selection circuit, the fundamental wave or the DC power supply voltage of the inverter is obtained from the startup digital comparator so that the output voltage of the inverter gradually increases with a constant frequency during the startup period. The fundamental wave or the DC power supply voltage of the inverter is controlled by the main intermittent control digital signal so that the fundamental wave or the DC power supply voltage of the inverter is intermittent based on the pulse train generated by an intermittent circuit that is intermittent based on a pulse train obtained from a comparator; a target frequency setting circuit that generates a digital signal corresponding to a target output frequency after the startup period of the inverter; An inverter device comprising a target value control comparator that compares a digital signal with the output digital signal of the frequency control counter and generates an output that stops the counting operation of the frequency control counter when both signals match. It is related.

Effects of the Invention According to the above invention, since the signal for intermittent control is formed based on the comparison between the logical triangular wave and the reference digital signal, intermittent control can be easily achieved. In addition, a digital start-up counter, a start-up digital comparator, and a start-up completion detection circuit are provided.
Start-up can be easily achieved.

Embodiment Next, an inverter device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 9. In FIG. 1 showing an inverter device, numeral 1 is an inverter in which, for example, six switching elements such as transistors are connected between a pair of DC power lines to form a three-phase bridge circuit.
The inverter 1 of this embodiment is a variable frequency and variable voltage inverter for driving an AC induction motor 1a as a load.

Reference numeral 2 denotes a harmonic reduction fundamental wave generation circuit, as shown in FIG. This generates a fundamental wave for reducing harmonics. This fundamental wave generating circuit 2 is the same as the PWM wave forming circuit disclosed in Japanese Patent Laid-Open No. 56-150973 or Japanese Patent Application No. 57-65635. It is configured to generate a PWM wave pulse in response to reaching a predetermined value. Further, the fundamental wave generating circuit 2 of this embodiment is constructed so that the frequency of the triangular wave changes in response to changes in the clock frequency, and at the same time, the frequency of the fundamental wave changes as well.

3 is an intermittent circuit that combines the fundamental wave shown in FIG. 2A supplied from the fundamental wave generation circuit 2 and the sufficiently high-frequency pulse train shown in FIG. 2B supplied from the voltage control circuit 4 surrounded by a dotted line. The control pulse (second
PWM waves) are generated and supplied as on/off control signals for the switching elements of the inverter 1. That is, this circuit generates a waveform C corresponding to the AND output of the waveform A and the waveform B in FIG. 2. Although not shown, the inverter 1
If there are three phases, control pulses for three phases are required, so a circuit for forming control pulses for three phases is of course provided. This type of three-phase control circuit can be easily achieved by the method disclosed in Japanese Patent Application Laid-Open No. 56-150973 or Japanese Patent Application No. 57-65635, so a description thereof will be omitted.

In this embodiment, the motor 1 is controlled by the inverter 1.
A is configured to be driven along a characteristic line of frequency f and output voltage V shown in FIG. That is, from the first point P ₁ with voltage O and frequency f _S ) the voltage
V _A frequency f _S is changed to point P ₂ , and then frequency f
The target frequency f _K is maintained by keeping the voltage V and the voltage V in a nearly proportional relationship.
and the target voltage _VK to a third point _P3 .

FIG. 4 shows the relationship in FIG. 3 with the horizontal axis representing the time axis. The output frequencies f and E of this Fig. 4D
As is clear from the output voltage V in Fig. 3, P ₁ ~
The P ₂ section corresponds to the startup period from t ₀ to _{t 1} , the P ₂ to _{P 3} section corresponds to the f/V increase section from t ₁ to _{t 2} , and the P ₃ point corresponds to the set target operation period after t ₂ . corresponds to

Next, a circuit for performing variable frequency and variable voltage control as shown in FIGS. 3 and 4 will be explained. In FIG. 1, 5 is a constant frequency oscillator, which generates a frequency signal that is the basis of control. 6 is a variable frequency divider, ie, a rate multiplier, which divides the output frequency of the oscillator 5 and supplies the divided frequency to the fundamental wave generation circuit 2 at the next stage. That is, this frequency divider 6 is the fundamental wave generating circuit 2.
generate a frequency signal for determining the output frequency of the In other words, the frequency of the fundamental wave and the output frequency of the inverter 1 are determined in accordance with the output frequency of the variable frequency divider 6.

7 is a digital counter for frequency control that can be preset, and it controls the frequency division ratio of the variable frequency divider 6, and voltage controls the reference digital signal in order to change the output voltage in accordance with the output frequency of the inverter 1. It is supplied to the circuit 4. Note that the clock input to this counter 7 is given from a frequency divider 8 which divides the frequency of the output of the oscillator 5.

Reference numeral 9 denotes a starting frequency setting circuit, which sends out a digital signal at the time of starting to preset the counter 7 to a digital count value corresponding to the starting frequency _fs in order to determine the starting frequency of the AC induction motor 1a. It is something.

Reference numeral 10 designates a control line for inhibiting the counting operation of the counter 7, and the counter 7 continues to send out the digital value preset by the starting frequency setting circuit 9 while a high level inhibition signal is input here.

11 is a target frequency setting circuit which outputs a digital value corresponding to the target frequency of the motor 1a after startup. Note that the output of the target frequency setting circuit 11 can be controlled by the variable control circuit 11a. 12 is a digital comparator which compares the target frequency digital value given from the target frequency setting circuit 11 and the output digital value of the counter 7, and when the two match, outputs an output to stop counting to the counter 7.
It is given to Since various circuits are added to the counter 7 as described above, the inverter 1
The output frequency can be changed as shown in FIG. 4D.

The voltage control circuit 4 is for changing the output voltage of the inverter 1 in synchronization with the starting of the motor 1a as shown in FIG. 15, a correction reference digital signal generation circuit 16, a main intermittent control digital comparator 17, a selection circuit 18, and a startup completion detection circuit 19.

5 shows the voltage control circuit 4 of FIG. 1 in more detail.
Each part will be explained with reference to the drawings. The starting digital counter 14 is cleared in response to the starting signal generated at time _t0 in _FIG . is sent to the comparator 15.

The logic triangular wave generation circuit 13 converts the clock provided from the oscillator 20 into an up/down counter 21.
This circuit generates a logical triangular wave D _B of several kHz consisting of the digital signal shown in FIG. 6A by counting at . In order to enable the generation of this triangular wave D _B , a counter control circuit 22, a triangular wave maximum value signal generation circuit 23, and a digital comparator 24 are provided. The triangular wave maximum value signal _{D M} is a digital signal corresponding to the apex of the triangular wave D _B in FIG.
Compare D _M and detect that it is the apex of the triangular wave. The counter control circuit 22 causes the counter 21 to count up from the minimum value 0 to the maximum value D _M as shown in FIG. 6A, and then causes the counter 21 to count down from the maximum value D _M to 0 in response to the output of the comparator 24. , in response to the borrow signal of the carry terminal at count zero, control is performed to increase the count again from 0 to the maximum value D _M. Also, this control circuit 2
2 also controls the counter 21 to synchronize with a synchronization signal given to synchronize with the fundamental wave generation circuit 2. That is, in the preferred synchronization state, the seventh
A triangular wave is generated according to the relationship shown in the figure, and when synchronization is lost, a triangular wave is generated in the state shown in FIG. 8 or 9. If synchronization is achieved as shown in FIGS. 8 and 9, it will be convenient to obtain PWM waves centered around 90 degrees as disclosed in Japanese Patent Application No. 57-65635.

In the starting digital comparator 15, the triangular wave
D _B and the activation digital signal D _C are compared as shown in FIG. 6A, and a high level output is delivered during a period where D _C >D _B. Since the starting digital signal D _C rises from zero, as time passes, the comparator 1 shown in FIG.
The width of the output pulse of No. 5 becomes larger. That is, as shown in FIG. _{4B ,} the activation digital signal D _C
As T gradually increases, the output pulse width of the comparator 15 becomes large, and the pulse width _T1 in FIG. 2B given to the intermittent circuit 3 in FIG. The output voltage gradually increases as shown in Figure E. The output of the comparator 15 is t ₀ in FIG.
It is only used during the start-up period ~ _t1 , after which the output of the other comparator 17 is used.

The main intermittent control digital comparator 17 is a logical triangular waveform.
D _B and the correction reference digital signal D _A given from the correction reference digital signal generation circuit 16 are shown in FIG.
A high level pulse is generated as shown in FIG. 6C in the section where D _A >D _B.

The correction reference digital signal generation circuit 16 is a digital addition circuit, that is, an adder circuit, and as is clear from FIG. 1, it receives the output of the counter 7 and the correction signal, and generates the added output of these as the correction reference digital signal D _A. do. In order to minimize the input current of the inverter 1a, this correction amount is determined so that f and V are not directly proportional as shown by the dotted line, but are shifted to the position shown by the solid line, as shown in FIG. . Therefore, if no correction is required, the counter 7
The comparator 17 uses the output of the reference digital signal D _A as the reference digital signal D A.
You may also enter the information in Correction reference digital signal D _A
corresponds to the output of the counter 7, so the output pulse of the comparator 17 corresponds to the output of the counter 7.

In order to keep the output frequency f at a constant starting frequency f _S during the starting period from t ₀ to t ₁ in FIG. 4, the counter 7 is fixed at a preset state corresponding to f _S as shown in FIG. 4 C. There is. Therefore, the frequency division ratio of the variable frequency divider 6 shown in FIG. 1 is also kept constant, and the fundamental wave frequency and the inverter output frequency are also kept at the starting frequency _fS . Further, a reference digital signal is supplied to the comparator 17 via the correction reference digital signal generation circuit 16.
D _C is also kept constant in the period from t ₀ to t ₁ as shown in FIG. 4B. However, since the output of the starting digital comparator 15 is selected by the selection circuit 18,
The output voltage V gradually increases as shown in FIG. 4E.

At time t ₁ in FIG. 4, the frequency fixing is released as shown in FIG. 4C, and the output frequency f is set as shown in FIG. 4D.
The start-up completion detection circuit 19 for making it possible to increase the correction reference digital signal DA and increase the correction reference digital signal D _A as shown in FIG. 27 and a flip-flop 28. This circuit 1
Flip-flop 19 at point 9 is reset by the activation signal at time _t0 , and the output is kept at a high level. AND gate 25 is digital comparator 1 for startup
5, the D _A =D _B signal obtained from the main intermittent control digital comparator 17, and the carry signal obtained from the addition circuit forming _the correction reference digital signal generation circuit 16, are transferred to the inverter ₂₉ . input the inverted signal, and send this output to the next stage.
It is supplied to the set terminal of flip-flop 28 via OR gate 27. That is, AND gate 25
from the start-up digital comparator 15 supplied to
The D _C = D _B signal is a signal instantaneously generated at time t ₂ when the starting digital signal D _C crosses the triangular wave D _B , as shown in Fig. 6 D, that is, the leading edge differential pulse of the pulse shown in Fig. 6 B. The D _A = D _B signal from the main intermittent control digital comparator 17 is shown in Fig. 6E.
As shown in , the correction reference digital signal D _A is a triangular wave D _B
The signal instantaneously generated at the time t ₁ crossing the 6th
This signal corresponds to the pulse leading edge differential pulse in Figure C, and the signal obtained by inverting the carry signal with the inverter 29 is a high level signal during normal operation, so after all,
When D _C gradually increases to D _A = D _B = D _C in FIG. 6A, that is, at time t ₁ in FIG. 4, a high level pulse is generated from the AND gate 25, and the flip-flop 28 is set. be done. When flip-flop 28 is set at _t1 in FIG. 4, its output goes low, and this low level signal is sent to counter 7 in FIG.
is supplied as a count operation start signal, that is, a count prohibition release signal. Therefore, from time _t1 in FIG. 4, the counter 7 allows the clock pulse to be accepted and starts counting by adding it to the preset value given by the starting frequency setting circuit 9, and the frequency division ratio of the frequency divider 6 gradually increases. As a result, the output frequency of the inverter 1 gradually increases from the starting frequency f _S as shown in FIG. 4D. In addition, the correction reference digital signal D _A is also
It rises as shown in Figure B. Note that the correction reference digital signal _DA rises at a smaller slope than the starting digital signal D _C.

Another AND gate 26 included in the startup completion detection circuit 19 in _FIG.
=D _B signal and the D _B =D _M signal of comparator 24 are input, and this output is applied to flip-flop 28 via OR gate 27 as a set signal. this
AND gate 26 detects D B when the correction reference digital signal D _A is set to _{the maximum value D M of} the triangular wave D _B
=D _M =D This is a circuit for considering that startup is complete at the time of _C , and is mainly a circuit for preventing abnormal operation.

The selection circuit 18 consists of an OR gate 30 and an AND gate 31, as shown in FIG. OR gate 3
0 is input with the D _A > D _B signal of the comparator 17 and the carry signal of the correction reference digital signal generation circuit 16, that is, the signal when the digital adder overflows, and the AND gate 31 is compared with the output of the OR gate 30. The D _C > D _B signal of the device 15 is input. Since the carry signal is not generated during normal operation, the selection circuit 18 selects either the D _A > D _B signal or the D _C > D _B signal during normal operation. That is, a high-level output pulse is sent from the AND gate 31 only during a period when both the output of the comparator 17 and the output of the comparator 15 are generated. Since D _{C <} D _A in the period t ₀ to _{t 1} in FIG. 4, the D C >D _B output pulse of the comparator 15 is narrower than the D _A >D _B output pulse of the comparator 17.
That is, the state is as shown in FIG. 6B and C. As a result, the 6th
The output corresponding to the pulse of comparator 15 shown in Figure B is
It is obtained from the AND gate 31. On the other hand, in Figure 4
After time _t1 , D _C > D _A , so the output pulse width of the comparator 17 based on D _A becomes smaller than the output pulse width of the comparator 15 based on D _C , and the comparator with the smaller pulse width The output of 17 is the selection circuit 18
is selected. Therefore, an intermittent pulse is supplied to the intermittent circuit 3 based on a comparison between the logical triangular wave D _B and the corrected reference digital signal D _A , and voltage control is performed based on this. That is, in the period _t1 to _t2 , the comparator 17
The width of the pulse obtained from this changes depending on the slope of D _A in FIG. 4B, and as a result, the output frequency f and the output voltage V vary from t ₁ to t ₂ as shown in FIGS. 4D and E. f/
It rises with a certain relationship in the V rising section.

When the count of the counter 7 in FIG. 1 progresses and its output becomes a digital output corresponding to the target frequency f _K in FIG. 3 set by the target frequency setting circuit 11,
A count stop signal is generated from the comparator 12, and the counter 7 stops reading the clock signal and outputs the count value at that point. As a result, as shown in Fig. ₄ , after t2, the correction reference digital signal D _A remains constant, the output frequency f is fixed at f _K , and the voltage V is fixed at V _K , and the set The target motion state is reached.

When it is desired to change the target frequency f _K and target voltage V _K , the variable control circuit 11a is activated based on detection or operation.
is operated to change the output of the setting circuit 11. Furthermore, when it is desired to change the relationship between the frequency f and the voltage V, the amount of correction given to the circuit 16 is changed.

As is clear from the above, according to this embodiment, the following effects can be obtained.

(a) Since the intermittent signal is formed based on the comparison between the logical triangular wave D _B and the reference digital signal D _A , intermittent control can be easily achieved.

(b) A starting digital counter 14 and a comparator 15 are provided, and from the first point P ₁ of V=0 and f=f _S , V=
Since the voltage is gradually increased to the second point P ₂ of V _A and f=f _S , the rush current at startup can be easily suppressed.

(c) Instead of simply increasing f and V in a proportional relationship,
f, V with the P′ ₂ points in Figure 3 corrected to P ₂ points.
Therefore, it becomes possible to correct the voltage drop of the motor 1a, etc. This makes it possible to supply V and f to minimize the input current.

(d) Since the frequency f and the output voltage V are controlled based on the output of the common counter 7, the circuit configuration can be simplified.

(e) Since the common logical triangular wave D _B is used for startup and main control, the circuit configuration can be simplified.

(f) Since the selection circuit 18 is constituted by the AND gate 31, selection between the starting pulse and the main control pulse can be easily achieved.

(g) Since the control is based on the logical triangular wave D _B , it is possible to easily make products uniform, change the ratio of f and V, etc.

(h) Since digital processing is used, synchronization as shown in FIGS. 7 to 9 can be easily performed.

Modification (a) In the embodiment, the control signal, that is, the fundamental wave, of the inverter 1 is intermittent at a high frequency having a voltage-controlled pulse width, but instead, the DC power supply voltage of the inverter 1 is intermittent by the output of the selection circuit 18. Good too.

(b) Although a simple fundamental wave is shown in FIG. 2A, it is of course applicable to the case where it is made into a complex PWM wave in order to remove various harmonic components.

[Brief explanation of the drawing]

1 is a block diagram showing an inverter device according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the state of points A to C in FIG. 1 in principle, and FIG. 3 is a diagram of the inverter shown in FIG. 1. A diagram showing the frequency-voltage relationship, Figure 4 is a diagram showing the operation method of the inverter in Figure 1, and Figure 5
The figure is a block diagram showing the voltage control circuit in Fig. 1, Fig. 6 is a waveform diagram showing the states of each part in Fig. 5, and Fig. 7 is a waveform diagram showing the state of each part in Fig.
8 and 9 are waveform diagrams showing the operation of the logic triangular wave generation circuit of FIG. 5. DESCRIPTION OF SYMBOLS 1... Inverter, 1a... Motor, 2... Fundamental wave generation circuit, 3... Intermittent circuit, 4... Voltage control circuit, 5... Oscillator, 6... Variable frequency divider (rate multiplier), 7 ...Frequency control counter,
9... Starting frequency setting circuit, 11... Target frequency setting circuit, 13... Logical triangular wave generation circuit, 14...
... Digital counter for starting, 15... Digital comparator for starting, 16... Correction reference digital signal generation circuit (adding circuit), 17... Digital comparator for main intermittent control, 18... Selection circuit, 19... Starting Completion detection circuit.

Claims (1)

[Scope of Claims] 1. An inverter that converts direct current into alternating current through on/off operations of switching elements, an oscillator that generates a predetermined frequency signal, and a frequency divider that determines the output frequency of the oscillator using a digital signal. a variable frequency divider that divides the frequency by a ratio and outputs the frequency, and a basic wave that generates a harmonic component reduction fundamental wave of a frequency corresponding to the output frequency of the variable frequency divider in order to control the switching element of the inverter. a wave generation circuit; a frequency control digital counter that generates a digital signal for changing the frequency division ratio of the variable frequency divider; A starting frequency setting circuit that presets the inverter load, and a starting digital signal (DC) that starts counting the clock signal in synchronization with the starting of the inverter load.
and a logical triangular wave (D _B ) at a repetition frequency sufficiently higher than the repetition frequency of the fundamental wave; and the starting digital signal (Dc) generated from the starting digital counter and the starting digital signal (Dc) generated from the starting digital counter and supplied from the logical triangular wave generating circuit. Digitally compare the logic triangular wave (D _B ) with the activation digital signal (Dc).
a starting digital comparator that generates a high-level output during a period in which the logical triangular wave (D _B ) is smaller or larger than the starting digital comparator; a start-up completion detection circuit that detects the completion of a start-up period of the frequency control digital counter and controls the frequency control digital counter so as to release the preset state of the frequency control digital counter using the detection signal and start clock counting; Reference digital signal (D _A ) consisting of the output of the digital counter for frequency control or its correction signal
and the logical triangular wave (D _B ) are digitally compared,
a digital comparator for main intermittent control that generates a high-level output during a period in which the logical triangular wave (D _B ) is smaller or larger than the reference digital signal (D _A ); a selection circuit that sends out the output of the inverter and, after the end of the startup period, sends out the output of the main intermittent control digital comparator; The fundamental wave or the DC power supply voltage of the inverter is intermittent based on the pulse train obtained from the starting digital comparator so that the fundamental wave or the DC power supply voltage of the inverter increases gradually with a constant frequency, and after the end of the starting period, the inverter's DC power supply voltage increases gradually with a constant frequency. an intermittent circuit that intermittents the fundamental wave or the DC power supply voltage of the inverter based on a pulse train obtained from the main intermittent control digital comparator so that the output voltage increases in accordance with an increase in frequency; a target frequency setting circuit that generates a digital signal corresponding to the target output frequency after the startup period; and comparing the digital signal obtained from the target frequency setting circuit with the output digital signal of the frequency control counter, and comparing both signals. an inverter device comprising: a target value control comparator that generates an output that stops the counting operation of the frequency control counter when the frequency control counters match;