JPH0576100A - Noncorrelator - Google Patents

Abstract

PURPOSE:To operate the entire noncorrelator producing a two-channel voice signal out from a monochrome voice signal by the same sampling frequency. CONSTITUTION:The noncorrelator is provided with a delay device 102 delaying an input signal, a selection device 103 selecting either of an input signal or an output signal of the delay device 102 at its output, and a controlling device 104 controlling the selection device 103 according to the input signal. The controlling device 104 counts the number of the input signals across the constant A, and controls the output of the delay device 104 to be selected by selecting an input signal each time the number of acrossing the constant A becomes the k times or selecting the constant A once.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decorrelation device for producing a signal having a low correlation with an input signal.

[0002]

2. Description of the Related Art 2 which has a feeling of spreading from a monaural audio signal
In order to generate a channel audio signal, it is sufficient to make the signals of the two channels uncorrelated (for example, Shinichi Ando "Concert Hall Acoustics" Chapter 4, Springer Fairark Tokyo (1987)). ..

Conventionally, as a means for generating a non-correlated signal, for example, a pitch converting device disclosed in Japanese Patent Laid-Open No. 251997/1990 has been used.

A pitch converting apparatus used as a conventional decorrelator will be described below.

FIG. 4 is a block diagram showing the configuration of the pitch converting apparatus. In FIG. 4, 401 is an analog signal for PC
A / D converter for converting to M digital signal, 402
Is a memory, 403 is a memory write address generation circuit,
404 is a first memory read address generation circuit, 40
Reference numeral 5 is a second memory read address generation circuit, 406 is a first latch circuit for latching data read by the first memory read address generation circuit 404, and 407 is data read by the second memory read address generation circuit 405. A second latch circuit for latching the data, and 408 is a first latch circuit for selecting the data in the latch circuit 406 or 407.
Selector circuit 409, a D / A converter 409 for converting the digital data of the first selector circuit 408 to analog, and a reference numeral 410 of the memory read address generation circuit 404 or 405 for reading the analog data currently being finally output. The second selector circuit 411 for selecting the read address on the side is a difference detection circuit for detecting the difference between the memory write address generation circuit 403 and the read address selected by the selector circuit 410, 41.
2 is a data inversion flip-flop circuit controlled by the difference detection circuit 411; 413 is a third selector circuit 414 for selecting the most significant bit on the side to be shifted from among the most significant bits of the latch circuits 406 and 407; The output of the flip-flop circuit 412 is used as a data input,
A flip-flop circuit 415 that receives the output of the selector circuit 413 as a clock input is a flip-flop circuit 413.
Is a data input and the output of the selector circuit 413 is a clock input. A flip-flop circuit 416 is a NAND circuit that obtains the logical product of the inverted output of the flip-flop circuit 414 and the output of the flip-flop circuit 415.
Reference numeral 17 is a NAND that takes the logical product of the output of the flip-flop circuit 414 and the inverted output of the flip-flop circuit 415.
The outputs of the NAND circuits 416 and 417 control the increment of addresses of the memory read address generation circuits 404 and 405, respectively.

FIG. 5 is a waveform diagram for explaining the operation of each part of FIG. In FIG. 5, (a) and (c) are digital data, but for the sake of explanation, they are displayed as analog waveforms.

The operation of the conventional decorrelator (pitch conversion device) configured as described above will be described below.

First, the Q output of the flip-flop circuit 412 which is cleared by the reset becomes "L", and the selector 4
The select signal sel of 13 (hereinafter referred to as a cell) is indefinite at the time of rising, but since the first signal pulse is input, the output of the flip-flop circuit 414 becomes "L", the cell is "L", and the output is 5 (d) is selected. Read address Read read by the latch circuit 406
The data of add1 and the data of the read address Read add2 read by the latch circuit 407 are D / A.
Assuming that the conversion has been performed, the waveforms of FIGS. 5A and 5C are obtained, respectively, and the most significant bit data of FIGS. 5A and 5C at this time are 2's complement codes. FIG. 5 (b),
As shown in (d), the negative half wave is a pulse of "H", and the positive half wave is a pulse of "L".

When the pitch shift is repeated and a region in which a round-trip delay is likely to occur, a clock pulse is applied to the flip-flop circuit 412, and the flip-flop circuit 412.
The output (e) of 12 becomes "H". At this time, FIG. 5 (f)
The output of the flip-flop circuit 414 shown in FIG. 5 is “L”, the output IY output of the latch circuit 407 is as shown in FIG. 5D, and the output becomes IH from FIG. 5 (f) becomes "H" by the rising pulse of FIG. 5 (d), and this time, the IY output of the latch circuit 406 is output as shown in FIG. 5 (b). 5 (f) becomes "H", this time, FIG. 5 (g) becomes "H" at the first rising pulse of FIG. 5 (b), and the data selector 40
8 outputs the data of FIGS. 5 (a) to 5 (c).
This is the data switching point from ReadAdd1 to ReadAdd2, and is the NA of FIGS. 5 (f) and 5 (g).
When ND is taken by the NAND circuit 417, the STOP2 signal is obtained.

That is, the address increase of ReadAdd2 is stopped by the time delay shown in FIGS. 5 (f) and 5 (g),
If the address of Read Add2 is increased again from the switched point, connection can be made in phase at the point of t1.
Next, Read Add2 repeats the pitch shift,
When it becomes a region where a round-trip delay with WRITE Add1 is likely to occur, a clock pulse is applied to the flip-flop circuit 412, the output of the flip-flop circuit 412 is inverted, and the output (e) of the flip-flop circuit 412 is "L".
Becomes The IY output of the latch circuit 406 is as shown in FIG. 5B, and the output (e) of the flip-flop circuit 412.
5L becomes "L" at the first rising pulse of FIG. 5B from the point where the latch circuit 40 becomes "L".
As the IY output of No. 7, the output of FIG. 5 (f) becomes "L", the output of the flip-flop circuit 412 becomes "L" at the first rising pulse of FIG. 5 (d), the cell is "L", and the data is shown in FIG. 5 (a). ) Signal is output. Also at this time, similarly, the cell and the NAND of FIG. 5 (f) are taken by the NAND circuit 416 to obtain the STOP1 signal and
FIG. 5 (f) and FIG. 5 (g) show the address increase of d Add1.
If it is stopped for the delay of, the in-phase connection can be made at the point of t4.

[0011]

However, in the above-mentioned conventional configuration, the sampling frequency Fsw of the data written to the memory and the sampling frequency Fsr of the data read from the memory are different. If a part operating at a different sampling frequency is incorporated into a system operating in synchronization with a sampling cycle, the whole system becomes complicated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a decorrelation device which has no portion operating at different sampling frequencies.

[0013]

In order to achieve this object, a decorrelation device of the present invention comprises a delay device for delaying an input signal, and either the input signal or the output signal of the delay device or a constant A. It has a selection device that selects and outputs one and a control device that controls the selection device according to the input signal.

[0014]

According to the present invention, the input signal is output every k times when the input signal crosses the constant A by the above configuration.
The constant A is output once and then the delayed signal is output, and a non-correlated signal is generated from the input signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the decorrelation device according to the first embodiment of the present invention. In FIG. 1, 101 is a signal input terminal, 102 is a delay device that delays an input signal, and 103 is an input signal or delay device 102.
Of the output signal or the constant A, 104 is a control device for controlling the selection device 103 according to the input signal, and 105 is a signal output terminal.

FIG. 2 is a block diagram showing the configuration of the control device 104. In FIG. 2, 201 is a signal input terminal, 2
02 is a subtracter that subtracts the constant A from the input signal, 203 is a delay device that delays the input signal by one sample, 204 is a subtractor that subtracts the constant A from the output signal of the delay device 203, and 205 is subtraction from the output signal of the subtractor 202 Multiplier multiplied by the output signal of the device 204, 206 is a k-ary counter for counting the number of times the output signal of the multiplier 205 changes from positive to negative, 207 is a toggle device operated by the carry signal of the k-ary counter 206, Reference numeral 208 is a delay device that delays the output of the toggle device 207, and 209 is a gate circuit that inputs the outputs of the toggle device 206 and the delay device 208. The delay device 208 and the gate circuit 209 operate in synchronization with the sampling cycle to form an edge detection circuit 210 that detects the edge of the output of the toggle device 207. 211 is a toggle device 206
OR which takes the logical sum of the output signal of
A circuit, 212 is a first output terminal, 213 is a second output terminal, and 214 is a third output terminal.

FIG. 3 is a waveform diagram for explaining the operation of each part of FIG. The operation of the decorrelation device of this embodiment configured as described above will be described below.

The input signal is, as it is, or after being delayed by one sampling cycle by the delay device 102, the selection device 10 is selected.
Input to 3. The constant A is also input to the selection device 103. The selection device 103 outputs one of the three input signals according to the control signal of the control device 104.

Next, the operation of the control device 104 will be described in detail. The controller 104 counts the number of times the input signal crosses the constant A and accordingly generates a control signal for the selection circuit 103. Hereinafter, for the sake of explanation, the input signal is x
(N) (n is an integer). The signal x (n) input to the signal input terminal 201 is subtracted by the constant A by the subtractor 202 and then input to the multiplier 205. An example of the output of the subtractor 202 is shown in FIG. 3 (a) (note that FIG. 3 (a), (b),
In (h), the central straight line represents the constant A). The input signal x (n) is delayed by the delay device 203, subtracted by the constant A by the subtractor 204, and then input to the multiplier 205. An example of the output of the subtractor 204 is shown in FIG. Multiplier 20
Since the output of 5 is the product of x (n) -A and x (n-1) -A, it takes a negative value when the input x (n) crosses the constant A. If the signal is a two's complement representation, the most significant bit of the signal will be "H" when the value of the signal is negative. This is shown in FIG. The k-ary counter 206 is a multiplier 2
The falling edge of the most significant bit of the output signal of 05 is counted. Then, when the count reaches k, a carry occurs. The counting state is shown in FIG. The toggle device 207 toggles according to the carry signal of the k-ary counter 206. This is shown in FIG. Toggle device 20
The output signal of No. 7 is directly output from the first output terminal 212. The output signal of the toggle device 207 is input to the edge detection circuit 210. The edge detection circuit 210 outputs a logical product of the output signal of the toggle device 207 delayed by one sampling period by the delay device 208 and the inverted signal of the toggle device 207. That is, “H” is output for one sampling period from the fall of the output signal of the toggle device 207. This is shown in FIG. The output signal of the edge detection circuit 210 is output from the third output terminal 214. The OR gate 211 ORs the output signal of the toggle device 207 and the output signal of the edge detection circuit 208. That is, the output signal of the toggle device 207 outputs “H” while the output signal of the toggle device 207 is “L” from the time point when one sampling cycle is delayed after the output signal of the toggle device 207 falls. This is shown in FIG. The output signal of the OR gate 211 is output from the second output terminal 213.

The above is the description of the operation of the control device 104. The selection device 103 selects the input signal while the first output terminal of the control device 104 is “H” and selects the output signal of the delay device 203 while the second output terminal is “H”. Three
If the constant A is set to be selected while the output terminal of the selector is "H", the output signal of the selection device 103 becomes as shown in FIG. The output signal of the delay device 203 is selected before t1 in FIG. At t1, the signal output terminal of the first output terminal of the control device 104 becomes “H”, and the selection device 103
Selects the input signal, the output signal of the selection device 103 has the same waveform as the input signal by skipping the input signal by one sample. At t2, the signal output terminal of the third output terminal of the control device 104 becomes “H”, and the selection device 103 selects the constant A. Then, at t3, the signal output terminal of the second output terminal becomes “H”, and the selection device 103 selects the output signal of the delay device 102. Therefore, the output signal of the selection device 103 is connected to the output signal of the delay device 102 with the constant A inserted at t2.

When the constant A is set to 0, the subtracter 20
2,204 can be omitted. Also, the delay devices 102 and 20
The same thing as 3 can be used.

[0023]

As described above, according to the present invention, the control device alternately outputs the input signal and the delayed input signal. Moreover, one data is skipped every time the constant A is crossed k times, or the constant A is inserted, so that the waveform connection is smooth and the noise is hardly generated. Then, since the input signal and the output signal are shifted in time, the effect of lowering the correlation can be obtained. Further, unlike the case of using the conventional pitch converter, since it does not include a portion operating at a different sampling frequency, it has many practically excellent effects such as realization with much simpler hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a decorrelation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a control device 103 in the same embodiment.

3 is a waveform chart for explaining the operation of each part of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional pitch converting device.

5 is a waveform diagram for explaining the operation of each part of FIG.

[Explanation of symbols]

 101, 201 Signal input terminals 102, 203, 208 Delay device 103 Selection device 104 Control device 105 Signal output terminal 202, 204 Subtractor 205 Multiplier 206 k-ary counter 207 Toggle device 209 Gate circuit 210 Edge detection circuit 211 OR circuit 212 First output terminal 213 Second output terminal 214 Third output terminal

Claims (2)

[Claims] 1. A delay device for delaying an input signal, a selection device for selecting and outputting any one of the input signal, an output signal of the delay device or a constant A, and the selection device according to the input signal. A controller for controlling the selector, wherein the controller counts the number of times the input signal crosses the constant A, and the number of times the constant A crosses the constant A every k times,
Select the input signal or select the constant A once,
After that, the decorrelation device is controlled to select the output of the delay device. 2. The decorrelation device according to claim 1, wherein the constant A is zero.