JPH0575928A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To secure a dynamic range and to attain low noise and high sensitivity by providing a horizontal CCD with the 1st and 2nd electrostatic charge detection circuits and controlling the 2nd charge detection circuit by an output from the 1st charge detection circuit. CONSTITUTION:Incident light upon an image pickup element is photoelectrically converted by photodiodes 1, 3 and stored as charge and the stored charge is transferred to the 1st charge detection circuit 6 through vertical CCD registers 2, 4 and the horizontal CCD 5 and converted into voltage. The converted voltage is inputted to a means 8 for controlling the 2nd charge detection circuit 110 and an output voltage 112 proportional to the charge is outputted from the means 8 and inputted to the circuit 110 to control it. In such constitution, the voltage 112 is outputted to the means 8 controlling the circuit 110 during a period from the input of the charge to the circuit up to its input to the circuit 110 through a signal charge delay means 9. Consequently the circuit 110 can be accurately controlled in accordance with the transferred signal charge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using a CCD register, and more particularly to a solid-state image pickup device having an improved dynamic range of a signal detecting section for finally extracting a signal charge from a CCD type solid-state image pickup device. ..

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIG. In the CCD type solid-state imaging device, there is a system using feedback as a high-sensitivity charge detection circuit having a large saturation signal amount. (February 1991 ISS
CCS Preliminary Collection p.210-p.211) Where
40 is a photodiode, 41 is a vertical CCD register, 4
2 is the rightmost vertical CCD register, 43 is a horizontal CCD
The register 44 is a junction field effect transistor type charge detection circuit provided in the horizontal CCD register. The charge detection circuit 44 is provided at the final stage of the horizontal CCD register. The signal charge photoelectrically converted in the photodiode 40 is transferred to the horizontal C by the vertical CCD registers 41 and 42.
It is transferred to the CD register 43. In the charge detection circuit 44, the drain current is modulated by the signal charge transferred by the horizontal CCD register 43, and converted into a voltage by the source follower circuit configured by the JFET 45. And 2
The current is further amplified by the source follower circuit 46 in the stage. The current-amplified output 47 is input to the means 48 for controlling the charge detection circuit and fed back to the charge detection circuit 44. As a result, when more charges are transferred, the potential of the transfer channel of the charge detection circuit 44 is deepened and the amount of charges that can be handled is increased. Here, the relationship between the signal charge and the output voltage can be expressed as follows.

Q = (Cin / Gv + Cb / Gv + Cb) Va (1) where Cin is the input capacitance of the charge detection circuit, Gv is the voltage gain of the charge detection circuit, Cb is the feedback capacitance, and Va.
Is the output voltage of the charge detection circuit. However, the feedback capacitance Cb is the gate capacitance of the gate electrode 32. It can be seen from the equation (1) that the signal charge Q is obtained from the output voltage Va of the charge detection circuit.

[0004]

However, in the case of the conventional method, the delay time inevitably exists in the feedback system. Therefore, when the clock frequency of the horizontal CCD register increases, the next signal charge is transferred to the charge detector within the delay time until the charge is detected and the signal is used to control the gate voltage provided in the charge detector. There is a possibility that it will be. In such a state, there is concern that accurate feedback may not be applied.

The present invention has been made in consideration of the above circumstances. Even when the clock frequency of the image pickup device is high, the signal charge can be detected with low noise, and the amount of signals that can be handled is large. To provide a solid-state image sensor of the above.

[0006]

The essence of the present invention is to provide a first charge detection circuit for detecting charges in advance, and a signal charge for delaying signal charges by a delay time required for feedforward. The delay means and the second charge detection circuit for detecting and outputting the charge are used, the charge is detected in advance by the first charge detection circuit, and the signal is used for controlling the gate voltage of the second charge detection circuit. To use.

That is, the delay time until the signal is detected by the first charge detection circuit and the gate voltage of the second charge detection circuit is controlled, and the signal charge detected by the first charge detection circuit is the second If the delay time to reach the charge detection circuit is the same, even if the operating frequency of the horizontal CCD register is high,
The gate voltage of the second charge detection circuit can be controlled accurately.

[0008]

According to the present invention, the signal charge transferred by the horizontal CCD register is detected by the first charge detection circuit and converted into a voltage. This voltage is input to the means for controlling the second charge detection circuit. The means for controlling the second charge detection circuit generates a voltage for controlling the gate electrode of the second charge detection circuit according to the input voltage. The second charge detection circuit changes the maximum handled charge amount by this voltage and improves the dynamic range. At this time, the time from the input of charge to the first charge detection circuit to the control of the second charge detection circuit and the charge input to the first charge detection circuit are transferred to the second charge detection circuit. Match the time until it is done. By doing so, even when the operating frequency of the horizontal CCD register is high, the gate voltage of the second charge detection circuit can be accurately controlled.

[0009]

EXAMPLE 1 An example of the present invention will be described below with reference to FIG. Here, 1 and 3 are photodiodes, 2 and 4 are vertical CCD registers, 5 is a horizontal CCD register, 6 is a first charge detection circuit for detecting charges in advance, and 7 is a junction field effect transistor. The first charge detection circuit 6 is a junction type field effect transistor type charge detection circuit, and the junction type field effect transistor 7 constitutes a source follower circuit. 8 is a means for controlling the second charge detection circuit, 9
Is a signal charge delay means, 110 is a second charge detection circuit, 1
Reference numeral 0 is a junction field effect transistor. The second charge detection circuit 110 is a junction-type field effect transistor type charge detection circuit, and the junction-type field effect transistor 10 constitutes a source follower circuit and serves as a first stage output amplifier. Reference numeral 111 is an output amplifier of the first stage.

Next, the overall operation will be described. The light incident on the image sensor is photoelectrically converted by the photodiodes 1 and 3 and stored as electric charges. The charges are transferred to the first charge detection circuit 6 by the vertical CCD registers 2 and 4 and the horizontal CCD register 5. In the first charge detection circuit 6, the drain current is modulated by the signal charge and converted into a voltage by the source follower circuit configured with the junction field effect transistor 7. The converted voltage is input to the means 8 for controlling the second charge detection circuit, and the output voltage 112 proportional to the charge input here is output. The output voltage 112 is input to the second charge detection circuit 110 for control. Here, the charge is input to the first charge detection circuit 6,
Means 8 for controlling the second charge detection circuit until it is input to the second charge detection circuit via the signal charge delay means 9.
The output voltage 112 of is output.

As a result, the second charge detection circuit 110 can be accurately controlled according to the transferred signal charge. At this time, the relationship between the signal charge and the output voltage can be expressed as follows.

Q = (Cin / Gv + Cf / Gv−Cf) Va−CfVb (2) where Cin is the input capacitance of the charge detection circuit, Gv is the voltage gain of the charge detection circuit, and Cf is the feedforward capacitance.
Va is the output voltage of the charge detection circuit, and Vb is the output voltage of the control means 8. Therefore, it can be seen that the signal charge is obtained from Va and Vb.

From the equation (2), the output voltage Vb of the control means 8
Is a function that changes continuously with the signal charge Q,
The output voltage Va of the charge detection circuit and the signal charge Q are uniquely determined. Therefore, by examining the relationship between Vb and Q in advance, it is possible to observe only the output voltage Va and obtain the signal charge Q by the signal processing in the subsequent stage.

Next, the control method of the charge detection circuit will be described in detail with reference to FIGS. 4, 7, and 8. 4, 36 and 37 are horizontal CCD electrodes and 31 is a horizontal CCD.
A junction-type field effect transistor type charge detection circuit provided in the register, 38 is a reset gate, 39 is a reset drain, 101 is an n-type diffusion layer for a buried channel, and 102 is a p-type diffusion layer. FIG. 7 is a cross-sectional structural view taken along the dotted line AB in FIG. 4, in which an n diffusion layer 101 for realizing a buried channel is formed right below a gate electrode 32 for controlling a charge detection circuit. FIG. 8 is a cross-sectional structural view taken along the dotted line CD. The p + diffusion layer 103 is provided on both sides of the second charge detection circuit control gate electrode 32.
30 are provided and respectively serve as a drain and a source of the junction field effect transistor. The drain current of the junction field effect transistor flows below the n diffusion layer 101 for the buried channel.

Next, the operation will be described. Horizontal CCD
The signal charge Q1 transferred by is converted into a voltage by the first charge detection circuit in advance, and is input to the second charge detection circuit control gate electrode 32 through the means 48 for controlling the second charge detection circuit. .. At this time, the second detection circuit 30
Since the signal charge Q1 is input to, the feedforward is accurately performed. In addition, the detection of the signal charge is
In FIG. 8, the gate electrode 3 for controlling the second charge detection circuit
This is performed by modulating the current flowing under the n diffusion layer 101 by the signal charge Q1 input under 2. Then, the voltage of the gate electrode 32 for controlling the second charge detection circuit is controlled by the means 48 for controlling the second charge detection circuit according to the input signal charge amount. As a result, the depth of the potential of the charge detection circuit unit is controlled, and the amount of charge handled by the charge detection circuit changes.

Further, in the present embodiment, the first charge detection circuit 6 can be a floating gate type charge detector. This structure facilitates manufacturing and has an effect of cost reduction. Further, the junction field effect transistor 7 or 10 also has similar effects because the structure is simplified and the manufacturing is facilitated by using a MOS transistor.

Regarding the peripheral circuits of the first charge detection circuit 6 and the second charge detection circuit 110, it is of course possible to configure the circuits outside the chip, but by making them on-chip, the user can see them. It requires no external parts and is extremely easy to use.

Further, in the present embodiment, the description has been made using the p substrate, but it is also possible to use the n substrate.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIG. Here, 20 represents a voltage switch, and 21 represents several kinds of set voltages.

Next, the operation of this embodiment will be described.
The signal charge transferred by the horizontal CCD register 5 modulates the drain current of the first type charge detection circuit 6,
It is converted into a voltage by the source follower circuit composed of the junction field effect transistor 7. Next, the set voltage 21 is switched by the set voltage switching unit 20 according to the range of the transferred signal charge amount by the converted voltage range. Here, the set voltage switching means 20 switches the set voltage 21 until the electric charge is input to the first charge detection circuit 6 and then to the second charge detection circuit via the signal charge delay means 9. For example, a case where four types of set voltages are used will be described with reference to FIG. FIG. 5 shows the relationship between the amount of signal charge transferred to the first type charge detection circuit 6 and the output voltage Vb of the setting voltage switching means 20, and the signal charge when the signal charge is transferred to the second charge detection circuit 110. The relationship between the signal charge amount and the output voltage Va is shown. When the signal charge amount input to the first type charge detection circuit is Qin, V1 and Qa <when 0 <Qin <Qa
V2 when Qin <Qb, V2 when Qb <Qin <Qc
3, when Qc <Qin <Qd, V4 is output as the output voltage Vb of the set voltage switching means 20. The output voltage Va at that time has a sawtooth shape.

Next, the effect will be described. Since the first charge detection circuit 6 serves both as a charge detector and a transfer CCD,
The detection capacitance cannot be made smaller than that of the second charge detection circuit 110. Therefore, the sensitivity becomes lower than that of the second charge detection circuit 110.
There is a possibility that the second charge detection circuit 110 cannot be accurately controlled by the output signal of. Therefore, in the present embodiment, the voltage switch 20 is used to switch between several kinds of set voltages 21 to control the second charge detection circuit 110. Then, as is clear from the equation (2) described above, the signal charge Q can be obtained using the output voltage Va of the charge detection circuit and the output voltage Vb of the control means 8. By doing so, the potential depth can be changed stepwise in accordance with the amount of signal charges input to the second charge detector 110, and a voltage that does not include noise can be obtained.
The second charge detector 110 can be controlled.

Further, since the set voltage switching means 20 determines four ranges, the result can be used as a 2-bit digital output. In addition, the second charge detection circuit 110 may be used by using a larger set voltage.
Can also be controlled. If the number of set charges is increased,
The amount of charge that can be handled increases, and the number of bits when used as a digital output image pickup device can be increased.

According to the present invention, by providing the output pin for the digital signal in addition to the conventional output pin for the analog signal on the image pickup device, the user can selectively use the analog signal and the digital signal as required. The effect is born.

Embodiment 3 Next, another embodiment of the present invention will be described with reference to FIG. Here, 112 is the output Va of the second source follower circuit.
And the output voltage Vb of the set voltage switching means 20. The output voltage Va of the charge detection circuit and the output voltage Vb of the control means 8 are generated by the signal charges transferred by the horizontal CCD 5. The means 112 for synthesizing these two signals outputs them as one signal. As a result, the user can use the same as a conventional image sensor without paying attention to feedforward.

[0025]

According to the structure using the two charge detection circuits of the present invention, even when the operating frequency of the horizontal CCD register is high as in a high-definition image pickup device, the dynamic range is secured, the noise is low, and the sensitivity is high. A charge detection circuit can be configured.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram for explaining another embodiment of the present invention.

FIG. 3 is a diagram illustrating a conventional technique.

FIG. 4 is a diagram illustrating a conventional technique.

FIG. 5 is a diagram showing a relationship among an input charge, a control voltage, and an output voltage for explaining another embodiment of the present invention.

FIG. 6 is a configuration diagram for explaining another embodiment of the present invention.

7 is a cross-sectional view taken along the line AB in FIG.

FIG. 8 is a sectional view of a CD portion of FIG.

[Explanation of symbols]

1, 3 ... Photodiode, 2, 4 ... Vertical CCD register, 5 ... Horizontal CCD register, 6 ... First charge detection circuit, 7, 10 ... JFET, 8 ... Means for controlling second charge detection circuit, 9 ... Horizontal CCD register for signal charge delay,
110 ... Second charge detection circuit, 111 ... Source follower circuit.

Claims (3)

[Claims] 1. A CCD type image pickup device comprising a photodiode, a vertical CCD register, a horizontal CCD register, and a signal detecting section, which comprises a first charge detecting circuit and a second charge detecting circuit provided in the horizontal CCD register. A solid-state imaging device comprising: a charge detection circuit; and a means for controlling the second charge detection circuit, wherein the output of the first charge detection circuit is used to control the second charge detection circuit. 2. The means for controlling the second charge detection circuit, wherein the voltage for controlling the second charge detection circuit is switched to several kinds of fixed voltages, and the voltage for controlling the second charge detection circuit and the second The solid-state imaging device according to claim 1, wherein an output voltage of the charge detection circuit is used. 3. The solid-state image pickup device according to claim 2, wherein one output is combined from a voltage for controlling the second charge detection circuit and an output voltage of the second charge detection circuit.