JPH0575593A - Initial alarm mask circuit for multiple synchronous detection - Google Patents

Abstract

PURPOSE:To automatically switch the period of a mask signal by discriminating pseudo-synchronism or not with respect to an initial alarm mask circuit of multiple synchronous detection which detects synchronism of plural highways in time division. CONSTITUTION:One of plural highways 1-1 to 1-n is successively selected by a selector 2 and is connected to a synchronizing part 3 to detect and protect the synchronism. The phase of a synchronizing pattern detection signal due to preceding synchronizing pattern hunting and that due to present synchronizing pattern hunting in the synchronizing part 3 are compared with each other by a comparing part 5. If this comparison results in coincidence, a first mask signal from a mask signal generating part 4 is selected and outputted by a selector 6; but otherwise, a second mask signal from the mask signal generating part 4 is selected and outputted by the selector 6, and a step out signal in the initial state is masked by an inhibiting circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initial alarm mask circuit for multiple synchronization detection which performs synchronization detection on a plurality of highways in a time division manner. Generally, a configuration is provided in which a synchronization unit that performs synchronization detection and synchronization protection is provided for each of a plurality of highways. However, as the number of highways increases, it is necessary to provide a synchronization unit corresponding to the number of highways, and the overall circuit scale becomes very large. Therefore, a configuration has been proposed in which one synchronization unit is provided for a plurality of highways to perform synchronization detection and synchronization protection in a time division manner. In such a configuration, each time the highway is selected, the synchronization unit is initialized and the synchronization detection and the synchronization protection are performed.
An alarm indicating out of synchronization will be sent. Since the initial alarm in this case is different from the alarm indicating the actual loss of synchronization, an initial alarm mask circuit is provided to prevent the alarm from being sent to the outside.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. A plurality of highways 51-1 to 51-n are selected by a selector 52 and connected to a synchronizing section 53, and a control section 55 controls the selector 52 and the synchronizing section 53. And the mask signal generation unit 54 are controlled, the synchronization detection unit 56 of the synchronization unit 53 performs the synchronization pattern hunting on the highway selected by the selector 52, and the synchronization protection unit 57 performs the backward protection and the forward protection of the synchronization. .. Then, at the time of out-of-sync, the out-of-sync signal of, for example, "1" is output from the synchronization protection unit 57.

The control unit 55 has highways 51-1 to 51-1.
Each time -n is switched in the selector 52, the mask signal generation unit 54 is activated to generate a mask signal, and the mask signal of "1" is added to the inhibit circuit 58 to make the synchronization unit 53.
The out-of-sync signal output from the synchronization protection unit 57 in the initial state is masked. Therefore, the sending of the alarm signal REC due to the out-of-sync signal in the initial state is blocked.

FIG. 6 is a diagram for explaining the operation of the conventional example. (A)
Is a monitoring period HW of a plurality of highways 51-1 to 51-n
1 to HWn, in which (b) is a highway 51-
It shows about 1. Further, (c) is an out-of-sync signal, (d) is a mask signal, and (e) is a highway 51-in the case of pseudo synchronization.
1 shows the monitoring period HW1 of 1 in which (f) shows an out-of-sync signal in that case, (g) shows a mask signal, (h) shows an unmasked out-of-sync signal, and (i) shows other mask signals. Also FP
Is a sync pattern, PFP is a pseudo sync pattern, A is a sync pattern hunting period, B is a backward protection period, C is a frame sync period, and D is a pseudo sync period.

When, for example, the highway 51-1 of the plurality of highways 51-1 to 51-n is selected by the selector 52 and connected to the synchronizing unit 53, the synchronizing unit 53 is reset to the initial state. As shown in (c), an out-of-sync signal of "1" will be output. And
The synchronization detector 56 detects the synchronization pattern of the highway 51-1. That is, when the detection signal of the synchronization pattern FP is obtained as shown in FIG. 6B, the backward protection period B
If the predetermined number of synchronization patterns FP are continuously detected during the backward protection period B, the frame synchronization period C is entered, and the out-of-sync signal shown in (c) becomes "0".

During the period between the sync pattern hunting period A and the backward protection period B, the out-of-sync signal shown in (c) becomes "1". Therefore, as shown in (d) of FIG. To output the mask signal for the period T1 [> (A + B)], and inhibit the output of the alarm signal REC by the out-of-sync signal in the initial state by the inhibit circuit 58. In the period T1 of the mask signal, the time required for the synchronous pattern hunting can be estimated in advance, and the backward protection period B is determined by the number of backward protection stages. Therefore, the period T1 is set in consideration of this.

Further, as shown in FIG. 6 (e), when the pseudo sync pattern PFP is detected, the sync pattern hunting period A shifts to the backward protection period B, and the backward protection period B.
After that, the period shifts to the pseudo synchronization period D, which is regarded as the frame synchronization period C. During this pseudo synchronization period D, since the pseudo synchronization pattern PFP cannot be detected continuously, the synchronization is lost after the forward protection period, and the period shifts to the synchronization pattern hunting period A again, as shown in (f). The out-of-sync signal is output separately from the out-of-sync signal in the initial state. Then, by detecting the synchronization pattern FP, the backward protection period B is entered, and by continuously detecting a predetermined number of synchronization patterns FP, the frame synchronization period C is entered and the out-of-sync signal is set to "0". ..

In this case, the mask signal shown in (g) is
The mask signal is the same as the mask signal in the period T1 shown in (d), and the out-of-sync signal in the initial state can be masked by this mask signal, but the out-of-sync signal after the pseudo-synchronization period D cannot be masked. Therefore, as shown in (i), the mask signal generator 54 outputs the period T2 [> (A + B
+ D + A + B)] to generate a mask signal to mask the out-of-sync signal in the sync pattern hunting period A and the backward protection period B in the case of such pseudo sync.

[0009]

Problems to be Solved by the Invention Multiple highways 5
When the synchronization detection of 1-1 to 51-n is performed by one synchronization detection unit 53, the synchronization pattern hunting state is set every time the highways 51-1 to 51-n are selectively connected, so that pseudo synchronization occurs. The possibility increases. Therefore, when the mask signal in the period T1 shown in (d) and (g) of FIG. 6 is used, the out-of-sync signal in the case where the pseudo synchronization shown in (f) occurs cannot be masked. When an alarm due to such an out-of-synchronization signal is sent, for example, in a system with an active backup switching configuration, a switching from the active system to the standby system may occur even though no failure has actually occurred. is there.

Therefore, assuming pseudo synchronization, (i) in FIG.
Although unnecessary alarm transmission can be masked by using the mask signal of the period T2 shown in, on the other hand, when the normal frame synchronization period C is entered without entering the pseudo synchronization, the frame synchronization period C is entered. Immediately after that, even if loss of synchronization occurs due to a failure of the transmission path or the like, there is a drawback that an alarm due to the loss of synchronization signal cannot be transmitted. It is an object of the present invention to automatically switch the period of a mask signal by determining whether it is pseudo synchronization or not.

[0011]

An initial alarm mask circuit for multiple synchronization detection according to the present invention will be described with reference to FIG. 1. A plurality of highways 1-1 to 1-n are sequentially selected by a selector 2.
The synchronization pattern hunting of the selected highway, the backward protection and the forward protection are performed by the synchronization unit 3, and the initial alarm of the synchronization unit 3 is masked by the mask signal generation unit 4.
The mask signal generator 4 uses a first mask signal in a period including at least a synchronization pattern hunting period and a backward protection period, and at least a synchronization pattern hunting period and a backward protection period. Of the second mask signal of the period including the period of time and the period of the forward protection, and a comparison unit 5 for comparing the phase of the synchronization pattern detection signal by the synchronization pattern hunting from the synchronization unit 3. When the comparison is made by the comparison unit 5, the first mask signal from the mask signal generation unit 5 is selected and used as the mask signal of the initial alarm. When the comparison is not made, the second mask from the mask signal generation unit 5 is selected. Selector 6 that selects a signal and uses it as the mask signal for the initial alarm
In order to mask the out-of-sync signal in the initial state with the mask signal, for example, the inhibit circuit 7
Is provided.

[0012]

The synchronizing unit 3 detects the synchronizing pattern of the selected highway and performs forward protection and backward protection. The comparing unit 5 compares the phases of the synchronizing pattern detection signals by synchronizing pattern hunting. That is, the phase of the sync pattern detection signal in the previous sync pattern hunting period is compared with the phase of the sync pattern detection signal in the current sync pattern hunting period. If the comparison coincides with this comparison, it means that the normal synchronization has been entered, and therefore the first mask signal from the mask signal generator 4 is selected. That is, since the pseudo synchronization is not entered, the backward protection period shifts to the frame synchronization period, and the out-of-sync signal until the shift to the frame synchronization period is masked by the inhibit circuit 7 or the like. An out-of-sync signal after shifting to the frame synchronization period can be sent as an alarm signal. If the comparison does not match, it indicates that the pseudo-synchronization has been started, and therefore the second mask signal from the mask signal generator 4 is selected. Therefore, the out-of-sync signal during the sync pattern hunting period and the backward protection period from the pseudo sync can be masked by the inhibit circuit 7 or the like.

[0013]

FIG. 2 is a block diagram of an embodiment of the present invention.
The plurality of highways 11-1 to 11-n are selected by the selector 12 and connected to the synchronization unit 13. This synchronization unit 1
As shown in FIG. 5, reference numeral 3 includes a synchronization detection unit that detects a synchronization pattern and a synchronization protection unit that performs front protection and rear protection of synchronization. Further, the mask signal generation unit 14 includes the first mask signal MSK1 in a period including at least the synchronization pattern hunting period and the backward protection period and the second mask signal MSK1 in the period including at least the synchronization pattern hunting period, the backward protection period, and the forward protection period. The mask signal MSK2 is output.

Reference numeral 15 is a comparator, 16 is a selector, 17 is a counter, 18 is a latch circuit, 19 is a memory, 20 is a control unit, 21 is an inhibit circuit, and 22 is a reset signal applied to the reset terminal R of the synchronization unit 13. The memory 19 is a reset circuit, and the memory 19 has an address terminal ADD, a write data terminal WD, a write clock terminal WC, and a read data terminal R.
D and a read clock terminal RC. The memory 19, the counter 17, the latch circuit 18, and the comparator 15 constitute the comparison unit 5 in FIG. Then, the counter 1 latched in the latch circuit 18 by the comparator 15
By comparing the count content of 7 and the previous count content of the counter 17 stored in the memory 19, the phases of the synchronization pattern detection signals are compared.

The control unit 20 controls the selector 12 to selectively connect the highways 1-1 to 1-n and activates the mask signal generation unit 14 to activate the first and second mask signals M.
SK1 and MSK2 are generated. Also, a clock signal is added to the counter 17 to count for one frame period. An address signal corresponding to the selected highway is added to the address terminal ADD of the memory 19. Further, a configuration for outputting the write clock signal WCLK and the read clock signal RCLK can be added. The first and second mask signals MSK1 and MS from the activated mask signal generator 14.
K2 is, for example, the first mask signal MSK in the initial state.
1 is applied as a mask signal to the inhibit circuit 21 via the selector 16, and one of the first and second mask signals MSK1 and MSK2 is selected by the output signal of the comparator 15, and the inhibit circuit 21 receives the mask signal. Added as.

One highway among the plurality of highways 1-1 to 1-n is connected to the synchronization unit 13 via the selector 12, and at that time, for example, a highway switching control signal H.
A rising edge of S is detected by the reset circuit 22, and upon detection of this rising edge, a reset signal is applied from the reset circuit 22 to the reset terminal R of the synchronization section 13 to initialize the state, and a synchronization pattern hunting is performed to detect the synchronization pattern of the highways switched and connected. In the period, the synchronization pattern detection signal is added to the latch circuit 18 as a latch signal, and the next backward protection period starts. During the synchronization pattern hunting period and the backward protection period, the out-of-sync signal of "1" is applied to the inhibit circuit 21. At that time, the mask signal generator 14 is activated to activate the first and second mask signals MSK.
1, MSK2 are output, and the first mask signal MSK1 is added as a mask signal to the inhibit circuit 21 via the selector 16 in the initial state, for example, so that the alarm signal REC due to the initial out-of-synchronization signal is not output.

The counter 17 is a free-running n-ary counter, and the content of the counter indicates the phase within one frame, and the latch circuit 1 receives the sync pattern detection signal from the sync section 13 during the sync pattern hunting period.
Latched to 8. At this time, an address signal corresponding to the highway selectively connected from the control unit 20 is applied to the address terminal ADD of the memory 19, and the read clock signal RC is added.
Since LK is added to the read clock terminal RC, the previous count content of the counter 17 is the read data terminal RD.
The count content read from the counter and the count content latched in the latch circuit 18 are compared in the comparator 15. That is, the phase of the previous sync pattern detection signal and the phase of the current sync pattern detection signal are compared.

In the case of comparison and coincidence by the comparator 15, it is determined that the normal sync pattern is detected, the selector 16 is controlled, and the first mask signal MS from the mask signal generator 14 is detected.
Select and output K1. If the comparison does not match, it is determined that the pseudo synchronization has been entered, and the selector 16 is controlled to selectively output the second mask signal MSK2 from the mask signal generator 14. Then, since the latch output of the latch circuit 18 is applied to the write data terminal WD of the memory 19, the latch output is selected at the timing of the write clock signal WCLK applied to the write clock terminal WC, and is connected to the selected highway. Write to the address.

As described above, in the case of normal synchronization, the first mask signal MSK1 having a short time is selected, so that the out-of-sync signal in at least the synchronization pattern hunting period and the backward protection period can be masked. it can. In the case of pseudo synchronization, the second mask signal MSK2 having a long time is used.
Is selected, the out-of-sync signal is masked during a period including at least the synchronization pattern hunting period, the front protection period, and the rear protection period.

FIGS. 3 and 4 are diagrams for explaining the operation of the embodiment of the present invention. FIG. 3 (1) shows a plurality of highways 11-1 to 11-1.
11-n indicates monitoring periods HW1 to HWn, (2) indicates a monitoring period HW1 including a plurality of frames of the selectively connected highway 11-1, and FP indicates a synchronization pattern having a plurality of bits. Further, (3) shows a sync pattern detection signal, (4) shows the count contents of the counter 17, and (5) shows the latch output of the latch circuit 18.

In the synchronization pattern hunting period A, the synchronization unit 13 has a synchronization pattern FP shown in (2) of FIG.
When the signal is detected, the sync pattern detection signal shown in (3) is output. The sync pattern detection signal in the sync pattern hunting period A is added as a latch signal of the latch circuit 18. At that time, if the count content of the counter 17 is m as shown in (4), the count content m is latched by the latch circuit 17.

Further, (6) of FIG. 4 shows a monitoring period HW1 of a plurality of highways 11-1 to 11-n similar to (1) of FIG.
To HWn, FP indicates a synchronization pattern, PFP indicates a pseudo synchronization pattern, and A indicates a synchronization pattern hunting period. Further, (7) is the latch output of the latch circuit 18, (8) is the write clock signal WCLK, (9) is the read clock signal RCLK, and (10) is the read terminal RD of the memory 19.
The read data output from the device, (11) indicates the comparison output of the comparator 15, and (12) indicates the mask signal selected by the selector 16. Further, t1 is a period of the first mask signal MSK1 including at least a synchronization pattern hunting period and a backward protection period, and t2 is a second period including at least a synchronization pattern hunting period, a backward protection period and a forward protection period.
The period of the mask signal MSK2 is shown.

Sync pattern F in sync pattern hunting period A of monitoring period HWn of highway 11-n
When the P detection signal is obtained, the count content of the counter 17 is r, and the monitoring period HW of the next highway 11-1.
When the count content of the counter 17 when the detection signal of the sync pattern FP in the sync pattern hunting period A of 1 is obtained is m, the latch outputs of the latch circuit 18 are r and m respectively as shown in (7). Becomes And
At the timing of the write clock signal WCLK shown in (8), the latch outputs r and m of the latch circuit 18 are written to the addresses of the memory 19 corresponding to the highways 11-n and 11-1, respectively.

Next highway 11-n monitoring period HWn
When the count content of the counter 17 is r again when the detection signal of the sync pattern FP in the sync pattern hunting period A is obtained, the latch output of the latch circuit 18 becomes r, and the read clock shown in (9) Signal RCLK
At the timing of, the previous count content r is read from the address corresponding to the highway 11-n as shown in (10), and the comparator 15 compares the latch output r with the read data r. This case corresponds to the case where the phase of the previous sync pattern detection signal and the phase of the current sync pattern detection signal are the same, and the comparison output of the comparator 15 becomes "1" as shown in (11), and (12) As shown in, the mask signal generator 14 outputs the first mask signal MS in the period t1.
K1 is selectively output from the selector 16, and the out-of-sync signal in the initial state output during the synchronization pattern hunting period and the rear protection period is masked by the inhibit circuit 21.

The monitoring period HW of the next highway 11-1
The counter 1 when the detection signal of the pseudo synchronization pattern PFP is obtained in the synchronization pattern hunting period A of 1.
When the count content of 7 is x, the highway 11- is set according to the timing of the read clock signal RCLK shown in (9).
The previous count content m is read from the address corresponding to 1, and the latch output x of the latch circuit 18 and the read data m from the memory 19 are compared in the comparator 15. This case corresponds to the case where the phase of the previous sync pattern detection signal and the phase of the current sync pattern detection signal are different, and the comparison output of the comparator 15 is a comparison disagreement signal of "0" as shown in (11). Become. Therefore, the second mask signal MSK2 from the mask signal generator 14 at time t2
However, as shown in (12), the inhibit circuit 21 masks the out-of-sync signal which is selectively output from the selector 16 and includes at least the synchronization pattern hunting period, the backward protection period, and the forward protection period.

In the case of this comparison disagreement, as described in the above-mentioned conventional example, after the pseudo-synchronization, the synchronization pattern hunting period A is entered again to detect the synchronization pattern, and the synchronization at that time is detected. The count content of the counter 17 at the timing when the pattern detection signal is obtained is latched by the latch circuit 18, and this latch output is monitored in the next highway 11-2 after the monitoring period HW1 of the highway 11-1 is completed. It is written into the address corresponding to the highway 11-1 of the memory 19 by the write clock signal WCLK shown in (8) at the time of shifting to the period HW2.

As described above, since the detection phase is different between the case of normal sync pattern detection and the case of pseudo sync pattern detection, normal sync and pseudo sync are discriminated. In the case of normal sync, the mask signal is detected. The first mask signal MSK1 from the generator 14 is selected as a mask signal for the initial alarm, and in the case of pseudo synchronization, the second mask signal MSK2 from the mask signal generator 14 is selected to mask the initial alarm mask signal. As a result, it is possible to prevent unnecessary alarms from being sent out. The present invention is not limited to the embodiment shown in FIG. 2. For example, the mask signal generator 14 and the like can be realized by a soft timer function under processor control. Is what you can do.

[0028]

As described above, according to the present invention, a plurality of highways 1-1 to 1-n are sequentially selected by the selector 2, and the synchronization unit 3 performs the synchronization pattern detection and the synchronization protection. Is an initial alarm mask circuit for multiplex synchronization detection for masking an out-of-sync signal in the synchronization pattern hunting period and the backward protection period from the synchronization unit 3 of FIG. The first mask signal including the pattern hunting period and the rear protection period and the second mask signal including at least the synchronization pattern hunting period, the rear protection period, and the front protection period are output, and the comparison unit 5 outputs the synchronization pattern hunting. By comparing the phase of the sync pattern detection signal by, it is determined whether it is normal synchronization or pseudo synchronization. Select signal, in the case of the pseudo synchronization by selecting a second mask signal, and a mask signal for masking an initial alarm.

Therefore, it is possible to automatically select the first mask signal and the second mask signal in the case of normal synchronization and the case of pseudo synchronization, and use them as the mask signal of the initial alarm. There is an advantage that the synchronization detection and the synchronization protection can be stably performed by the single synchronization unit 3 for the plurality of highways 1-1 to 1-n.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is an operation explanatory diagram of a conventional example.

[Explanation of Codes] 1-1 to 1-n Highway 2 Selector 3 Synchronizing unit 4 Mask signal generating unit 5 Comparing unit 6 Selector

Claims (1)

[Claims] 1. A plurality of highways (1-1 to 1-n) are sequentially selected by a selector (2), and synchronization pattern hunting, backward protection and forward protection of the selected highways are performed by a synchronization unit (3). In an initial alarm mask circuit for multiplex synchronization detection for masking an initial alarm of the synchronizing unit (3) with a mask signal from a mask signal generating unit (4), the mask signal generating unit (4) is provided with at least the synchronization signal. A first mask signal in a period including a pattern hunting period and the backward protection period; and a second mask signal including at least the synchronous pattern hunting period, the backward protection period, and the forward protection period. And a comparison unit for comparing the phases of the synchronization pattern detection signals from the synchronization unit (3) during the synchronization pattern hunting period. 5) and the comparison match by the comparison unit (5), the first mask signal from the mask signal generation unit (4) is selected as the mask signal for masking the initial alarm, and the comparison mismatch At the time, the second signal from the mask signal generator (4)
An initial alarm mask circuit for multiple synchronization detection, comprising: a selector (6) for selecting the mask signal of (1) and masking the initial alarm.