JPH0575026A - Manufacture of resistor element - Google Patents

Abstract

PURPOSE:To completely flatten a resistor element by suppressing variation in resistance value by the heat treatment in after process, and simplifying the control of the resistance value of a polysilicon film of high resistance. CONSTITUTION:A groove having a certain curvature is made in a semiconductor substrate 1, and a thermal oxide film 4 and a nitride film 5 are formed in order, and then, a polysilicon film 6 is charged in the groove, and the polysilicon film 6 on the surface excluding the groove is removed by etchback, and further a nitride film 8 is formed on the polysilicon film 6, and a CVD film 9 is formed on this nitride film 8, and a contact window is formed on the polysilicon film 6, and aluminum wiring 10 is formed on this contact window.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a polysilicon resistance element as a substrate-embedded type to reduce electric field concentration at the corners of the resistance element to improve the breakdown voltage, and to cover the polysilicon resistance element with a nitride film. The present invention relates to a resistance element manufacturing method in which the controllability of the resistance value is simplified by suppressing the diffusion of impurities doped in the silicon film, and further the flattening that greatly contributes to the measure against the disconnection in the wiring process of the fine process is enabled. Is.

[0002]

2. Description of the Related Art Conventionally, as a resistance element, a diffusion resistance and an ion implantation resistance, which are easy to form, are often used, and it is difficult to control the resistance value of a polysilicon resistance. In most cases, it is used as a resistive element or as a high resistance of several hundred kΩ or more without doping impurities. In many circuits, it is often used as a jumper or polysilicon wiring in combination with aluminum wiring, it is rarely used as a load resistance for actual circuit configuration, and a diffusion resistance with a high sheet resistance when a high resistance load is required. Or it used the ion implantation resistance. However, in recent years, in driver driver circuits and the like, there is a case where a resistance element having a high withstand voltage and a high current capability, that is, a resistance element having a high pinch-off voltage is adopted. It is becoming more common to use silicon resistance elements as circuit loads. Hereinafter, a manufacturing method and a structure of a general high resistance element using polysilicon will be described with reference to FIGS. 7 and 8.

As shown in the figure, the semiconductor substrate 21, the thermal oxide film
Since the method of manufacturing the polysilicon resistor constituted by 22, the polysilicon film 23, the CVD oxide film 24, the aluminum electrode 25, and the step 26 is already known, it will be briefly described. First, a thermal oxide film 22 is formed on a semiconductor substrate 21 as shown in the figure, and then the surface is washed, and then LP-CV is used.
The polysilicon film 23 is grown by the D technique, impurities are doped so that the target sheet resistance value is obtained, and the back surface treatment is performed. After that, a desired patterning of the resistance element is formed by the photolithography technique and the dry etching technique. At this time, the resistance width of the resistance element is determined by its processing accuracy. After that, a CVD oxide film 24 is formed as a passivation film.
And open a contact window for electrode extraction,
Aluminum electrode 25 sputter technology, photolithography technology,
It is formed by making full use of dry etching technology.

[0004]

However, in the structure of the conventional example described above, as shown in FIGS.
The thermal oxide film 22 used for insulation between the semiconductor substrate 21 and the semiconductor substrate 21 prevents the oxide film from being destroyed by increasing the film thickness according to the voltage used in consideration of the destruction of the oxide film when forming a high voltage resistance element. Was. Also, the cross section of the formed polysilicon film 23 is rectangular as shown in FIG. 8, and in the case of a high voltage, electric field concentration occurs especially at the corners, which may cause defective resistors. was there. In addition, as a barometer that determines the resistance value, the processing accuracy of the resistance element and the change in the concentration of the doped impurities can be mentioned. The processing accuracy can be improved to some extent by the lithography technology and the dry etching technology. As is generally known, the diffusion rate of impurities in polysilicon is several orders of magnitude faster than that of silicon, and as a result, it fluctuates greatly due to heat treatment in the subsequent process, so that the resistance of the impurities in the active state is about tens of kΩ. Formation was very difficult. Also, in terms of circuit configuration,
A step is formed by the polysilicon film 23 and the underlying thermal oxide film 22 when the aluminum wiring is crossed over the polysilicon film 23. Even if the step is flattened to some extent by the CVD oxide film 24, As shown in FIG. 8, the step 26 remains, and further flattening is difficult with normal processing. If the step 26 is steep, the coverage of the sputtered aluminum deteriorates, which may cause a break in the aluminum wiring. Had a problem.

The present invention solves such a problem and suppresses the resistance value variation due to the heat treatment in the subsequent step, simplifies the resistance value control of the high resistance polysilicon film, and completely flattens the resistance element. The purpose is to plan.

[0006]

In order to solve this problem, the present invention relates to a step of forming a pattern of a resistance element on a semiconductor substrate, and a semiconductor for obtaining a desired depth and curvature using the pattern as a mask. A step of etching a substrate with silicon; a step of forming an oxide film on the silicon-etched semiconductor substrate; a step of growing a nitride film on the oxide film; and a step of growing a polysilicon film on the nitride film. A step of removing a polysilicon film and a nitride film and an oxide film deposited on a portion other than the silicon-etched portion of the semiconductor substrate by an etch-back technique to flatten the surface, and a step of growing a nitride film on the polysilicon film. A step of growing a CVD film on the nitride film, a step of opening a contact window on the polysilicon film, and an step of forming an contact window on the contact window. Miniumu wiring is made of the step of forming a.

[0007]

When the resistance element cross section is considered by the above method, the junction with the underlying semiconductor substrate has a structure with a certain curvature, so that the concentration of the electric field is prevented when the device is used with a high breakdown voltage. Can be relaxed, underlying insulating film (nitride film and oxide film here)
The impact on is also reduced. Therefore, the reliability of the resistance element itself can be improved, and the pinch-off voltage can be improved more than before. In addition, a nitride film is spread under the polysilicon film, and the upper part is also covered with the nitride film to completely wrap it so that the impurities doped in the polysilicon film are diffused into the oxide film and the CVD film. Since it is possible to suppress the impurities in the active state by the nitride film, the influence of the heat treatment on the resistance value can be reduced. Further, even when the aluminum wiring crosses over the resistance element in the circuit configuration, it is possible to form a completely flattened polysilicon film without any step by embedding the polysilicon film in the semiconductor substrate. In the case of an IC circuit or the like, it is possible to overcome disconnection in a wiring process of a fine process. In addition, the nitride film on the polysilicon film is used as an insulating film,
It is also possible to form a MIS capacitor in which the lower electrode is a polysilicon film and the aluminum electrode is attached to the upper part thereof.
It is also possible to form a capacitive element that has little voltage dependency and temperature dependency and can reduce stray capacitance.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the drawings (FIG. 1).
~ FIG. 6) will be described. First, in FIG. 1, 1 is a semiconductor substrate, 2 is a protective oxide film, and 3 is a nitride film serving as a mask for silicon etching. Also, in FIG.
Is a thermal oxide film, and 5 is a nitride film below the resistor. Next, FIG.
In the figure, 6 is a polysilicon film, and 7 is a resist for etch back. Further, in FIG. 4, 8 is a nitride film for protecting the upper part of the resistor and the surface of the semiconductor substrate. Furthermore, FIGS.
9 is CVD for an interlayer film deposited by the CVD method
Membrane, 10 is aluminum wiring (including aluminum electrode)
Is.

The manufacturing process of the above structure will be described. First, in FIG. 1, a protective oxide film 2 is grown on a semiconductor substrate 1 having a constant concentration by dry oxidation to a thickness of about 50 nm, and a nitride film 3 is formed by LP-CVD in a continuous process. After depositing
The desired depth and curvature of the polysilicon film are patterned by photolithography, and the protection oxide film 2 described above is formed.
Then, the nitride film 3 is anisotropically dry-etched with an F-based gas using the resist as a mask. In this state, the semiconductor substrate 1 is CF4 gas + 02 with the protective oxide film 2 and the nitride film 3 as a mask.
Isotropic dry etching is performed with an etching gas mainly containing gas to etch the portion a in FIG. At this time, it is desirable that the etching gas conditions are such that the selection ratio between the nitride film 3 and the protective oxide film 2 with respect to silicon is high, and that the etching rates in the vertical and horizontal directions with respect to silicon are equal. After completion of the isotropic silicon etching, the nitride film 3 used as the etching mask is removed by a wet treatment such as phosphoric acid, and the protective oxide film 2 is removed by a mixed solution of hydrofluoric acid + ammonium fluoride. The surface of the substrate 1 is completely exposed.

Next, in FIG. 2, a thermal oxide film 4 of about 50 nm is formed on the semiconductor substrate 1 by dry oxidation to recover damage from silicon etching, and then a nitride film 5 is deposited by LP-CVD. Needless to say, it is desirable that the LP-CVD apparatus used at this time has excellent coverage of the nitride film 5. Further, the film thickness of the nitride film 5 is derived from the relationship between the breakdown voltage of the nitride film 5 and the nitride film thickness according to the target resistance value of the polysilicon film 6 and the voltage used, and is determined in consideration of the film thickness variation. .. For reference, here, assuming that the operating voltage is 50 V, the nitride film thickness is about
100 nm.

Next, in FIG. 3, immediately after the deposition of the nitride film 5, a polysilicon film 6 is deposited by LP-CVD.
The polysilicon film 6 after deposition is not doped with impurities by heat treatment, but is doped with impurities by ion implantation so as to have a target resistance value. At this time, P-type impurities such as boron are preferable as N-type impurities such as arsenic, because the mobility of atoms is smaller than that of N-type impurities such that resistance variation due to heat treatment can be suppressed. Polysilicon film 6
Then, the back surface polysilicon film of the semiconductor substrate 1 is removed, a desired region is opened by a photolithography technique, and the above ion implantation is performed. After that, a thick film resist 7 is applied on the entire surface, and etching back is performed with the surface being flat. The conditions for the etch back are as follows: H with a selection ratio of the resist 7 and the polysilicon film 6 of about 1: 1.
Etching is performed with an etching gas mainly containing Br and HCl gas to remove the polysilicon film 6 on the field and expose the nitride film 5, and at the same time, an F gas is added to the etching gas to nitride the polysilicon film 6 with the etching gas. Etching is performed under the gas condition that the selection ratio of the film 5 is about 1: 1, and the gas for etching the thermal oxide film 4 is added in the state where the nitride film 5 on the field is removed, and the treatment is performed. In this way, the polysilicon film 6, the nitride film 5, and the thermal oxide film 4 on the field are completely removed, and etching is performed until the polysilicon film 6 buried in the groove of the resistance portion is exposed.
Processing is performed until the surfaces of the polysilicon film 6, the nitride film 5, the thermal oxide film 4, and the semiconductor substrate 1 are flush with each other.

Next, as shown in FIG. 4, a polysilicon film 6 is formed.
A nitride film 8 for surface protection is deposited on the upper surface of the silicon oxide film so that the polysilicon film 6 is completely covered by the nitride film 5 and the upper nitride film 8, and an oxide film of impurities doped in the polysilicon film 6 is formed. A stable resistance value can be obtained by suppressing diffusion to other areas. Next, as shown in FIGS. 5 and 6, a CVD film 9 having a constant concentration is deposited as an interlayer film on the nitride film 8 and a low-temperature short-time reflow process is performed to further flatten the flatness. The patterning of the contact window is formed by photolithography and oxide-based dry etching. At this time, the nitride film 8 on the polysilicon film 6 is also processed under the condition that it is etched, and anisotropic dry etching is performed so that no step is formed at the interface between the CVD film 9 and the nitride film 8. After the contact window is opened, aluminum is sputtered and the aluminum wiring 10 is formed by utilizing the photolithography technique and the dry etching technique. It should be noted that FIG. 6 shows that the step difference shown in FIG. 8 of the conventional example does not occur.

[0013]

As described above, according to the present invention, by forming the polysilicon film into the buried type and covering it with the nitride film, in the formation of the high resistance polysilicon film, the resistance value is stabilized regardless of the voltage used. Can realize the polysilicon film
Further improvement in pinch-off voltage can be expected. Further, by completely embedding the polysilicon film to be the resistor in the semiconductor substrate, the resistance element can be completely flattened, and the reliability of the aluminum wiring of the fine rule can be improved.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a first step of a method for manufacturing a polysilicon resistance element according to an embodiment of the present invention.

FIG. 2 is a vertical sectional view showing a second step of the method for manufacturing the polysilicon resistance element in the embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view showing a third step of the method for manufacturing the polysilicon resistance element in the embodiment of the present invention.

FIG. 4 is a vertical cross-sectional view showing a fourth step of the method for manufacturing the polysilicon resistance element in the embodiment of the present invention.

FIG. 5 is a vertical sectional view showing a fifth step of the method for manufacturing the polysilicon resistance element in the embodiment of the present invention.

FIG. 6 is a transverse sectional view of the same.

FIG. 7 is a vertical cross-sectional view of a polysilicon resistance element according to a conventional example.

FIG. 8 is a cross-sectional view of a conventional polysilicon resistance element.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Protective Oxide 3 Nitride Film 4 Thermal Oxide Film 5 Nitride Film 6 Polysilicon Film 7 Resist 8 Nitride Film 9 CVD Film for Interlayer Film 10 Aluminum Wiring

Claims (1)

[Claims] 1. A step of forming a pattern of a resistance element on a semiconductor substrate, a step of etching the semiconductor substrate with silicon so as to obtain a desired depth and curvature using the pattern as a mask, and the silicon-etched semiconductor substrate. A step of forming an oxide film on the oxide film, a step of growing a nitride film on the oxide film, a step of growing a polysilicon film on the nitride film, and a step of depositing a silicon film on the semiconductor substrate other than a silicon-etched portion. A step of removing the polysilicon film and the nitride film and the oxide film by an etch-back technique to flatten the surface; a step of growing a nitride film on the polysilicon film; a step of growing a CVD film on the nitride film; A step of forming a contact window on the polysilicon film and a step of forming an aluminum wiring on the contact window. Method for manufacturing a resistive element.