JPH0574986A - Structure of semiconductor device - Google Patents

Structure of semiconductor device

Info

Publication number
JPH0574986A
JPH0574986A JP3235085A JP23508591A JPH0574986A JP H0574986 A JPH0574986 A JP H0574986A JP 3235085 A JP3235085 A JP 3235085A JP 23508591 A JP23508591 A JP 23508591A JP H0574986 A JPH0574986 A JP H0574986A
Authority
JP
Japan
Prior art keywords
wiring
semiconductor element
heating
electrode
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3235085A
Other languages
Japanese (ja)
Inventor
Hidekazu Sato
英一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3235085A priority Critical patent/JPH0574986A/en
Publication of JPH0574986A publication Critical patent/JPH0574986A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To stabilize the hardening temperature of an adhesive for fixing by controlling the temperature of a heating tool by the temperature of a thermocouple, in respect of the hardening of the adhesive for fixing at connection of a semiconductor element. CONSTITUTION:The heating part 17 of a heating tool 15 is heated with electric resistance by letting off a current from a heating power source to the heating tool 15. At this time, the optimum hardening temperature of an adhesive 13 for fixing is preserved by estimating the thermoelectromotive force at heating of the adhesive 13 for fixing at the crossing between the first and second metallic wirings 5 and 6 which constitute the thermocouple of wiring part 4 through an external connector 9, and feeding back the estimate value to the heating source and controlling the current output. Thus, the hardening temperature of the adhesive 13 for bonding can be stabilized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体素子を配線基板
上に実装してなる半導体装置の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure in which a semiconductor element is mounted on a wiring board.

【０００２】[0002]

【従来の技術】近年液晶表示体や、ＩＣメモリーカード
等、一定面積の配線基板内に、複数の半導体素子を高密
度に、かつ薄く実装する需要が高まっている。2. Description of the Related Art In recent years, there has been an increasing demand for mounting a plurality of semiconductor elements at high density and thinly on a wiring substrate having a constant area such as a liquid crystal display or an IC memory card.

【０００３】これらの要望に応えるべき実装方法とし
て、図４に示すごとく半導体素子１０の能動面を、配線
基板１上に配設した配線パターン２の導電粒子１２を配
置した接続部３と対向して配置した後、半導体素子１０
の電極１１と接続部３を整合して固定用接着剤１３を硬
化させ半導体素子１０の電極１１と、配線基板１に配置
した配線パターン２の接続部３とを導電粒子１２により
電気的に導通をとる方法が知られている。As a mounting method to meet these demands, as shown in FIG. 4, the active surface of the semiconductor element 10 is opposed to the connecting portion 3 on which the conductive particles 12 of the wiring pattern 2 arranged on the wiring board 1 are arranged. Semiconductor device 10 after
The electrode 11 of the semiconductor element 10 and the connecting portion 3 of the wiring pattern 2 arranged on the wiring board 1 are electrically connected by the conductive particles 12 by aligning the electrode 11 and the connecting portion 3 and curing the fixing adhesive 13. It is known how to take.

【０００４】このような配線基板１と半導体素子１０と
の固定には、固定用接着剤１３をポッティングあるいは
転写印刷等の配置手段により塗布した後、半導体素子１
０の電極１１と、配線基板１の接続部３を整合して載置
し、図５の断面図のごとく図示しない上下機構を有する
加熱ツール１５を下降して半導体素子裏面１４より加
熱、押圧することにより、固定用接着剤１３を硬化させ
た後再び加熱ツール１５を上昇することによって、半導
体素子１０の電極１１と配線基板１上の配線パターン２
の接続部３との導電粒子１２による電気的な接続を可能
としていた。In order to fix the wiring board 1 and the semiconductor element 10 as described above, the fixing adhesive 13 is applied by an arrangement means such as potting or transfer printing, and then the semiconductor element 1 is applied.
The electrode 11 of 0 and the connecting portion 3 of the wiring board 1 are aligned and placed, and the heating tool 15 having an up-and-down mechanism (not shown) as shown in the sectional view of FIG. As a result, after the fixing adhesive 13 is cured, the heating tool 15 is moved up again, so that the electrode 11 of the semiconductor element 10 and the wiring pattern 2 on the wiring board 1 are formed.
It was possible to electrically connect the connection part 3 with the conductive particles 12.

【０００５】[0005]

【発明が解決しようとする課題】しかし前述の従来技術
では半導体素子の電極と、配線パターンとの接続の場
合、加熱工具の加熱分布の不均一や、半導体素子裏面の
表面状態また固定用接着剤の塗布量の不均一、基板接続
箇所の放熱状態の違い等のため固定用接着剤の硬化不良
を起こして電気的接続不良を起こし易いという問題点を
有する。However, in the above-mentioned prior art, when the electrodes of the semiconductor element are connected to the wiring pattern, the heating tool has a non-uniform heat distribution, the surface state of the back surface of the semiconductor element, and a fixing adhesive. There is a problem in that the fixing adhesive is apt to be hardened due to the non-uniform application amount, the difference in the heat radiation state at the substrate connecting portion, and the electrical connection failure is likely to occur.

【０００６】また、電気的接続不良を起こすことのない
ように、加熱工具の加熱温度を上昇した場合には、例え
ばガラスエポキシ基板のごとき樹脂基板の場合樹脂が変
質してしまうことや、ガラス基板の場合には局部的な加
熱温度による熱衝撃によりガラス基板が割れてしまう等
の問題点が発生することや、半導体素子が極端な加熱に
より破壊してしまうという問題点も発生した。Further, when the heating temperature of the heating tool is raised so as not to cause electrical connection failure, the resin may be deteriorated in the case of a resin substrate such as a glass epoxy substrate, or the glass substrate may be deteriorated. In this case, there are problems that the glass substrate is broken by thermal shock due to local heating temperature and that the semiconductor element is destroyed by extreme heating.

【０００７】そこで本発明はこのような問題点を解決す
るために為されたものであり、その目的は基板上に接続
した半導体素子を接続する場合に、熱安定性の良い加熱
が可能となり、固定用接着剤の硬化に適した加熱温度を
得ることの出来る構造を有する半導体装置の実装構造を
提供するところにある。Therefore, the present invention has been made to solve such a problem, and an object thereof is to enable heating with good thermal stability when connecting semiconductor elements connected on a substrate, Another object of the present invention is to provide a mounting structure of a semiconductor device having a structure capable of obtaining a heating temperature suitable for curing a fixing adhesive.

【０００８】[0008]

【課題を解決するための手段】本発明の半導体装置の構
造は、半導体素子の電極と、配線基板上の半導体素子の
電極と対向した配線パターンの接続部とを、導電粒子を
介して接続するために、半導体素子の能動面と対向した
回路基板上に、配線基板の配線パターンと接しない配線
部を配置し、該配線部は交差点を有する２種類の金属配
線により形成され、それぞれの金属配線の他端は半導体
素子の配置範囲の外部に位置して外部接続端子とした。According to the structure of a semiconductor device of the present invention, an electrode of a semiconductor element and a connection portion of a wiring pattern facing the electrode of the semiconductor element on a wiring board are connected via conductive particles. For this purpose, a wiring portion which is not in contact with the wiring pattern of the wiring board is arranged on the circuit board facing the active surface of the semiconductor element, and the wiring portion is formed by two kinds of metal wirings having intersections, and the respective metal wirings are formed. The other end was located outside the range of arrangement of the semiconductor elements to serve as an external connection terminal.

【０００９】[0009]

【作用】本発明の構成によれば、半導体素子の能動面と
対向した回路基板上に、配線基板の配線パターンと接し
ない配線部を配置し、該配線部は白金と白金９０％ロジ
ウム１０％の合金、白金と白金８７％ロジウム１３％、
クロメルとアルメル、銅とコンスタンタン、クロメルと
コンスタンタン等の２種類の金属を用い、２種の金属は
交差点を有し形成したことから、２種ぞれぞれの金属配
線の他端である半導体素子配置範囲の外部に位置した外
部接続端子部に電圧計を接続することで交差点での熱起
電力を検出することが可能となる。これにより、配線基
板上に半導体素子を搭載し、固定用接着剤を硬化する場
合には、交差点での熱起電力を測定しながら加熱温度を
設定することにより固定用接着剤の最適硬化条件での硬
化が可能となる。According to the structure of the present invention, the wiring portion which is not in contact with the wiring pattern of the wiring substrate is arranged on the circuit substrate facing the active surface of the semiconductor element, and the wiring portion is made of platinum and platinum 90% and rhodium 10%. Alloy, platinum and platinum 87% rhodium 13%,
Since two kinds of metals such as chromel and alumel, copper and constantan, and chromel and constantan are used and the two kinds of metals have intersections, they are semiconductor elements which are the other ends of the two kinds of metal wirings. By connecting a voltmeter to the external connection terminal portion located outside the arrangement range, it becomes possible to detect the thermoelectromotive force at the intersection. As a result, when the semiconductor element is mounted on the wiring board and the fixing adhesive is cured, the heating temperature is set while measuring the thermoelectromotive force at the intersection, and the optimum curing conditions for the fixing adhesive are set. Can be cured.

【００１０】[0010]

【実施例】図１は本発明の実施例における配線基板の正
面図であり、１は配線基板、２は配線パターン、３は半
導体素子の電極と対向して配置された配線パターン２の
接続部である。４は配線部であり、第１の金属配線５と
第２の金属配線６より構成され、第１の金属配線５と第
２の金属配線６は配線パターン２と接しないように半導
体素子の配置範囲７の内側に配設した。第１の金属配線
５と、第２の金属配線６は配置範囲７の内側で互いに交
差して交差点８を形成している。配線部４の外部接続端
子９は、半導体素子の配置範囲７の外部に配線部４を延
長して配置した。1 is a front view of a wiring board according to an embodiment of the present invention, in which 1 is a wiring board, 2 is a wiring pattern, and 3 is a connection portion of a wiring pattern 2 which is arranged so as to face an electrode of a semiconductor element. Is. Reference numeral 4 denotes a wiring portion, which is composed of a first metal wiring 5 and a second metal wiring 6, and a semiconductor element is arranged so that the first metal wiring 5 and the second metal wiring 6 are not in contact with the wiring pattern 2. It was arranged inside the range 7. The first metal wiring 5 and the second metal wiring 6 intersect each other inside the arrangement range 7 to form an intersection 8. The external connection terminals 9 of the wiring portion 4 are arranged by extending the wiring portion 4 outside the arrangement area 7 of the semiconductor element.

【００１１】配線基板１にはガラス製の液晶表示体パネ
ルを用い、ガラス製の配線基板１上に透明導電膜（ＩＴ
Ｏ）へニッケルメッキを施した配線パターン２を配置し
た。また、配線部４の第１の金属配線５はアルメルをス
パッタすることにより形成し、次に交差点８を形成する
ように第２の金属配線６としてクロメルをスパッタする
ことにより形成した。これにより、第１の金属配線５と
第２の金属配線６は、交差点８で接続される。A liquid crystal display panel made of glass is used as the wiring board 1, and a transparent conductive film (IT) is formed on the wiring board 1 made of glass.
The wiring pattern 2 in which nickel plating was applied to (O) was arranged. Further, the first metal wiring 5 of the wiring portion 4 was formed by sputtering alumel, and then was formed by sputtering chromel as the second metal wiring 6 so as to form the intersection 8. As a result, the first metal wiring 5 and the second metal wiring 6 are connected at the intersection 8.

【００１２】このような配線基板１を用いた半導体装置
の構造を図２の断面図により説明する。１０は半導体素
子、１１は半導体素子１０の電極で、配線パターン２の
半導体素子１０の電極１１と対向して配置された接続部
３と接続している。４は配線部で、第１の金属配線５及
び、第２の金属配線６よりなり、交差点８を形成してい
る。配線部４の他端は外部接続端子となる。１２は導電
粒子、１３は固定用接着剤である。配線基板１上に配置
された配線パターンと、半導体素子１０の電極１１は、
導電粒子１２により、電気的に導通がとられており、配
線基板１と、半導体素子１０は、固定用接着剤１３によ
り固定されている。The structure of a semiconductor device using such a wiring board 1 will be described with reference to the sectional view of FIG. Reference numeral 10 is a semiconductor element, 11 is an electrode of the semiconductor element 10, and the electrode is connected to the connection portion 3 of the wiring pattern 2 which is arranged to face the electrode 11 of the semiconductor element 10. A wiring portion 4 is composed of a first metal wiring 5 and a second metal wiring 6, and forms an intersection 8. The other end of the wiring portion 4 becomes an external connection terminal. Reference numeral 12 is a conductive particle, and 13 is a fixing adhesive. The wiring pattern arranged on the wiring board 1 and the electrode 11 of the semiconductor element 10 are
Electrical connection is established by the conductive particles 12, and the wiring board 1 and the semiconductor element 10 are fixed by a fixing adhesive 13.

【００１３】図３の断面図により、本発明の半導体装置
の製造方法を説明する。配線基板１の接続部上に導電粒
子１２を配置し、配線部４上に固定用接着剤１３を塗布
した後、接続部と、半導体素子１０の電極１１を整合す
る。半導体素子裏面１４より加熱ツール１５により接続
に必要な圧力を確保した後、配線部４の外部接続端子９
に電圧測定端子１６を接続する。今回は電圧測定端子の
材質にもアルメル及びクロメルの端子を用い電圧検出を
行うこととした。A method of manufacturing a semiconductor device according to the present invention will be described with reference to the sectional view of FIG. After the conductive particles 12 are arranged on the connection portion of the wiring board 1 and the fixing adhesive 13 is applied on the wiring portion 4, the connection portion and the electrode 11 of the semiconductor element 10 are aligned. After the pressure necessary for connection is secured from the back surface 14 of the semiconductor element with the heating tool 15, the external connection terminal 9 of the wiring section 4 is connected.
The voltage measuring terminal 16 is connected to. This time, we decided to detect voltage by using alumel and chromel terminals as the material of the voltage measurement terminal.

【００１４】図示しない加熱電源より加熱ツール１５に
電流を流すことにより、加熱ツールの加熱部１７を電気
抵抗加熱することができる。この時外部接続端子９を介
して配線部４の第１の金属配線５と第２の金属配線６の
交差点８で固定用接着剤１３加熱時の熱起電力を測定
し、その測定値を図示しない加熱電源に帰還して電流出
力を制御することで固定用接着剤１３に最適な硬化温度
を保持することが可能となる。By supplying a current to the heating tool 15 from a heating power source (not shown), the heating portion 17 of the heating tool can be electrically resistance heated. At this time, the thermoelectromotive force when the fixing adhesive 13 is heated is measured at the intersection 8 of the first metal wiring 5 and the second metal wiring 6 of the wiring portion 4 via the external connection terminal 9, and the measured value is shown in the figure. By returning to the heating power source and controlling the current output, it is possible to maintain the optimum curing temperature for the fixing adhesive 13.

【００１５】以上により、固定用接着剤１３を加熱硬化
した後、加熱電流を遮断し、電圧測定端子１６を外部接
続端子９より離し加熱ツール１５を引き上げることで半
導体素子１０の電極１１と、配線基板１の配線パターン
２との導電粒子１２による接続を終了する。As described above, after the fixing adhesive 13 is heated and hardened, the heating current is interrupted, the voltage measuring terminal 16 is separated from the external connection terminal 9, and the heating tool 15 is pulled up, and the electrode 11 of the semiconductor element 10 and the wiring. The connection between the wiring pattern 2 on the substrate 1 and the conductive particles 12 is completed.

【００１６】以上説明した実施例においては、半導体素
子の電極と配線基板の電気的な接続に導電粒子を用い、
配線基板にはガラス基板を用いて説明したが、半導体素
子の電極としてバンプと呼ばれる突起電極を用いたり、
また配線基板として、アルミナセラミック基板等のセラ
ミック基板や、ガラスエポキシ積層基板等を用いても固
定用接着剤の硬化のために、配線基板上に配置した配線
部の交差点で加熱時の熱起電力を測定し加熱電源に測定
値を帰還する半導体装置の構造は本発明に含まれる。In the embodiments described above, conductive particles are used for electrical connection between the electrodes of the semiconductor element and the wiring board,
Although the glass substrate is used as the wiring substrate, a bump electrode called a bump is used as an electrode of the semiconductor element,
Even if a ceramic substrate such as an alumina ceramic substrate or a glass epoxy laminated substrate is used as the wiring substrate, the thermoelectromotive force at the time of heating is applied at the intersection of the wiring portions arranged on the wiring substrate due to the curing of the fixing adhesive. The present invention includes a structure of a semiconductor device that measures the temperature and returns the measured value to the heating power source.

【００１７】[0017]

【発明の効果】以上述べたごとく本発明の半導体装置の
構造によれば、半導体素子の電極と、半導体素子の電極
と対向する位置に配線パターンを有する配線基板からな
り、半導体素子の電極と、配線パターンとを電気的に接
続することからなる半導体装置の構造において、配線基
板の、半導体素子の能動面と対向する位置に、配線パタ
ーンと接しない配線部を配置し、配線部は交差点を有す
る２種類の金属配線により形成されそれぞれの金属配線
の配線部より延長した配線部の外部接続端子は、半導体
素子の配置範囲の外部に有することにより、外部接続端
子を通して交差点の熱起電力を計測することが出来る。As described above, according to the structure of the semiconductor device of the present invention, the electrode of the semiconductor element and the wiring board having the wiring pattern at the position facing the electrode of the semiconductor element are provided. In a structure of a semiconductor device that is electrically connected to a wiring pattern, a wiring portion that does not contact the wiring pattern is arranged at a position facing the active surface of a semiconductor element of a wiring substrate, and the wiring portion has an intersection. Since the external connection terminals of the wiring portion formed of two types of metal wiring and extending from the wiring portions of the respective metal wirings are provided outside the semiconductor element arrangement range, the thermoelectromotive force at the intersection is measured through the external connection terminals. You can

【００１８】これにより、加熱工具による半導体素子裏
面よりの加熱接続の場合交差点に発生する熱起電力を計
測して加熱温度を制御することや、熱起電力の計測値を
加熱電源に帰還しての加熱制御を行うことができるた
め、固定用接着剤の最適硬化条件での硬化を行うことが
可能となる。また、最適硬化条件を得ることが可能とな
る結果、ガラスエポキシ基板等の樹脂基板の場合ありが
ちだった樹脂の変質や、ガラス基板の場合の局部的な加
熱温度の上昇によるガラス基板の割れ及び極端な加熱に
よる半導体素子の破壊等を防ぐ効果を有する。Thus, in the case of heating connection from the back surface of the semiconductor element by a heating tool, the thermoelectromotive force generated at the intersection is measured to control the heating temperature, and the measured value of the thermoelectromotive force is returned to the heating power source. Since the heating control can be performed, it becomes possible to cure the fixing adhesive under optimum curing conditions. In addition, as a result of being able to obtain the optimum curing conditions, there is a change in the resin that was often the case with resin substrates such as glass epoxy substrates, and glass substrate cracks and extremes due to the local increase in heating temperature. It has an effect of preventing a semiconductor element from being destroyed due to excessive heating.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例を示す配線基板の正面図。FIG. 1 is a front view of a wiring board showing an embodiment of the present invention.

【図２】本発明の半導体装置の構造を示す断面図。FIG. 2 is a cross-sectional view showing a structure of a semiconductor device of the present invention.

【図３】本発明の半導体装置の製造方法を説明するため
の断面図。FIG. 3 is a sectional view for explaining the method for manufacturing a semiconductor device of the present invention.

【図４】従来の半導体装置の構造を示す断面図。FIG. 4 is a sectional view showing the structure of a conventional semiconductor device.

【図５】従来の半導体装置の製造方法を説明するための
断面図。FIG. 5 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

１ 配線基板 ２ 配線パターン ３ 接続部 ４ 配線部 ５ 第１の金属配線 ６ 第２の金属配線 ７ 配置範囲 ８ 交差点 ９ 外部接続端子 １０ 半導体素子 １１ 電極 １２ 導電粒子 １３ 固定用接着剤 １４ 半導体素子裏面 １５ 加熱ツール １６ 電圧測定端子 １７ 加熱部 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Wiring pattern 3 Connection part 4 Wiring part 5 First metal wiring 6 Second metal wiring 7 Arrangement range 8 Intersection point 9 External connection terminal 10 Semiconductor element 11 Electrode 12 Conductive particle 13 Fixing adhesive agent 14 Semiconductor element back surface 15 Heating Tool 16 Voltage Measuring Terminal 17 Heating Section

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の電極と、前記半導体素子の
電極と対向する位置に、配線パターンを有する配線基板
からなり、前記電極と、配線パターンを電気的に接続す
ることからなる半導体装置の、半導体素子の能動面と対
向する位置に、前記配線パターンと接しない配線部を配
置し、前記配線部は交差点を有する２種類の金属配線に
より形成され金属配線の他端に配置した外部接続端子部
は前記半導体素子の配置範囲の外部に有することを特徴
とする半導体装置の構造。1. A semiconductor device comprising an electrode of a semiconductor element and a wiring board having a wiring pattern at a position facing the electrode of the semiconductor element, and electrically connecting the electrode and the wiring pattern, An external connection terminal portion, in which a wiring portion not in contact with the wiring pattern is arranged at a position facing the active surface of the semiconductor element, and the wiring portion is formed by two kinds of metal wiring having intersections and arranged at the other end of the metal wiring. Is provided outside the range of arrangement of the semiconductor element. 【請求項２】 前期２種類の金属配線は、白金と白金・
１０％ロジウム、白金と白金１３％ロジウム、クロメル
とアルメル、銅とコンスタンタン、クロメルとコンスタ
ンタン等の熱起電力を測定しやすい組合せの金属配線と
することを特徴とする請求項１記載の半導体装置の構
造。2. The first two types of metal wiring are platinum and platinum.
2. The semiconductor device according to claim 1, wherein the metal wiring is a combination of 10% rhodium, platinum and platinum 13% rhodium, chromel and alumel, copper and constantan, chromel and constantan, etc., in which thermoelectromotive force can be easily measured. Construction.
JP3235085A 1991-09-13 1991-09-13 Structure of semiconductor device Pending JPH0574986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3235085A JPH0574986A (en) 1991-09-13 1991-09-13 Structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3235085A JPH0574986A (en) 1991-09-13 1991-09-13 Structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0574986A true JPH0574986A (en) 1993-03-26

Family

ID=16980849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3235085A Pending JPH0574986A (en) 1991-09-13 1991-09-13 Structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0574986A (en)

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